JPS58147253A - Error correcting device of digital information signal - Google Patents

Abstract

PURPOSE:To correct an error of PCM-modulated digital data through the mean value interpolation of a circuit of simple constitution, by providing a mean value calculating circuit and plural switches which are controlled according to the error states of two succeeding data. CONSTITUTION:After being held in an N-bit register 10 by one timing block, N-bit parallel PCM data is supplied to the mean value calculating circuit 15 through an N-bit register 13 and the network consisting of N units of switches 11, 12, 14, and 16. The output of the circuit 15 is supplied as corrected PCM data to a register 17. An error detection signal regarding the input data, on the other hand, is supplied to one-bit registers 18 and 19 successively and the switches 11, 12, 14, and 16 are controlled by the error detection signal as shown in a table. Consequently, the PCM data containing the error is corrected by being replaced by the mean value of correct PCM data before and after the error data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital information signal correction device for correcting error data in a PCM digital information signal to improve the fidelity of a reproduced analog signal.

A PCM (pulse coat modulation) system that converts an analog information signal such as an audio signal into a binary code, transmits it or records it on a recording medium, receives it or reproduces it, decodes it, and obtains the original analog information signal again. In this case, if there is an error in the received or reproduced binary code data, the analog signal obtained by decoding will be different from the original analog signal. In particular, if the upper bits in the binary code are incorrect, large pulse-like noise will appear in the reproduced analog signal. In order to avoid such undesirable phenomena, noise is generally reduced by transmitting check bits for error detection along with binary data to determine whether there are errors in the reproduced data and correcting the errors. Ru. In this case, if an error correction code is recorded and transmitted together with the data, an operation is performed to correct the erroneous data to correct data, and when correction is impossible, error correction is performed.

A relatively simple method for correcting this error is the average value interpolation method (
The linear interpolation method) is well known. In this method, when there is an error in the data of a certain sample value, the average value of the correct sample value immediately before and the correct sample value immediately after this sample value is calculated and used in place of the erroneous data.

There is an apparatus described in Japanese Patent Application Laid-open No. Sho 56-78256 as an error correction apparatus for a PCM digital information signal which can perform practical and sufficient correction using this average value interpolation method and has a small number of circuit elements. When an error occurs in binary data of a predetermined number of bits representing one sample value, this device attempts to correct only the upper bit group that has a large effect on the reproduced decoded signal. A configuration in which data corresponding to the average value of each corresponding upper focus group of the immediately preceding correct data and the correct data following the error data is calculated, and this average data is replaced with the corresponding upper bit group of the error data. It has become. However, such an apparatus has the disadvantage that, if it attempts to process data of 16 bits per sample in units of bytes (8 bits), the structure becomes complicated and the number of circuit elements increases.

Further, when changing the processing unit such as processing data of 1 sample and 16 pits in bytes, if it is not desired to change the number of data that can be processed within a unit time, it is necessary to increase the speed of circuit operation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an error correction apparatus for digital information signals that can cope with changes in processing units without complicating the structure, has a simple structure, and can operate at high speed.

The error correction device according to the present invention has a first data supply circuit that supplies only correct data and two input terminals, and calculates and generates data corresponding to the average value of the data respectively supplied to the two input terminals. An average value calculation circuit and a first
A data storage circuit temporarily stores data supplied from a data supply circuit and supplies the stored data to one input terminal of the average value calculation circuit, and an error detection signal storage circuit indicates that the storage contents of the error detection signal storage circuit indicate the arrival of incorrect data. a first circuit that is turned on and causes the output of the data storage circuit to be supplied to its input only when
A second switch circuit is connected between the two input terminals of the average value calculation circuit and turns off only when correct data arrives following the error data; and a second data supply circuit that supplies the calculated data to the other input terminal of the average value calculation circuit, and the calculation result in the average value calculation circuit is configured to be output data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a part of a general PCM decoder. A clock signal extraction circuit 1 and a timing control circuit 2 generate a clock signal synchronized with the data from an input PCM data signal. Data is extracted in the data extraction circuit 3 using the clock signal. Error detection circuit 4 detects erroneous data, adds an error indication bit signal indicating the presence or absence of an error, and writes it into memory 5. The memory 5 is configured so that data representing one sample value is stored as parallel data, and memory writing control is performed based on a control signal from the timing control circuit 2. Reading from the memory is performed based on the clock signal generated by the reference clock signal generation circuit 6, and by writing to and reading from the memory using independent clock signals, temporal fluctuations in the input PCM data signal can be reduced. Corrections are made. The data read from the memory is corrected by the error correction circuit 7, then input to the D/A converter 8, where it is converted into an analog signal, and thereafter analog processing is performed appropriately. Incidentally, reference numeral 9 denotes a timing control circuit that generates a timing signal for controlling the memory 5, the error correction circuit 7, and the D/A converter 8 in accordance with the clock signal from the reference clock signal generation circuit 6.

FIG. 2 is a block diagram showing an embodiment of the present invention of the error correction circuit 7 in the PCM decoder shown in FIG. In FIG. 2, an N-bit parallel binary data signal is applied to an N-bit parallel register 1o for temporarily storing each of these bits in parallel. The register 10 temporarily stores the supplied data using a first predetermined clock generated every time input data arrives. This register 1
o and is supplied to the switch circuit 12 as a second data supply circuit. The switch circuits 11 and 12 are both formed of N analog switches each having one input/output terminal supplied with a signal corresponding to each bit in the output of the register 1o, and each control input terminal being commonly connected. . An N-bit parallel binary data signal is supplied from the other input/output terminal of the N analog switches forming the switch circuit 11 to an N-bit parallel register 13 serving as a data storage circuit. Register 13, like register 1o, temporarily stores supplied data using a first predetermined clock. A switch circuit 14 is connected between the input terminal and output terminal of this register 13. Also,
The output of the register 13 is input to the average value calculation circuit 150 input terminal B.
It is also supplied to the input terminal A of the average value calculation circuit 15 via the switch circuit 16. switch circuit 1
4 and 16 have the same configuration as the switch circuit 11 or 12. An N-bit parallel binary data signal is also supplied to the input terminal A of the average value calculation circuit 150 from the other input/output terminal of the N analog switches forming the switch circuit 12. In the average value calculation circuit 15, the input terminal A
, B is calculated and supplied to the N-bit parallel register 17. Register 17, like register 10 or 13, temporarily stores supplied data using a first predetermined clock.

The output of this register 17 is used as an error-corrected data output.

On the other hand, error detection signals are used for on/off control of the switch circuits 11, 12, 14, and 16.

That is, a 1-pit register 18 for temporarily storing the error detection signal and a 1-pit register 19 for temporarily storing the output thereof are provided. Both registers 18 and 19 temporarily store data supplied by the first predetermined clock or another clock whose repetition frequency is the same as that of the first predetermined clock and whose occurrence time is different from that of the first predetermined clock. The outputs of the registers 18 and 19 are then supplied to a control signal generation circuit (not shown). This control signal generation circuit includes switch circuits 11 and 12 as shown in Table 1.
, 14.16 are determined by supplying a control signal to the commonly connected control input terminals of the analog switches in each switch circuit.

In the configuration shown in Table 1 and above, all N points forming one sample value in the input data are temporarily stored in the register 10 at the same time. Further, an error detection signal corresponding to the stored input data is stored in the register 18, and an error detection signal corresponding to the input data immediately before the input data stored in the register 10 is shifted from the register 18 to the register 19. be done. When the stored contents of these registers 18 and 19 are both So'', that is, when the input data that has arrived is continuously correct, switch circuits 11 and 16 are turned on and switch circuits 12 and 14 are turned off.

Then, when the calculation result of the average value calculation circuit 15 is the output data sheath of the register 13, (xrL+xn)/2
= xn, the output data of the register 13 is supplied as is to the register 17, and the input data is the first
Register 10゜13 at the predetermined clock generation timing
, 17 in sequence.

Next, when an error occurs in the input data and the error data is temporarily stored in register 1o, the storage contents of register 18 becomes 9'' and the storage contents of register 19 reaches 10#, switch circuits 11 and 12 are activated. is turned off and the switch circuits 14 and 16 are turned on.At this time, the register 10
The error data stored in the register 13 and the correct data immediately before the error data stored in the register 13 are
If xrrLl, the output data xy, -1 of the register 13 is supplied to the input terminal of the register 130 by the action of the switch circuit 14, and the data output from the average value calculation circuit 15 also becomes xrrv-1:. Therefore, assuming that the next input data is xm+i and there is no error in data "m+1," the stored contents of registers 10, 13, and 17 are updated at the timing of the first predetermined clock to become xm+t + xm-t, respectively.

$m-1, and the previous correct data xm-1 is stored in the register 13 instead of the error data x,1. As the storage contents of these registers 10 and 13.17 are updated, the storage contents of registers 18 and 19 are also updated, and the storage contents of registers 18 and 19 become 10" and 11#, respectively. Then, the switch circuit 1
1 and 12 are turned on and switch circuits 14 and 16 are turned on.
is turned off, data xm+1 is supplied from the register 10 to the input terminal A of the average value calculation circuit 150 by the action of the switch circuit 12, and data xm+1 is supplied to the input terminal B from the register 10.
Data xm-1 will be supplied from 3. Therefore, the average value calculation circuit 15 calculates (xrn+1+xm
-1)/2 is supplied to the register 17. Therefore, when the next input data is xm+2, the contents of registers 10, 13 and 17 are updated at the timing of the first predetermined clock, and become "77Z+2 +xm+l".
+ (xm+ 1 +xm −2)/2, and data corrected for errors by the average value interpolation method is output from the register 17.

Next, errors occur continuously in the input data, and the register 18
, 19 become V"1", switch circuits 11 and 12 are turned off, switch circuits 14 and 16 are turned on, and the stored contents of registers 18 and 19 become -]", "0#, respectively. The state is the same as when . Therefore, the data immediately preceding the error data is continuously output from the register 17. Thereafter, when correct data arrives, the contents stored in the registers 18 and 19 become 10'' and 10'', respectively, and error correction is performed by the average value interpolation method, completing correction of all error data.

Here, the configuration of the average value calculation circuit 14 that calculates the average value differs depending on the expression format of the binary code, but for example, if the offset binary code expression format is as shown in Table 2, a circuit as shown in FIG. 2 is used. It is possible to use To find the average value of two offset binary encoded numbers, add the two numbers and carry.
The result including the bits may be shifted one bit to the right (LSB) direction.

Table 2 For example, the average value of 1 and 3 in decimal notation (1++S)
/2=2 is determined by the offset binary code as follows.

The same applies to other numbers. However, the numbers below the decimal point shall be rounded down if the result is a positive number, and rounded up if the result is a negative number. Therefore, as shown in Fig. 3, an N-bit full adder is used, its carry input terminal CIN is grounded, and the carry output (COUT) is set as the MSB of the average value data, and the M of the addition result is
SB (SN) is set as MSB-1 bit, and then the second bit (S2) of the addition result is set as LSB by sequentially shifting 1 bit at a time.
It would be a good idea to do this.

In the above embodiment, it is assumed that input data consisting of one sample data for one channel arrives continuously, but if data for multiple channels arrives sequentially by time division multiplexing, N-bit parallel data storage circuit is used. In addition to register 13, N-bit parallel registers are connected in series to register 13 for the increase in the number of channels, and in addition to step 19, a 1-bit register is connected between registers 18 and 19 for the increase in the number of channels. They may be connected in series to hold error information of data temporarily stored in the register 10 and the data storage circuit.

Furthermore, in the above embodiment, all bits forming one data were processed at the same time, but in the error correction device according to the present invention, it is possible to perform error correction by processing data in units of an arbitrary number of bits. can. The circuit in Figure 4 is 1
Error correction is performed by processing 6-bit parallel data in units of bytes (8 pits). In FIG. 4, switch circuits 11, 12, 14, 16, average value calculation circuit 1
5 and registers 18 and 19 are connected in the same manner as in FIG. However, in this example, the switch circuit 11
, 12, 14, and 16, and the average value calculation circuit 15 is formed by an 8-bit full adder. Further, both registers 10 and 13 have an 8-pin parallel register configuration, and 8-bit parallel registers 20 and 21 are connected in series to registers 10 and 13, respectively. Registers 10, 13, 20, 2] temporarily store one upper byte or one lower byte of data supplied by a second predetermined clock generated with a repetition frequency twice that of the first predetermined clock. The output of the register 20 is supplied to the switch circuits 11 and 12, and the output of the register 21 is supplied to the input terminal B of the average value calculation circuit 15 and the input terminal A of the average value calculation circuit 150 via the switch circuit 16. The signal is supplied to the register 13 via the switch circuit 14. Also, register 17 is 9
It has a bit parallel register configuration. The addition output Σ and carry output (C0UT) of the 8-bit full adder forming the average value calculation circuit 15 are such that the carry output is the MSB.
Then, the addition output is applied to the register 16 so as to form the following 8 pins. The 7 bits excluding the LSB in the addition output of the 8-bit full adder are applied to the 7-bit parallel register 22. A second predetermined clock is alternately supplied to registers 17 and 22, and registers 17 and 22 temporarily store the output of the 8-bit full adder alternately. The output of this register 17 forms the upper 9 bits of the output data, and the output of the register 22 forms the lower 7 pins of the output data.

The carry output of the 8-bit full adder is 1-bit register 2.
3. 1 bit register 23 has register 2
2, a second predetermined clock is supplied at the same time as register 22 temporarily stores the addition output, and at the same time register 23 temporarily stores the carry output. The output of this register 23 is applied to the carry input terminal CIN of the 8-bit full adder.

In the above configuration, each time the second predetermined clock occurs, the lower 1 byte and the upper 1 byte are sequentially processed, and each time this second predetermined clock occurs twice, it is processed in the same way as the circuit in Figure 2. Error correction for one data is performed in this way.

The circuit shown in FIG. 5 corrects errors by processing data bit by bit in time series. In FIG. 5, registers 1o, ! 3, 18, 1c+, switch circuits 11, 12, 14, 16 and average value calculation circuit 15
are connected in the same way as in FIG. However, in this example, both registers 10 and 13 have a 1-via register configuration. And these registers 10°1
3 temporarily stores bits supplied by a third predetermined clock generated with a repetition frequency 16 times that of the first predetermined clock.

Further, the number of analog switches forming each of the switch circuits 11, 12, 14, and 16Q is one, and the average value calculation circuit 14 is formed by a 1-bit full adder. The addition output Σ of this 1-pit full adder is 3
It is supplied via a state buffer gate 24 to a serial-parallel converter 25 consisting of a 16-bit shift register or the like. Carry output (COUT) of 1-pit full adder
is supplied to the 1 pit register 26. A third predetermined clock is supplied to the serial/parallel converter 25 and this register 26, and the register 26 temporarily stores the carry output at the timing of generation of the third predetermined clock. The output of this register 26 is supplied to the carry input terminal CIN of the 1-bit full adder and also supplied to the serial-parallel converter 25 via the 3-state buffer gate 27.

A carry output corresponding to the MSB of the output data is input to each control input terminal of the buffer gates 24 and 27 to the register 25.
For example, the carry output of a hexadecimal counter (not shown) is incremented by a third predetermined clock so that only the buffer gate 27 among the buffer gates 24 and 27 is activated when the data is temporarily stored, and its inverted signal. are supplied respectively.

In the above configuration, input data is input in order from LSB to
The bits up to SB are sequentially supplied to the register 10 in chronological order. Switch circuits 11, 12, 14, 16
operates according to the contents stored in the registers 18 and 19 in the same way as the circuit shown in FIG. Then, the addition output of the l-bit full adder is sequentially applied from the LSB+1st bit to the MSB to the serial-parallel converter 25 via the buffer gate 24, and then the carry output corresponding to the MSB of the output data is temporarily stored in a register. The output of 26 is applied to the serial-to-parallel converter 25 via a buffer gate 27. The 16-pit parallel data output from the serial-parallel converter 25 is used as error-corrected data.

As described in detail above, the error correction device according to the present invention can perform N-bit parallel processing, processing in units of an arbitrary number of bits, and
A switch circuit 11 is capable of performing any of the 1-bit serial processing, and is turned on when correct data following error data arrives to switch the output of the register 10.
Since the switch circuit 12 is provided to directly supply the signal to the average value calculation circuit 15 without going through either of the signals 14 and 16, there is little signal delay caused by the switch circuit, etc., and high-speed operation is possible. Therefore, according to the present invention, it is possible to optimize the system by arbitrarily setting the processing unit in consideration of the required number of channels, system operating speed, complexity of peripheral circuits, etc. Switch circuits 11, 12, 14, 16 are MO
Since the error correction device according to the present invention can be easily realized using eight field effect transistors or the like, it is suitable for implementation as an IC. Further, in the error correction device according to the present invention, since the switch circuit 12 is provided, the switch circuit 1
This also means that there is no need to use a bidirectional device as the fourth option.

[Brief explanation of drawings]

FIG. 1 is a partial block diagram of a decoding device including a general PCM signal error correction circuit, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram of a decoding device including a general PCM signal error correction circuit. FIG. 4 is a circuit block diagram showing another embodiment of the present invention, and FIG. 5 is a circuit block diagram showing still another embodiment of the present invention. Explanation of symbols of main parts 10, 13, 17, 18, 19, 20, 2
1, 22, 23, 25, 26...
...Registers 11, 12, 14, 16
・・・Switch circuit 15 ・・・・・・・・・
...Average value calculation circuits 24, 27...
...Buffergate applicant Motohiko Fujimura, agent of Pioneer Co., Ltd., patent attorney

Claims (1)

[Claims] An error correction device that detects error data in a digital information signal in which each piece of data is composed of predetermined bits, generates an error detection signal, and corrects the error data in response to the error detection signal, the error correction device comprising: an error detection signal storage circuit that temporarily stores the error detection signals corresponding to at least two pieces of the individual data; and an error detection signal storage circuit that temporarily stores the error detection signals corresponding to at least two pieces of the individual data; an average value calculation circuit having two input terminals and calculating and generating data corresponding to an average value of data respectively supplied to the two input terminals; and the first data supply circuit. A data storage circuit temporarily stores data supplied from the circuit and supplies the stored data to one input terminal of the average value calculation circuit, and the storage contents of the error detection signal storage circuit indicate the arrival of incorrect data. a first circuit that is turned on only when
a second switch circuit connected between the two input terminals of the average value calculation circuit and turned off only when the memory contents of the error detection signal storage circuit indicate the arrival of correct data following error data; and a second data supply circuit that supplies the individual data to the other input terminal of the average value calculation circuit only when the storage contents of the error detection signal storage circuit indicate the arrival of correct data following the error data. An error correction device for a digital information signal, characterized in that the calculation result in the average value calculation circuit is used as output data.