JPH0511474B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error correction circuit using a so-called cyclic code.

[Background of the invention]

Figure 1 is a block diagram showing an example of a general error correction system, which is used for so-called character code broadcasting (Yamada et al. 1: "Results of Field Experiments on Error Correction Codes for Character Code Broadcasting", Television Science and Technology Journal ICS61-2, p. 55). , 58/5).

In Figure 1, 1 is an input terminal for inputting the received sequence received as a character code signal, 2 is a receiving buffer for temporarily storing the received sequence, 3 is a data bus for exchanging data, and 4 is a receiving terminal. An error correction circuit for correcting transmission errors in the received sequence read out from the buffer 2; 5 a central processing control unit (hereinafter abbreviated as CPU) for controlling the entire system; 6 an error correction circuit 4; 7 is a storage circuit (hereinafter abbreviated as RAM) for storing the received sequence after error correction;
This is a storage circuit (hereinafter abbreviated as ROM) for storing control instructions for controlling the CPU 5.

Next, the operation in FIG. 1 will be explained.

Character code signals are sequentially transmitted in time series from a broadcasting station, and are received as a reception series on the receiving side. In this case, the received sequence is written into the receiving buffer 2 via the input terminal 1 at the same time as it is being received.
The reception sequence written in reception buffer 2 is
It still contains errors that occurred during transmission. Therefore, the CPU 5 controls the received sequence to be written into the error correction circuit 4 in order to correct the error. After all received sequences are written into the error correction circuit 4,
The CPU 5 issues an error correction command to the error correction circuit 4. This error correction command causes the error correction circuit 4
corrects errors in the received sequence and outputs an error-free received sequence. The CPU 5 controls the received sequence corrected by the error correction circuit 4 to be read via the data bus 3 and written into the RAM 6. The operation in FIG. 1 has been described above, and the error correction circuit 4 will be explained in more detail.

FIG. 2 is a block diagram showing a conventional error correction circuit.

In FIG. 2, 11 is an 8-bit input buffer, 12 is a basic operation clock signal for the error correction circuit 4, 13 is a timing generation circuit that generates control timing for the entire error correction circuit from the clock signal 12, and 14 is an input buffer 11. The data written via the data bus 3 is held at the output.
15 is a parallel/serial/serial/parallel conversion circuit that converts the parallel input of data 14 into parallel and serial, and converts the output of the ER circuit 19 into serial/parallel; 16 records the output of the parallel/serial converter 15 in 272 bits in series; The shift register circuit 17 is a syndrome register, which inputs the output from the parallel-to-serial conversion circuit 15, calculates and stores a series called a syndrome for error detection, and then outputs the calculation result. 18 is an error detection circuit that detects errors from the output of the syndrome register 17; 19 is an E between the error detection circuit 18 and the shift register 16;
ER circuit that takes R (exclusive OR); 20 holds and buffers the output of the serial-to-parallel conversion circuit 15;
This is a bit output buffer.

Next, the operation in FIG. 2 will be explained.

First, the CPU 5 controls the reception buffer 2 to read out the received sequence in parallel, 8 bits at a time, and write it to the input buffer 11 via the data bus 3. Next, the CPU 5 operates the timing generation circuit 13 via the input buffer 11, converts the 8-bit parallel data 14 into serial data by the parallel-to-serial conversion circuit 15, and sequentially serializes the data bit by bit to the shift register 16 and syndrome register 17. Control is performed so that 8 bits are written to.

By the way, the character code signal has a packet format as shown in FIG.

FIG. 3 is a schematic diagram showing a character code signal.

As shown in Figure 3, one packet consists of 272 bits, and the content of the packet consists of 8 bits.
SI/IN, 6-bit PC, 22-byte character code,
It consists of 82 bits of parity for error correction. Here, SI/IN and PC are packet control codes, respectively. Since one packet is 272 bits, in order to write all the data for one packet to the shift register 16, from 272÷8=34,
It is enough if the data is written 34 times.

Next, after the 272-bit data for one packet is written to the shift register 16, the CPU
5 outputs an error correction command to the error correction circuit 4. The error correction command controls the timing generation circuit 13 via the input buffer 11. Then, by determining the output of the syndrome register 17 with an error detection circuit 18, it is detected whether or not there is an error in the first bit of the shift register 16. If there is an error, the output of the error detection circuit 18 becomes "H" level, and the first bit of the shift register circuit 16 is inverted by the EOR circuit 19 and sent to the serial/parallel conversion circuit 15. In addition, if there is no error, the output of the error detection circuit 18 becomes "L" level,
Therefore, the first bit of the shift register circuit 16 is directly transferred to the serial/parallel converter circuit 1 by the EOR circuit 19.
Sent to 5. In this way, when an error correction command is sent from the CPU 5 once, the 8-bit data is error-corrected and sent to the serial/parallel conversion circuit 15, where it is serial-parallel converted. Thereafter, the output from the 8-bit parallel serial/parallel conversion circuit 15 is read out to the data bus 3 via the output buffer 20. The above operations are performed every time an error correction command is sent, and data for one packet is read out until all the data is read out from the shift register 16. Such error correction circuit 4
The error-corrected received sequence is sent to the RAM 6. The above is the explanation of the error correction circuit shown in FIG.

Such conventional error correction circuits have the following drawbacks.

FIGS. 4a and 4b are schematic diagrams each showing a storage format when the character code signal shown in FIG. 3 is stored.

The received sequence has a transmission form as shown in FIG. 3, and since the error correction code must be continuous, it is stored in the reception buffer 2 in the form shown in FIG. 4a. Control code within this
Since the PC is 6 bits, all subsequent data is shifted 2 bits at a time. Therefore, the received sequence corrected by the error correction circuit 4 is also output in the same form as shown in FIG. 4a, and therefore the form stored in the RAM 6 is also in the form shown in FIG. 4a. However, since these pieces of information cannot be treated as character code signals in their current form, they are first converted into the form shown in Figure 4b, that is, SI/IN, PC, character code 1, character code 2, and so on. It was necessary to change the format to one where bytes are given and memorized. This processing is done using CPU5, and all 22 bytes of character code must be processed, so it is quite time consuming.
The disadvantage was that the CPU 5's capacity had to be used for shift processing. Further, when processing with hardware, there is a drawback that the data must be read from the RAM 6 and then written to the RAM 6 anew after the shift processing, which requires a fairly large circuit.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a code word consisting of variable-length data in sequence by giving a predetermined bit to each group and storing it in a RAM without causing an increase in circuit scale. The object of the present invention is to provide an error correction circuit that can perform the following steps.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention variably presets the number of serial bits to be read out from the shift register at each timing in synchronization with the conversion timing of the serial-to-parallel conversion circuit. and means for controlling the number of bits of the digital signal read out from the shift register per timing according to the set number of bits.

[Embodiments of the invention]

FIG. 5 is a block diagram showing one embodiment of the present invention.

In FIG. 5, parts that perform the same functions as those shown in FIG. 2 and described in the prior art are given the same numbers as in FIG. 2. In FIG. 5, 41 is a register circuit for recording data for controlling the timing of the timing generation circuit 13, 42 is the output of the register circuit 41, and 43 is the timing generation circuit 1.
The output of 3 and 44 are clear signals.

Before explaining this example in detail, first,
The operations of the shift register 16 and serial/parallel conversion circuit 15 shown in FIG. 2 or 5 in relation to the present invention will be described. (Although this circuit is a circuit that is used for both parallel-to-serial and serial-to-parallel conversion, the following explanation will be made only for the case of serial-to-parallel conversion.) The output from the timing generation circuit 13 consists of a pulse train, and the shift It is input to the register 16 and the serial/parallel converter circuit 15, respectively (it is also input to the syndrome register 17, but it is not directly related to the following explanation).

In the shift register 16, the timing generation circuit 1
Every time one pulse is input from 3, information (in this case,
Character code signal) is output one bit at a time.

Furthermore, each time one pulse is input from the timing generation circuit 13, the serial/parallel conversion circuit 15 inputs one bit of information coming from the shift register 16, and at the same time shifts the previously input information serially one bit at a time. are doing. However, since the output end of the serial/parallel conversion circuit 15 only has the function of outputting 8 bits of information, information shifted by 8 or more steps is sequentially erased.

The information input to the serial/parallel conversion circuit 15 in this manner is output in parallel at a certain time t _a . That is, at time _ta , all the information (8 bits worth of information) existing internally at that time is output at once. However, by outputting information, the information existing inside does not disappear; it remains in that state unless new information is input and shifted. Further, the timing (time _ta ) at which the information from the serial/parallel conversion circuit 15 is output is periodic and synchronized with the output from the timing generation circuit 13.

Now, the operation of this embodiment will be explained while comparing it with the conventional technology.

FIG. 6a is a waveform diagram showing the output waveform of a conventional timing generation circuit, and FIG. 6b is for explaining the relationship between the output of the timing generation circuit according to the present invention and the character code signal read out from the shift register. FIG.

In FIG. 6b, A indicates the output of the timing generation circuit, and B indicates the character code signal.

Conventionally, as shown in FIG. 6a, the timing generation circuit 13 always repeatedly outputs eight pulses at a period T. Therefore, as described above, in the serial-to-parallel conversion circuit 15, the 8-bit information read out from the shift register 16 during time _t1 is sequentially input and shifted, and
At a certain time _ta between _t2 , these 8 bits of information are output in parallel.

In this embodiment, such a timing generation circuit 1 is used.
I tried changing the output from 3 as shown in A of Figure 6b. That is, as described later, the timing generation circuit 1
By operating the register circuit 3 and the register circuit 41, it is possible to output 6 pulses only when corresponding to the information of "PC", instead of the conventional method of repeatedly outputting 8 pulses with a cycle T.

Hereinafter, using FIG. 6b, the shift register 16
and the operation of the series/parallel circuit 15 will be explained.

The first eight pulses sequentially input the 8-bit information read from the shift register 16, that is, the "SI/IN" information, to the serial/parallel conversion circuit 15. Then, at a certain time _ta during time _t2 , 8-bit information of "SI/IN" is output in parallel. As described above, even after the information is output in parallel, the 8-bit information of "SI/IN" remains inside the serial/parallel conversion circuit 15.

Next, six pulses are output from the timing generation circuit 13. As a result, the shift register 16
From now on, instead of 8-bit information as in the past, "PC"
Only 6 bits of information will be read out. In other words, since only 6-bit "PC" information is input to the serial/parallel conversion circuit 15, only 6 steps are shifted inside the circuit, and therefore, the lower 2 of the previous "SI/IN" information is The bit information will not be deleted and will remain. Therefore, in the serial/parallel conversion circuit 15, at a certain time _ta during time _t2 , the information of the lower two bits of "SI/IN" and
The 6-bit information of "PC" will be output in parallel.

Next, the timing generation circuit 13 outputs eight pulses again. As a result, 8-bit information of "character code 1" is read out from the shift register 16, and is sequentially input to the serial/parallel conversion circuit 15, and the same operation is repeated thereafter.

In the end, from the shift register 16 to the series/parallel circuit 15
The information input to the circuit is 8 bits (``SI/IN''), 6 bits (``PC''), 8 bits (``character code 1''), etc., and is sent from the serial/parallel circuit 15 to the data bus via the output buffer 20. The information output to 3 is 8 bits (``SI/IN''), the lower 2 bits of 8 bits (``SI/IN'' and ``PC''), 8 bits (``Character code 1''),...
becomes.

Therefore, if the CPU 5 controls to read the output of the error correction circuit 4 and write it directly into the RAM 6, a correct character code signal as shown in FIG. 7 will be stored.

FIG. 7 is a schematic diagram showing the storage state of character code signals stored in the RAM according to the present invention.

In FIG. 7, α indicates information on the lower two bits of "SI/IN".

Furthermore, as shown in Figure 7, information α of the lower two bits of "SI/IN", which is unnecessary information, will be written to address 2, but this can be ignored and processed. No problem.

Next, the operation of the timing generation circuit 13 and the register circuit 41 for causing the timing generation circuit 13 to output an output waveform as shown in A of FIG. 6B will be explained using FIGS. 5 and 8.

FIG. 8a is a circuit diagram showing a specific example of the register circuit 41 in FIG. 5. FIG.

This circuit is a D-type flip-flop, and each output Q ₁ , Q ₂ , Q ₃ , ..., Q _N is independently set to "H" by the strobe signal and data from the CPU 5.
It is possible to switch between the low level and the "L" level. That is, this circuit outputs 6 pulses or 8 pulses from the timing generation circuit 13 by setting each output according to instructions from the CPU 5.
This determines whether to output a pulse. For example, if you want to output 6 pulses (Q ₅ , Q ₄ , Q ₃ ,
Q ₂ , Q ₁ ) = (0, 0, 1, 1, 1) (Hereafter, parallel data will be expressed simply as (0, 0, 1, 1, 1).) However, if you want to output 8 pulses, set it as (0, 1, 0, 0, 1).

FIG. 8b is a block diagram showing a specific example of the timing generation circuit 13 in FIG. 5, and FIG. 8c is a waveform diagram showing input and output waveforms of each part in FIG. 8b.

In FIG. 8b, 12 is a clock signal, 42
is an output from the register circuit 41, 44 is a clear signal, and 53 is a counter circuit for counting the number of clocks of the clock signal 12. Furthermore, Q ₁ , Q ₂ ,
Q ₃ , ..., Q _N each represent the LSB output to the MSB output in order. Further, 54 is an inverter circuit, 55 is a decode circuit that outputs one pulse when the output of the counter circuit 53 reaches a predetermined value, for example (0, 0, 0, 0, 1), and 56 is a register circuit 41.
a comparator 5 that compares the output 42 from the counter circuit 52 with the output from the counter circuit 52 and outputs a detection output when they match;
7 is a state holding circuit generally called an SR flip-flop circuit, 58 is a delay circuit for matching the phase of the state holding circuit 57, and 59 is an AND gate circuit for calculating the AND of the output from the delay circuit 58 and the clock signal 12. It is.

Now, the timing generation circuit 13 shown in FIG. 8b
The operation will be explained. Note that although the timing generation circuit 13 outputs 8 pulses and 6 pulses as described above, the following explanation will be made only for the case of 6 pulses. Therefore,
The output 42 of the register circuit 41 is set to (0, 0, 1, 1, 1) by the CPU 5.

A clock signal 12 having a continuous waveform as shown in FIG. 8c is input to the counter circuit 53.
Further, a clear signal 44 is input to the CLR terminal, and when the clear signal 44 reaches the "H" level as shown in FIG. 8c, the counter circuit 53 is cleared. By clearing, when the output Q _N , which is the MSB output of the counter circuit 53, goes to "L" level, the output of the inverter circuit 60 goes to "H" level, and the enable input of the counter circuit 53 allows operation, and the counter circuit 53 starts counting. When counting starts, the waveforms of each output (Q ₁ , Q ₂ , Q ₃ ) of the counter circuit 53 become as shown in FIG. 8c.

The decoding circuit 55 decodes the output of the counter circuit 53, and when the output becomes (0, 0, 0, 0, 1), the decoding circuit 55 decodes the output of the counter circuit 53.
The output G becomes "H" level.

Further, the output of the counter circuit 53 is compared with the output 42 of the register circuit 41 in a comparator 56, and the output of the counter circuit 53 is (0, 0, 1,
1, 1) (as mentioned above, the register circuit 4
The output 42 of 1 is set to (0, 0, 1, 1, 1). ), the output H of the comparator 56 becomes "H" level as shown in FIG. 6c.

Further, since the output G of the decoding circuit 55 is connected to the set terminal S of the state holding circuit 57 and the output H of the comparator 56 is connected to the reset terminal R of the state holding circuit 57, the output I of the state holding circuit 57 is connected to the set terminal S of the state holding circuit 57. 8
The result will be as shown in Figure c. And the state holding circuit 5
In order to match the phase of the gate pulse which is the output I of 7, the phase is changed by a delay circuit 58. Then, by inputting the output J of the delay circuit 58 and the clock signal 12 to the AND circuit 59, the logical product of both is derived, and the output 4 of the timing generation circuit 13 is
3.

In the manner described above, six pulses of output 43 are obtained from the timing generation circuit 13.

In the above explanation, only the case of outputting 6 pulses was explained, but also when outputting 8 pulses, the output 42 of the register circuit 41 is (0,
1, 0, 0, 1), and the same operation can be performed.

Furthermore, it goes without saying that the present invention is not limited to the case where the output from the timing generation circuit 13 is 6 or 8 pulses as in this embodiment, but can be used for any number of pulses. Note that in that case as well, the output can be performed using the same operation.

Finally, with reference to FIG. 5, the operation for causing the timing generation circuit 13 to output the output waveform shown in FIG. 6b, A will be comprehensively explained.

Initially, the CPU 5 sends the output 42 to the register circuit 41 via the input buffer 11 (0, 1, 0, 0,
1). Then, the CPU 5 generates a clear signal 44, operates the timing generation circuit 13 as described above, and generates eight pulses. Next, the CPU 5 sends the output 42 to the register circuit 41 via the input buffer 11 (0, 0, 1, 1,
1). Then, the CPU 5 generates a clear signal 44, and the timing generation circuit 1
3 to generate 6 pulses. after that,
Again, the CPU 5 sends the output 42 to the register circuit 41 via the input buffer 11 (0, 1, 0, 0,
1). Then, the CPU 5 generates a clear signal to operate the timing generation circuit 13. Below, 1 packet (272 bits)
CPU until all data has been corrected.
5 converts the output 42 of the register circuit 41 into (0, 1,
0, 0, 1), and the timing generation circuit 13 is operated.

In the manner described above, the output waveform shown in FIG. 6B is obtained from the timing generation circuit 13.

〔Effect of the invention〕

According to the present invention, a code word consisting of variable length data can be stored in a RAM in sequence for each set of predetermined bits without requiring any new shift processing such as hardware or software. It is possible to avoid an increase in software capacity or a significant increase in hardware scale.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a general error correction system, Fig. 2 is a block diagram showing a conventional error correction circuit, Fig. 3 is a schematic diagram showing a character code signal, and Fig. 4 a and b are FIG. 3 is a schematic diagram showing the storage format when character code signals are stored, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6a is a diagram showing the output waveform of a conventional timing generation circuit. FIG. 7 is an explanatory diagram for explaining the relationship between the output of the timing generation circuit and the character code signal according to the present invention, and FIG. 7 is a schematic diagram showing the storage form of the character code signal according to the present invention. Figure 8a
5 is a circuit diagram showing a specific example of the register circuit in FIG. 5, FIG. 5b is a block diagram showing a specific example of the timing generation circuit in FIG. 5, and FIG. This is a waveform diagram. Code explanation, 4...Error correction circuit, 5...CPU,
6...RAM, 11...Input buffer, 12...
Clock signal, 13...timing generation circuit, 1
5... Parallel-to-serial conversion/serial-to-parallel conversion circuit, 16...
...Shift register, 17...Syndrome register, 18...Error detection circuit, 19...EOR circuit,
20...Output buffer, 41...Register circuit.

Claims (1)

[Scope of Claims] 1. Serial storage means for sequentially inputting and storing digital signal sequences in series, and detecting errors in the digital signal sequences input to the serial storage means and detecting errors based on the detection results. an error detection and correction means for correcting errors in a digital signal sequence sequentially read out in series; and a serial-to-parallel conversion means for converting the error-corrected digital signal sequence into serial-to-parallel units in units of a predetermined number of bits. An error correction circuit comprising: means for variably presetting the number of serial bits to be read out from the serial storage means per timing in synchronization with the timing of the serial/parallel conversion; Accordingly, an error correction circuit comprising means for controlling the number of bits of a digital signal read out from the serial storage means per timing. 2. In the error correction circuit according to claim 1, the control means includes a counting means that starts counting in response to a counting start signal and stops counting when the counted value reaches a predetermined value, and the counting means pulse generating means for generating a first pulse based on the counting output from the counting means; and detecting that the counting output from the counting means has reached a value corresponding to the setting result by the setting means, and outputting a second pulse. a detection means, a gate signal generation means for generating a gate signal by being set by the first pulse and set by the second pulse, and an AND means for generating a logical product of the gate signal and the clock signal. An error correction circuit comprising: