JPH02288511A - Code transmission method - Google Patents

Abstract

PURPOSE:To attain excellent code transmission by suppressing the low frequency component of an error detection correction entirely so as to suppress the low frequency component of the entire code series. CONSTITUTION:A parity calculation circuit 201 generates a parity of an external code and a DSV(Digital Sum Value) arithmetic circuit 204 outputs data being a reference of deciding a CDS(Code word Digital Sum) of the succeeding parity. In order to vary the CDS of the present parity into the CDS designated by the circuit 204, data to be inserted as a dummy data is stored as a table in the data ROM 205. A new dummy data outputted from the ROM 205 is inserted to a dummy data part of a code string Di through an output bus 105. Thus, the code series whose low frequency is sufficiently suppressed is outputted to attain excellent code transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a code transmission method, and more particularly to a code transmission method in which an error detection and correction code is added to a main information code for transmission.

[Prior Art] Generally, in a system that digitizes an information signal such as an image signal and transmits it to a transmission path such as a recording medium, the information data is converted into a transmission code suitable for the transmission path before transmission.

Hereinafter, in this specification, a magnetic recording device such as a digital VTR will be explained as a typical example of such a transmission device.

Normally, in this type of magnetic recording device, it is difficult to record and reproduce extremely low frequencies and DC components due to the transmission characteristics of the magnetic recording system. Therefore, recording is generally performed after converting the digital data to be recorded into a recording code with less low frequency components.

As a transform coding method for suppressing this low frequency component,
Conventionally, conversion encoding systems with redundancy, such as a system (8-9 conversion) for converting 8-bit data into 9-bit data, have been used. However, this method has the disadvantage of increasing redundancy, and with the increase in data volume and high-density recording, it is desirable to record and reproduce data with fewer codes, so this is an encoding method that does not increase redundancy. % Formula % Therefore, as a method that does not increase the redundancy, for example, an n-n mapping coding method that converts n-bit data into the same n-bit data was considered. For example, in the case of image information, the low frequency components of the code sequence to be recorded are suppressed by utilizing the statistical properties of image information, such as the property that there is a high correlation between adjacent codes.

As an example of this method, an input signal is differentially encoded, and by using the fact that the differential code has a Laplace distribution that concentrates around zero of the positive and negative quantization levels, CD5 is applied to the differential code that appears frequently. (Code word Dig
ital Sum ), thereby assigning a small code of D
The SV (Digital Sum Value) is reduced. In this way, the low frequency components of the recorded code sequence are suppressed. For example, 4-4 mapping, which converts a 4-bit differential code to a 4-bit code, Examples include encoding methods.

[Problems to be Solved by the Invention] As described above, mapping coding cannot suppress low frequency components of coded code sequences for information codes such as image information that have a correlation between adjacent codes. However, it is not possible to suppress low frequency components of codes that have no correlation between codes.

For example, when inserting an error detection and correction code that detects and corrects code errors or a code sequence that records uncorrelated additional information, the effect of suppressing low frequency components is sufficient for the code sequence. I can't get it. Moreover, as a result, the code error rate during decoding increases.

This point will be further explained below with reference to FIGS. 2 and 3. FIG. 2 is a schematic diagram showing an example of the structure of a general data frame in a code sequence to be recorded. In the part shown as information data in the figure, the above-mentioned mapping-encoded information code sequence is arranged and shown as parity. An error detection and correction code such as a parity code such as a Hamming code or a Reed-Solomon code is arranged in the portion. Furthermore, a synchronization pattern is placed in the portion shown as synchronization data.

Also, Figure 3 shows how the inner code (row check code) is configured in the data frame shown in Figure 2 above, a plurality of such data frames are arranged vertically, and the outer code (column check code) is arranged vertically. FIG. 3 is a diagram showing a data matrix configured so that a product code is configured as a whole. In particular, in this configuration, the main information code and parity are arranged two-dimensionally, so the code configuration is suitable for a device that records a code sequence obtained by encoding two-dimensional information such as image data. It can be said that there is. This data matrix will be recorded sequentially for each data frame.

However, when a data matrix like the one shown in Figure 3 is configured, there is no correlation between the inner and outer codes, so the effect of suppressing low frequency components by mapping coding cannot be expected, and the same code is not repeated. It can be said that we are in a situation where this is likely to occur. In particular, in a data frame consisting only of the parity of the code and the inner code, the parity continues for a long time, which has the disadvantage that the low frequency suppression effect of the code sequence in the vicinity is significantly reduced. .

As one method to solve such problems, the applicant
We proposed a technique for distributing additional information codes such as error detection and correction codes within a recorded code sequence (Japanese Unexamined Patent Publication No. 62-30
436), this method disperses the codes that cause low frequency components in the code sequence, making it possible to significantly reduce the code error rate during decoding. By the way, in this method, the low frequency component of the error detection and correction code itself is not changed.

Against this background, the present invention provides a novel encoding method that can suppress the low frequency components of the entire encoded sequence by suppressing the low frequency components of the error detection and correction code itself as a whole. The purpose is to

[Means for Solving the Problems] In order to solve the problem, according to the present invention, in a method of transmitting an error detection and correction code added to each data group including a main information code and a control code, past error detection A method is presented for detecting a low frequency component of a correction code and determining a control code pattern to add an error detection and correction code that cancels out the detected low frequency component.

Further, in a preferred embodiment of the present invention, when the error detection and correction code of each data group consists of a plurality of parities, the pattern of the control code is determined so as to sequentially cancel out the low frequency components of the plurality of parities. .

[For use] By configuring as described above, even if there is a continuous portion of error detection and correction codes in the code sequence to be transmitted, the low frequency components of the code sequence are canceled out, resulting in a low overall It has become possible to sufficiently suppress frequency components and perform good code transmission.

Furthermore, as shown in the preferred embodiment of the present invention, by having a configuration in which the low frequency components of multiple parities are canceled out in sequence, the low frequency components of the entire code sequence can be suppressed without increasing the circuit scale. be able to. Furthermore, this control operation can be performed at high speed.

[Example] Examples of the present invention will be described below.

FIG. 1 is a diagram showing the main part configuration of a recording apparatus to which the code transmission method of the present invention is applied, and shows a generating section of a code sequence to be recorded, particularly a generating section of an outer code. Furthermore, FIG. 4 is a diagram showing a data matrix of code sequences recorded by the apparatus of this embodiment.

In FIG. 4, ■ is the main information code, and a=1 to b=1 to i. Also, Ib.

is the parity of the inner code, and a=O~2°b=o~m. Also, OP is the parity of the outer code, and a=O~
2. b=1 to i. Furthermore, Dah is dummy data as a control code, and a=1. b=l~i.

As shown in FIG. 4, dummy data DI+-D++ is placed on the first line of the data matrix, and the dummy data allows the values of parity OPo+ to OP□ of the outer code to be The inner code and the outer code each have three words of parity I added thereto, thereby forming a product code.

The circuit configuration in FIG. 1 mainly consists of a circuit 106 that processes the main information code and a circuit 106 that processes the outer code parity oPob+o
A circuit that generates p, I,, o p, 213゜31
It consists of 3.413. Each circuit 213°313.4
13 has the same circuit configuration, and the parity calculation circuit 201
, 301, 401, data ROM 205, 305, 40
5 and the internal coefficients of the coefficient multiplier 209, 309, and 409 are different.

It is also assumed that low frequency components of the main information code in the input code Di have been suppressed by a mapping coding circuit (not shown). Further, it is assumed that all dummy data in the code Di are preset with O's. This code D
i is the delay circuit 101 and the parity calculation circuits 201 and 30
1° 401 at the same time.

The parity calculation circuits 201, 301, and 401 are configured to perform calculations in the vertical direction of the data matrix, and generate an outer code using the main information code of the line and the dummy data of the line in FIG. The configuration is such that the outer code parity for three lines is continuously output when all matrix calculations are completed.For subsequent processing, a circuit 213 that generates the outer code 0Po- of the O-th line is used. I will only explain about.

The parity generated by the parity calculation circuit 201 is OP
o+, OPo*” ” ' Delay circuit 2 in the order of 0Po-
03 and D SV (Digital Sum Val
ue) is input to the arithmetic circuit 204. The DSV calculation circuit 204 does not operate while the parity calculation circuit 201 is calculating parity, and starts calculation at the same time as each outer code OPO is input. DSv calculation circuit 204
Now, determine the number of 0.1 for each symbol (word),
The integrated value is calculated and stored. Then, the circuit 204 outputs the next parity CD S (Code word Digi
tal Sum ) is output. This data is the CDS value of the next parity, -8. -6. -4. −
It outputs 4-bit data corresponding to nine types of 2.0°, 2.4, and 6.8, and serves as an address control signal for the data ROM 205.

The data ROM 205 has four
The bits are supplied as the upper address, and the 8-bit parity generated with dummy data as O is supplied as the lower address. In the data ROM 205, data values to be inserted as dummy data in order to change the current parity CDS to the CDS designated by the DSV calculation circuit 204 are stored as a table. However, since the data stored in the data ROM 205 requires suppression of the low frequency components of the dummy data itself, C
Large values of DS are excluded.

The dummy data output from the data ROM 205 is output to the internal bus 104 used in each parity generation circuit 213, 313, 413, and is also output to the delay circuit 205.
The timing is adjusted in step 2. Then, this new dummy data is stored in the buffer 211 in the dummy data portion of the code string Di whose timing is similarly adjusted by the delay circuit 101.
via the output bus 105.

The dummy data output to the internal bus 104 is sent to the multiplier 20
7, it is multiplied by the coefficient from the coefficient unit 209. By adding this multiplication result to the parity generated by setting the dummy data to 0 in an adder 208, a parity having a desired CDS is obtained. The parity value having the desired CDS is fed back to the DSV calculation circuit 204, and the DSV value held by this parity is corrected.

By the above-described series of operations, OPo+ and OP+i are obtained in the parity of the outer code shown in FIG.

Set each parity to a desired CDS value in the order of OPgs, 0P04.0Pts” ” ” .This allows the DS to be set in units of 3 words in the code transmission direction (line direction).
As a result, the outer code parity generator outputs a code sequence in which low frequency components are sufficiently suppressed in all three data frames in which parity words are consecutive. Thereafter, a circuit (not shown) further adds an inner code parity IP and supplies it to the subsequent recording system circuit.

By configuring as described above, all three data frames consisting only of parity can be recorded as code sequences with low frequency components suppressed, and the occurrence of errors in the recording/reproduction system can be significantly reduced. Further, since each parity can be determined by only one calculation, it can be realized with a relatively simple circuit configuration and high-speed processing is also possible.

Note that the parity of the inner code added in the latter stage will be recorded in three consecutive words, but the above-mentioned Japanese Patent Laid-Open No. 62-3
With the technique disclosed in Japanese Patent No. 0436, the inner codes can be easily distributed and arranged within each line, causing almost no problem.

Next, another embodiment of the present invention will be described with reference to FIG.

This FIG. 5 also shows only the configuration of the outer code generation section, and it is assumed that the code sequence shown in the data matrix of FIG. 4 is recorded as in the above-described embodiment.

In the figure, 1212 is a circuit that generates the parity OP of the outer code, 1312 is a circuit that generates the parity OP of the outer code, and 1412 is a circuit that generates the parity OP of the outer code. Since they are the same, only the internal configuration of the circuit 1212 will be disclosed in FIG. These parity generation circuits 1212
．． 1312 and 1412 are different from the parity generation circuits 213, 313, and 413 of the embodiment shown in FIG.

Similar to the embodiment of FIG. 1, the circuit 1212.1312°1
At 412, parity calculation and DSV calculation are performed, respectively. Taking circuit 1212 as an example, parity calculation is performed in parity calculation circuit 1201 and DSV calculation is performed in DSV calculation circuit 1203. These circuits 1212°131
Data from CDS 2 and 1412 is supplied to a common dummy data calculation circuit 1008 via a parity bus 1009 for parity, and a control bus 1010 for data related to a desired CDS value.

First, the parity and CDS calculated in the circuit 1212
Specified data is sent to data R via bus 1009.1010.
The address is input to OM 1001 and data ROM 1002 as an upper address. Data ROM 1001.10
In 02, data to be inserted into the dummy line is provided as a table in order to generate parity having the CDS necessary to converge the DSV in the continuous parity part of OP oh to 0.

The data ROMs 1001 and 1002 each output dummy data for generating parity having the same CDS value but different values. The value output here is a value multiplied by the coefficient of the generator matrix so that a common table can be used for each parity.

The two types of dummy data output from the data ROMs 1001 and 1002 are input to coefficient units 1003 and 1004, respectively, and are divided by the coefficients of the generation matrix of the parity OPo2 selected by the control signal described later. The circuit 100 determines the form of data inserted as data.
5. At this point, buses 1009 and 101
Data from the circuit 1312 for parity 0PIIl is output to 0, and is simultaneously supplied to the discrimination circuit 1005.

In the discrimination circuit 1005, the input two types of dummy data are multiplied by the coefficients of the generation matrix of parity op and b, and further added to the parity from the parity op and b body circuit 1312, and the inserted parity 0PIb is Two types are generated. Furthermore, the discrimination circuit 1005 calculates the CDS of these two types of parity, and calculates the input parity o.
Based on the DSV values of p and b, this parity op,
, the switching circuit 1006 is controlled to select dummy data that can generate parity with a high effect of suppressing low frequency components.

Thereafter, as in the previous embodiment, the coefficient of the generation matrix of the parity OP ob is multiplied by the coefficient unit 1007, and the first
It will be output to the internal bus 1011 as in the embodiment shown. The operation after this is completely the same as the embodiment shown in FIG. It will be output.

Although the detailed structure of the discrimination circuit 1005 is not particularly disclosed, it is obvious that it can be easily constructed from the structure of the parity generation circuit shown in FIGS. 1 and 4.

Further, the above control signal is parity OP o. , O
PI+,,OP,,Medium,Data indicating which parity column's DSV is currently being operated to reduce the DSV, and is coded D.
It can be easily obtained in synchronization with the input timing of i. That is, the above-mentioned processing is performed on circuit 1 for parity 0Pol.
This is about the process of performing DSV control of the parity string based on the data output by the parity 212, but at the next timing, processing is performed based on the data from the circuit 1312 for parity 0PIIl, and the judgment circuit 1005 The DSV of the column 0P2Il should be made as small as possible (switching the switching circuit 1006).Similarly, processing is performed based on the data from the circuit 1412 for parity 0P2b, and in the judgment circuit 1005, the DSV of the parity column OPo
Switching circuit 100 to reduce SV as much as possible
The process of switching 6 will be repeated.

According to the configuration shown in FIG. 5 as described above, the DSV of each parity can be controlled more frequently than the configuration shown in FIG. This can be done even more effectively. According to this embodiment, two types of dummy data are generated and selected from these, but by increasing the types of dummy data, it is possible to further increase the effect of suppressing low frequency components. It is. It is also clear that low frequency components can be suppressed more effectively by obtaining the DSV referred to for this selection from more parity columns.

In the present invention, the number of parity words for each check code is 3 words, but the present invention can be applied regardless of this number.

[Effects of the Invention] Against this background, the present invention provides a novel method that can suppress the low frequency components of the entire coded sequence by suppressing the low frequency components of the error detection and correction code itself as a whole. The purpose is to provide an encoding method.

As explained above, according to the code transmission method of the present invention, by suppressing the low frequency components of the error detection and correction code itself as a whole, it is possible to suppress the low frequency components of the entire encoded sequence. It became possible to perform good code transmission.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main part configuration of a recording device as an embodiment of the code transmission method of the present invention, FIG. 2 is a schematic diagram showing the configuration of a data frame for boat fishing, and FIG. Figure 4 is a diagram showing the configuration of a data matrix when a product code is formed using the data frame in Figure 1. Figure 5 is a diagram showing the configuration of a data matrix handled by the configuration shown in Figure 1. Figure 5 is a code according to the present invention. FIG. 3 is a diagram illustrating a main part configuration of a recording device as another example of a transmission method. In the figure, 101 are mapping encoding circuits, 213 and 31, respectively.
3.413.1212.1312゜1412 are parity generation circuits, 201.301, 401.1201 are parity calculation circuits, 204.304, 404.1203 are DSV calculation circuits, 205, 305. 405. 1001. 1002
are each data ROM. 209.309,409,1004,1005゜100
7 and 1208 are coefficient multipliers, 1005 is a discrimination circuit, and 1006 is a switching circuit.

Claims (2)

[Claims] (1) A method of transmitting an error detection and correction code added to each data group including a main information code and a control code,
A code transmission method comprising: detecting low frequency components of past error detection and correction codes; and determining a control code pattern to add an error detection and correction code that cancels out the detected low frequency components. (2) The error detection and correction code of each data group is composed of a plurality of parities, and the pattern of the control code is determined to sequentially cancel out the low frequency components of the plurality of parities. Code transmission method described in section 1).