JP2714128B2 - Code transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code transmission method, and more particularly to a code transmission method in which an error detection / correction check code is added to a main information code for transmission.

2. Description of the Related Art Generally, in a system in which an information signal such as an image signal is digitized and transmitted to a transmission path such as a recording medium, information data is converted into a transmission code suitable for the transmission path before transmission.

Hereinafter, in this specification, a magnetic recording device such as a digital VTR will be described as a typical example of such a transmission device.

Normally, in this type of magnetic recording device, it is difficult to record and reproduce very low frequency and DC components due to the transmission characteristics of the magnetic recording system. Therefore, after converting the digital data to be recorded into a recording code with few low frequency components,
An operation of recording is generally performed.

As a conversion coding method for suppressing the low-frequency component, a conversion coding method having a redundancy such as a method of converting 8-bit data into 9-bit data (8-9 conversion) is conventionally used. Have been. However, this method has a disadvantage that the redundancy is increased. With the increase in the data amount and the high-density recording, a coding method that does not increase the redundancy even from the background where recording and reproduction with a smaller number of codes is desired. Is desired.

Therefore, as a method that does not increase the redundancy, for example, nn which converts n-bit data into the same n-bit data is used.
A mapping coding scheme was considered. The nn mapping coding suppresses low-frequency components of a code sequence to be recorded by using a statistical property of an input code sequence, for example, a property that a correlation between adjacent codes is high in image information. Things.

As an example of this method, an input signal is differentially coded, and the difference code has a Laplace distribution concentrated around zero of the positive / negative quantization level. A code with a small CDS (Code word Digital Sum) is assigned, thereby reducing the DSV (Digital Sum Value) of the converted and coded code sequence. The low-frequency component of the code sequence to be recorded in this way is suppressed, and for example, a 4-4 mapping coding system that converts a 4-bit differential code into a 4-bit code can be used.

[Problems to be Solved by the Invention] By the way, in the mapping coding, as described above, for information codes such as image information having correlation between adjacent codes, it is possible to suppress a low frequency component of a coded code sequence. However, low-frequency components of codes having no correlation between codes cannot be suppressed.

For example, when an error detection / correction code for detecting or correcting a code error or a code sequence for recording additional information having no correlation is additionally inserted, the effect of suppressing low-frequency components of the code sequence is sufficient. I can't get it. As a result, the bit error rate at the time of decoding increases.

Hereinafter, this point will be further described with reference to FIG. FIG. 4 is a schematic diagram showing a configuration example of a general data frame as a format of a code sequence to be recorded;
In the figure, the information data sequence subjected to the mapping coding described above is arranged in the part shown as information data, and the inspection point such as a Hamming code or Reed-Solomon code is arranged in the part shown as a check point. . In addition, Sync.I
In a portion indicated as D or the like, it is arranged as an additional information code such as a synchronization code or an ID code.

However, when a data frame as shown in FIG. 4 is configured, since there is no correlation between codes in a portion where the check points of the error detection and correction code are continuous, mapping coding cannot be performed, and It can be said that continuity is likely to occur. Therefore, a low-frequency component is easily generated in this portion, and the low-frequency component is not sufficiently suppressed as a whole of the code sequence to be recorded.

As one method for solving such a problem, the present applicant has proposed a technique of distributing additional information codes such as error detection and correction codes in a code sequence to be recorded (Japanese Patent Laid-Open No. Sho 62-30).
No. 436). In this method, the codes causing low frequency components are dispersed in the code sequence, so that the code error rate at the time of decoding can be significantly reduced. By the way, in this method, the low frequency component itself of the error detection and correction code itself is not changed.

The present invention provides a novel encoding method capable of suppressing the entire low-frequency component of an encoded sequence by suppressing the low-frequency component of the error detection and correction code itself in such a background. Aim.

[Means for Solving the Problems] For such a purpose, according to the present invention, there is provided a method of adding an error detection / correction check code to a main information code and transmitting the same, wherein the method comprises the steps of: Including a control code other than the main information in the code group used for the calculation of,
A method of detecting a calculated bit pattern of the error detection / correction check code and changing the value of the control code according to the detection result is presented.

In a preferred embodiment of the present invention, the main information code is a code coded so as to suppress low frequency components.

Further, as another preferred embodiment of the present invention, a fractional bit in a sub information code included in each code group is used as a control code.

[Operation] With the configuration described above, even when a continuous portion of the error detection and correction code exists in the code sequence to be transmitted, the low frequency component of the code sequence can be sufficiently suppressed, and Code transmission can be performed.

Further, as shown in the preferred embodiment of the present invention, the above-mentioned effects can be realized without increasing redundancy at all by using fractional bits in the sub-information codes included in each code group as control codes.

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a diagram showing a main configuration of a recording apparatus to which the code transmission method of the present invention is applied, and shows a generation unit of a code sequence to be recorded.

In this embodiment, it is assumed that a Reed-Solomon code in which an irreducible polynomial on a Galois field (2 ⁸ ) is used as a generator polynomial as an error detection and correction code, and an 8-bit code is treated as one symbol. .

The format of the code sequence to be recorded is
Assume the data frame configuration shown in the figure. That is, as is clear from FIG. 3, one data frame configuration is composed of n bits (= N symbols) including l unused bits (1 is less than 8) in M symbols of the main information symbol to be transmitted originally. , And parity bits for K symbols as an error detection and correction code.

The sub-information code includes a synchronization code (Sync) and an ID code. Here, l is less than 8 because the unused l
When bits are handled as codes in symbol units, the number of bits of the original sub-information code is not a multiple of 8 but is a fractional bit, and by using these unused bits as dummy codes, Low frequency components of the entire code sequence can be suppressed without increasing the redundancy at all. That is, the ID code or the like included in the sub-information code does not have a predetermined number of bits that is an integral multiple of 8 bits, and often uses unused bits when handling codes in symbol units. In the present embodiment, attention is paid to this fractional bit which has not been used at all, and the low frequency component of the error detection and correction code is suppressed.

In FIG. 1, a main information code sequence Di to be transmitted is input to a mapping coding circuit 101, and the mapping coding circuit 101
In 1, the above-described mapping encoding using the statistical properties of the input main information code sequence Di is performed,
The information is converted into a main information code sequence in which low frequency components are suppressed without increasing the redundancy at all, and is output.

The converted main information code is input to the memory 102,
The data is sequentially read according to the format shown in FIG.

On the other hand, a synchronization code or an ID code, which is a sub information code, is added to a predetermined position in a data frame by a synchronization (Sync) ID adding circuit. Note that the parity bit as the error detection and correction code is generated by a parity calculation circuit or the like to be described later, and is inserted at a predetermined position in a data frame in a subsequent stage. Unused bits in the above-described sub-information code are assumed to have a code of, for example, all zeros inserted as an initial setting value before the parity calculation.

Now, in a state where a predetermined initial set value is substituted for unused bits, the sub information code and the main information code are parity operation circuits 111, 121, 131 for error detection and correction codes, and IDs for latching symbols including unused bits. Latch 105
And supplied to the memory 103.

Here, an operation for parity generation will be described. Now, a code for generating a parity bit, that is, a main information code M symbol and a sub information code N symbol is represented by a vector of information = (i ₁ , i ₂ , i ₃ ... I _{M + N} ). , Error detection I do. Here, x ₁ ~x _K corresponds to the parity bit. These two Using the generator matrix G Can be expressed as Here, G is a matrix as follows.

That is, parity bits are generated by an operation called matrix multiplication.

FIG. 2 shows a parity calculation circuit shown in FIG.
FIG. 3 is a diagram illustrating a configuration example of 111, 121, and 131. Generator matrix ROM20
1 stores the above-mentioned counts P _{1,1 to} P _{k, M + N} of the generator matrix at addresses corresponding to the respective elements of the information, and the Galois pair multiplier 202 stores the respective elements of the information and the ROM 202 corresponding thereto. , Ie, Galois field multiplication of each count of the generator matrix. Further, the signals are integrated by a circuit including the Galois field adder 203 and an I symbol delay circuit, and the above-described matrix operation is performed. Here, the addition of the Galois field is performed by EXOR (exclusive OR) of each bit.

Parity calculation circuit realized by the above configuration
Each parity generated by 111, 121, 131 is
2, 122, 132. On the other hand, the memory 103 holds the sub information code and the main information code until the parity generation ends. In addition, the ID latch 105 holds only the symbols including the unused bits in order to generate the symbols including the changed unused bits when changing the above-described unused bits.

Next, each parity calculated as described above is input to the bit pattern detection circuit 151, and the bit pattern is detected. Then, based on the detected bit pattern, the determination circuit 152 determines whether or not the calculated parity is one in which low-frequency components have been sufficiently suppressed. Specifically, the DSV of the parity part is calculated,
It may be determined whether or not the absolute value is smaller than a preset threshold.

If the absolute value is smaller than the threshold value, it is determined that the generated parity code portion is one in which the low-frequency component has been sufficiently suppressed, and the generated unused bit is not changed and the generated parity code portion is not changed. Latching parity
At 114, 124, and 134, the information is latched, added to the information as it is, and output.

On the other hand, if the DSV is larger than the threshold value, it is determined that the generated parity code portion has a low-frequency component, and the insertion data generation circuit 153 sets a new l bit to change the unused bit. Generate a pattern.
The new bit pattern is used as the unused bit to calculate the parity again, and the determination circuit 152 determines again whether the new parity bit pattern has a low frequency component. The above operation is repeated until a parity of the pattern in which the low frequency component is suppressed is generated.

The insertion data generation circuit 153 is capable of generating all bit patterns of l bits. The method of generating the l-bit pattern by the insertion data generation circuit 153 at this time may be such that all the patterns are generated sequentially from a simple counter, and are calculated in advance according to the determination result of the determination circuit 152. A configuration for generating a pattern is also possible. In this embodiment, since the initial value set value of the unused bit is set to an all-zero pattern, the above change can be realized by addition of Galois fields.

On the other hand, the correction of the parity can be realized as follows. Now, assuming that the symbol including the unused bits is the j-th symbol on the information, i.e., _ij ,
During the above-described parity calculation, only the operation of the term related to i _j needs to be redone. That is, P
_{1, j,} to P _{2, j} ····· P _K, conducted multiplication only unused bits of _j and the information i _j, calculation results when the unused bits Calculated previously been an all zero What is necessary is just to add each. Information
In unused bits only multiplication of i _j is other bits of insertion values to information i _j may be performed multiplication as 0.

The parity ROM 154 in FIG. 1 stores a result obtained when a change value of an unused bit is input and the above-described matrix operation is performed in accordance with the input value. Accordingly, the output of the parity ROM 154 is supplied to the adders 113, 123, and 133, and is added to the parity when the unused bits already calculated are all zero, thereby realizing the parity correction.
The parity recalculated by such an operation is input to the bit pattern detection circuit 151 again, and the optimum parity is selected by repeating the above-described determination to correction operations.

At this time, in the repetitive calculation, only when a parity pattern with less low frequency components than before is obtained,
The parity is latched by the latches 114, 124, and 134. At the same time, the symbol including the unused bit changed by the inserted bit pattern at that time is also latched by the latch 107. With this configuration, the parity of the optimal pattern is finally latched in the latches 114, 124, and 134.

Here, when the unused bits are, for example, 4 bits, 00
Even if all bit patterns other than 00 are inserted and calculations are performed accordingly, only 15 calculations are required, and the pattern with the lowest low-frequency component suppressed is selected from the parity obtained at this time. Can be performed in a short time.

In this case, instead of selecting the pattern in which the low-frequency component is suppressed the most, the above-described repetitive arithmetic processing is terminated when a parity having a low-frequency component equal to or less than a predetermined threshold is obtained, and the parity at that time is changed. A configuration in which latch is performed can also be adopted. In this case, the operation time can be further reduced.

As a method of determining the suppression state of the low-frequency component in the determination circuit 152, the size of the CDS value of each parity,
Or check the number of consecutive same level (0 or 1),
Alternatively, it is conceivable to make a condition judgment or the like combining them.

The suppressed parity of the low-frequency component determined as described above and the symbol in which the unused bit is changed to the insertion value are latched by latches 107, 114, 124, and 134, respectively, at the timing according to the data format shown in FIG. The information is combined with other information i _a (a = 1,..., M + N, where j is gradually reduced) and output. Note that the memory 103 performs an operation of delaying the stored data by the time required for the parity calculation.

By the above operation, it is possible to insert an appropriate bit pattern into the above-mentioned unused bits and suppress the low-frequency component of the parity part.

In this embodiment, an example in which the number of parities is 3 is shown, but the present invention is not limited to this. or,
It is also possible to adopt a configuration in which a dummy code is separately prepared. Further, it goes without saying that the present invention can be applied to error detection and correction codes other than Reed-Solomon codes.

[Effects of the Invention] As described above, according to the code transmission method of the present invention,
Even when a continuous portion of the error detection and correction code exists in the code sequence to be transmitted, the low frequency component of the code sequence can be sufficiently suppressed, and good code transmission can be performed. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a recording apparatus to which the code transmission method of the present invention is applied, FIG. 2 is a diagram showing an example of a configuration of a parity calculation circuit shown in FIG. 1, FIG. FIG. 4 is a diagram showing a data format of a code sequence transmitted by the configuration of FIG. 1, and FIG. 4 is a schematic diagram showing a configuration example of a general data format of the code sequence. In the figure, 101 is a mapping coding circuit, 102 and 103 are memories, 10
4, 105, 107, 112, 114, 122, 124, 132, 134 are latches, respectively.
6, 113, 123, and 133 are adders, 111, 121, and 131 are parity calculation circuits, 151 is a bit pattern detection circuit, 152 is a determination circuit, 153 is an insertion data generation circuit, and 154 is a parity ROM.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 7/24 H04N 7/13 A

Claims (3)

(57) [Claims] 1. A method of adding an error detection / correction check code to a main information code and transmitting the same, wherein a control code other than the main information code is included in a code group used for an operation when the error detection / correction check code is generated. And detecting the calculated bit pattern of the error detection / correction check code, and changing the value of the control code according to the detection result. 2. The code transmission method according to claim 1, wherein said main information code is a code coded so as to suppress low-frequency components. 3. The code group according to claim 1, wherein the code group includes sub-information related to the main information in addition to the main information, and the control code is a fractional bit in the sub-information code. The code transmission method according to the item.