JPH1141211A - Digital modulatin circuit and its method, and digital demodulation circuit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfactorily suppress the DC and low frequency components of the recording and transmitting signals by multiplexing the prescribed data as the dummy data to generate a multiplex block, using the multiplex block as an information part to perform the Reed-Solomon coding for generation of the 1st and 2nd Reed-solomon coaes, and setting the 2nd Reed-Solomon code of the minimum DC component for the output use. SOLUTION: A dummy data multiplexer 11 multiplexes a prescribed original of a GF(Galois field) as the dummy data at the head of a block of a prescribed number of bits which are successively segmented from the data series inputted via an input terminal 10 of a modulation circuit. The block that is multiplexed by the dummy data is called a multiplex block. An RS encoder 13 performs the Reed-Solomon coding with the multiplex block used as an information part and generates a 1st Reed-Solomon code. A j-type EX-OR device 20 adds plural types of scrambling Reed-Solomon codes to the 1st Reed-Solomon code and generates a 2nd Reed-solomon code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation circuit and a digital modulation method for modulating a data sequence (data stream) into a signal waveform sequence (bit stream) such as a recording signal or a transmission signal. The present invention also relates to a digital demodulation circuit and a digital demodulation method for demodulating a signal waveform sequence into a data sequence.

[0002]

2. Description of the Related Art A binary data sequence is modulated into a signal waveform train such as a recording signal or a transmission signal suitable for the characteristics of a recording medium, a recording head, a transmission medium or the like, and recorded on the recording medium or transmitted to a transmission system. Sent out. For example, it is RLL-coded and further NRZI-modulated and recorded on a recording medium. Thereby, the recording density can be increased. In some cases, a binary data sequence is directly subjected to NRZ modulation or NRZI modulation and recorded on a recording medium.

In the RLL coding, m-bit data words (data elements) are sequentially cut out from an input data sequence, and each data word is converted into an n-bit code word.
In this conversion, restrictions are imposed on increasing the minimum value Tmin of the polarity inversion interval of the signal waveform sequence after NRZI modulation and decreasing the maximum value Tmax. That is, in the code string (bit stream) after RLL encoding, the number of bits “0” existing between bit “1” and bit “1” is set to d or more and k or less. Restrictions are imposed. The RLL code converted so as to satisfy this constraint is referred to as a (d, k; m, n) RLL code.

In NRZI modulation, modulation is performed in which the RLL code is inverted at bit “1” and not inverted at bit “0”. Accordingly, the bit inversion interval in the signal waveform sequence of the recording signal and the transmission signal after the NRZI modulation is set to the NRZI
It becomes larger than the bit inversion interval in the RLL code before modulation. For this reason, compared with the case where the RLL code before NRZI modulation is recorded on a recording medium or transmitted to a transmission system, the signal waveform sequence after NRZI modulation is recorded on a recording medium or transmitted to the transmission system. In the case of reproducing the transmitted signal, the waveform distortion in the reproduced signal is reduced.
As a result, errors during reproduction are reduced. In addition, if the same reproduction error is allowed, the recording of the recording signal after the NRZI modulation or the signal waveform sequence of the transmission signal on the recording medium or sending to the transmission system is better before the NRZI modulation. The recording density can be increased as compared with the case where the RLL code is recorded on a recording medium or transmitted to a transmission system.

The following is desired for a signal waveform sequence of a recording signal or a transmission signal. (1) The minimum value Tmin. Tmin is obtained by the product of "d + 1" and Tw. Tw is the detection window width. When the recording density is increased, the inversion interval of the recording signal is reduced, and the reproduced signal is easily distorted by waveform interference. As a result, a read error is likely to occur. In order to reduce waveform distortion when reading a recording medium having a high recording density and reduce reading errors, it is desirable that Tmin be large.

(2) The maximum value Tmax. Tmax is determined by the product of "k + 1" and Tw. As long as the polarity is not inverted, a reproduction pulse cannot be obtained. Therefore, the clock cannot be directly generated from the reproduction pulse, and the clock is likely to be incorrect. Further, as the polarity inversion interval becomes longer, the fluctuation of the DC component becomes larger. Therefore, it is desirable that Tmax be small.

(3) DC component or low frequency component. A recording device for recording a signal waveform sequence on a recording medium and a reproducing device for reproducing a signal recorded on the recording medium have an AC coupling element. A device for converting a signal waveform sequence into an analog signal and sending it to a transmission system and a device for reproducing an analog signal obtained from the transmission system also have an AC coupling element. For this reason, if the signal waveform sequence has a DC component, the waveform is distorted in the AC coupling element, which is not preferable. Further, the DC component lost at the time of recording or the like cannot be restored at the time of reproduction.
Therefore, it is desirable that the DC component and the low frequency component are small. To evaluate DC components and low frequency components in the recording signal, use D
SV (Digital Sum Value) is used. DSV sets the value of bit “1” to “+1” and the value of bit “0” to “−”.
As “1”, an accumulated value from the start of the waveform sequence of the recording signal is obtained. If the absolute value of the DSV is small, the DC component or the low frequency component is small. For evaluation of DC components and low frequency components in each codeword, CDS (Codewo
rd Digital Sum) is used. CDS is the DSV within each codeword. If the CDS is small, the DC component or low frequency component of the code word is small.

(4) Detection window width Tw. The detection window width Tw is given by (m / n) T. here,
T is the bit interval of the data stream before modulation. The detection window width Tw indicates the time that can be used for detecting the reproduced bit, that is, the resolution. The figure also shows the tolerance for phase fluctuation of a reproduced signal due to waveform interference, noise, and the like. Tw is
Larger is desirable.

(5) The constraint length Lc. In order to improve Tmin, Tmax, and DSV, encoding may be performed with reference to preceding and succeeding codewords. The length of the codeword before and after being referred to at that time is called a constraint length Lc. The larger the value of Lc, the greater the error propagation and the more complicated the circuit configuration. Therefore, it is desirable that Lc is small.

Japanese Patent Application Laid-Open No. 52-128024 discloses N
There is disclosed a technique for increasing Tmin and decreasing Tmax of a recording signal after RZI modulation. JP-A-52-128
In Japanese Patent Application Publication No. 024, RLL encoding is performed in which a 2-bit data word (data element) is sequentially cut out from an input data sequence and converted into 3-bit code words.
(1, 7; 2, 3) RLL codes are generated. The code string of the generated RLL code is NRZI modulated. If d = 1 cannot be satisfied,
(1,7; 4,6) RLL code is generated.

Japanese Patent Publication No. 1-27510 discloses NRZ
A technique for performing code conversion (RLL coding) so as to reduce the DC component of a recording signal after I modulation and performing code conversion so that Tmin of a recording signal after NRZI modulation does not become small is disclosed. In Japanese Patent Publication No. 1-27510, blocks of n bits are sequentially cut out from a code string after code conversion, and a plurality of redundant bits are inserted between adjacent blocks. The code string after the insertion of the redundant bits is supplied to the NRZI modulation circuit. here,
The redundant bit is selected based on the necessity of sign inversion between blocks into which the redundant bit is to be inserted and the state of the end of the immediately preceding block. That is, the selection is made so that the DC component of the recording signal after the NRZI modulation is reduced and Tmin is not reduced.

Japanese Patent Publication No. 5-34747 discloses that a conversion rule for converting a data string into an RLL code is adjusted in accordance with the sequence of a data sequence, so that Tmin is 1.5T and Tma
A code conversion method in which x is 4.5T and Lc is 5T is disclosed. Japanese Patent Publication No. 4-77991 discloses NRZI
There is disclosed a technique for reducing the DC component of a modulated recording signal and increasing Tmin. 4-7799
In No. 1, 8-bit data words (data elements) are sequentially cut out from an input data sequence, and each data word (data element) is converted into a 14-bit codeword. This conversion is performed so that the number of bits “0” existing between bit “1” and bit “1” in the converted code string is one or more and eight or less.
In addition, two tables for converting an 8-bit data word (data element) into a 14-bit code word (code word) are prepared, and the code word (code word) converted immediately before is converted.
Are selected based on the DSV at the end of the table. That is, NRZ
It is selected so that the DC component of the recording signal after the I modulation is reduced.

Japanese Unexamined Patent Publication No. 6-311042 discloses an NR
The DC component of the recording signal after ZI modulation is sufficiently reduced and the recording density ratio DR is increased by increasing Tmin.
(Density Ratio) is disclosed. In JP-A-6-311042, 8-bit data words (data elements) are sequentially cut out from an input data sequence, and each data word (data element) is converted into a 17-bit code word. . This conversion is performed so that the number of bits “0” existing between bit “1” and bit “1” in the converted code string is 2 or more and 9 or less. The 17-bit code word (co
deword) is obtained by adding two redundant bits to a 15-bit code corresponding to an 8-bit data word (data element). In JP-A-6-311042, two types of tables are provided for associating 8-bit data words (data elements) with 15-bit codes, and three types of 2-bit redundant bits are prepared. A 17-bit code selected from the six types of codewords obtained by combining the two types of tables and the three types of redundant bits based on the DSV at the end of the data immediately before conversion. The word (codeword) replaces the 8-bit data word (data element). That is,
With a 17-bit codeword selected to reduce the DC component of the recording signal after NRZI modulation,
The 8-bit data word (data element) is replaced.

[0014]

In each of the techniques disclosed in the above publications, redundant bits are added or a plurality of conversion tables are prepared in order to suppress a DC component or a low frequency component of a recording signal. In this case, a technique of selecting an optimum conversion table according to an input data word or the like is used. For this reason, restrictions on the above “d” and “k” are relaxed, and as a result, Tmin becomes smaller or Tmax becomes smaller.
Or the size of the image becomes large. Further, as a result of the increase in the number of bits of the code word, there is a problem that Tw is reduced and the minimum resolution is reduced.

An object of the present invention is to sufficiently suppress a DC component and a low frequency component of a recording signal and a transmission signal. Desirably, the object is to sufficiently suppress the DC component and the low frequency component of the recording signal and the transmission signal while preventing Tmin from becoming small and Tmax from becoming large. Also,
It is an object of the present invention to increase Tw and improve the resolution while sufficiently suppressing a DC component and a low frequency component of a recording signal and a transmission signal. It is another object of the present invention to reduce the reproduction error and the propagation of the reproduction error. Another object is to achieve the above object with a simple circuit configuration.

[0016]

[Means for Solving the Problems]

1. Configuration of each claim. The invention according to claim 1 is a digital modulation circuit that modulates a data sequence, wherein the multiplexer multiplexes predetermined data as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block; An RS encoder that generates a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, and data indicating a mutually different scrambling method at a position corresponding to the dummy data; An adder for adding a plurality of Reed-Solomon codes for scrambling having the same code length to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes; A setting device for setting a second Reed-Solomon code having a minimum DC component among the Solomon codes for output. It is a modulation circuit.

According to a second aspect of the present invention, there is provided a digital modulation circuit for modulating a data sequence, which multiplexes predetermined data as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block. And a Reed-Solomon encoder that uses the multiplexed block as an information
An RS encoder for generating a Reed-Solomon code, a memory for storing the first Reed-Solomon code, and data indicating a different scrambling method at a position corresponding to the dummy data; A first adder that adds a plurality of Reed-Solomon codes for scrambling having the same length to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes; and a plurality of second Reed-Solomon codes. A selector for selecting a scrambling Reed-Solomon code that gives a second Reed-Solomon code having the minimum DC component among the codes; and a first read-out device that reads the scrambling Reed-Solomon code selected by the selector from the memory. A second adder for adding the output to the Solomon code and outputting the result.

According to a third aspect of the present invention, there is provided a digital modulation circuit for modulating a data sequence, wherein a multiplexed block is generated by multiplexing predetermined data as dummy data at a predetermined position in each block in the data sequence. And a Reed-Solomon encoder that uses the multiplexed block as an information
An RS encoder for generating a Reed-Solomon code and a plurality of Reed-Solomon codes for scrambling having data indicating different scrambling methods at positions corresponding to the dummy data and having a code length equal to the first Reed-Solomon code. An adder for adding each of the first Reed-Solomon codes to generate a plurality of second Reed-Solomon codes; a memory for storing the plurality of second Reed-Solomon codes; A selector for selecting a second Reed-Solomon code having a minimum DC component among the Solomon codes; a reader for reading and outputting the second Reed-Solomon code selected by the selector from the memory;
Is a digital modulation circuit having:

According to a fourth aspect of the present invention, in any one of the first to third aspects, the adder or the first adder is determined according to a pattern of an information section in a scrambling Reed-Solomon code. RO for outputting pattern for parity section
M is a digital modulation circuit. The invention according to claim 5 is the digital modulation circuit according to any one of claims 1 to 4, wherein the predetermined data and the data indicating the scrambling method are each 8-bit data.

A sixth aspect of the present invention is the digital modulation circuit according to any one of the first to fifth aspects, wherein the predetermined position in the block to which the dummy data is multiplexed is a head position of the block. . The invention of claim 7 is claim 1
6. The multiple scrambler according to claim 5, wherein the multiplexer multiplexes two sets of bit data constituting the predetermined data at predetermined two positions in each block in a data sequence. The Reed-Solomon code is a digital modulation circuit having two sets of bit data, each of which constitutes data indicating a different scrambling method, at positions corresponding to the two positions of dummy data.

According to an eighth aspect of the present invention, in the seventh aspect, the predetermined two positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing. The digital modulation circuit is a position in the block corresponding to the head of the latter half of the code length of the Reed-Solomon code.

According to a ninth aspect of the present invention, in any one of the first to fifth aspects, the multiplexer is configured to divide four sets of bit data constituting the predetermined data into each block in a data sequence. Multiplexed at predetermined four positions, the plurality of scrambling Reed-Solomon codes each have four sets of bit data constituting data indicating the mutually different scrambling methods at positions corresponding to the dummy data at the four positions. ,
It is a digital modulation circuit.

According to a tenth aspect of the present invention, in the ninth aspect,
The four predetermined positions in the block to which the dummy data are multiplexed are the head position of the block and the code length of the Reed-Solomon code having a data length after the dummy data multiplexing as an information portion. This is a digital modulation circuit, which is each position in the block corresponding to each head of the quarter and the quarter.

The invention of claim 11 is the invention of claims 1 to 5
In any one of the above, the multiplexer multiplexes eight sets of bit data constituting the predetermined data at predetermined eight positions in each block in a data sequence, and the plurality of scrambling Reed-Solomon codes. Is a digital modulation circuit having eight sets of bit data constituting data indicating the mutually different scrambling methods at positions corresponding to the eight positions of dummy data.

According to a twelfth aspect of the present invention, in the eleventh aspect, the predetermined eight positions in the block to which the dummy data is multiplexed include the head position of the block and the data length after the dummy data multiplexing. 1/8 half, 2/8 half, 3/8 half, 4/8 code length of Reed-Solomon code
This is a digital modulation circuit, which is each position in the block corresponding to each head of half, 5/8 half, 6/8 half, and 7/8 half.

The thirteenth aspect of the present invention relates to the first to fourth aspects.
Wherein t is 4 and the multiplexer is:
The predetermined element of the Galois field GF (2 ⁴ ) is defined as the beginning of each block in the data series and the Galois field GF (2 ⁴ )
Are multiplexed at positions in a block corresponding to the beginning of the latter half of the code length of a Reed-Solomon code having a data length obtained by adding two elements to the multiplexed block to generate a multiplexed block. The first adder has an element of a different Galois field GF (2 ⁴ ) at the head and an element of a different Galois field GF (2 ⁴ ) at the head of the latter half of the code length, and A plurality of Reed-Solomon codes for scrambling having the same code length as the first Reed-Solomon code
A digital modulation circuit that generates a plurality of second Reed-Solomon codes by adding to a Reed-Solomon code.

According to a fourteenth aspect of the present invention, there is provided the first aspect of the invention.
Wherein t is 2 and the multiplexer is:
The predetermined element of the Galois field GF (2 ² ) is defined as the beginning of each block in the data sequence and the Galois field GF (2 ² )
The code length of a Reed-Solomon code having a data length obtained by adding four elements to the information part is 1/4 half, 2/4 half, and 3/4.
Each of the multiplexed blocks is multiplexed at each position in a block corresponding to each head of the half to generate a multiplexed block, and the adder or the first adder calculates an element of a Galois field GF (2 ² ) different from each other. An element of a Galois field GF (2 ² ) having a head and different from each other has an element of a Galois field GF (2 ² ) at the head of the quarter of the code length and an element of a Galois field GF (2 ² ) different from the code length 2 / A plurality of elements having a Galois field GF (2 ² ) at the head of the quarter and different from each other, having an element at the head of the code length of 3/4 and having a code length equal to the first Reed-Solomon code; A digital modulation circuit for adding a Reed-Solomon code for scrambling to each of the first Reed-Solomon codes to generate a plurality of second Reed-Solomon codes.

According to a fifteenth aspect of the present invention, in the digital modulation method for modulating a data sequence, predetermined data is multiplexed as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block. A first Reed-Solomon code is generated by performing Reed-Solomon encoding using the multiplexed block as an information part, and data indicating a mutually different scrambling method is provided at a position corresponding to the dummy data. A plurality of Reed-Solomon codes for scrambling having the same length,
Adding to the Reed-Solomon code to generate a plurality of second Reed-Solomon codes, and setting a second Reed-Solomon code having a minimum DC component among the plurality of second Reed-Solomon codes for output; Modulation method.

The invention according to claim 16 is the digital modulation method according to claim 15, wherein the predetermined data and the data indicating the scrambling method are each 8-bit data.

The invention according to claim 17 is the digital modulation method according to claim 15 or 16, wherein a predetermined position in a block to which the dummy data is multiplexed is a head position of the block.

According to an eighteenth aspect of the present invention, in the digital modulation method for modulating a data sequence, two sets of bit data constituting predetermined data are set as dummy data at two predetermined positions in each block in the data sequence. Multiplexing to generate a multiplexed block, Reed-Solomon encoding using the multiplexed block as an information part to generate a first Reed-Solomon code, and combining two sets of bit data constituting data indicating mutually different scrambling methods. Adding a plurality of scrambling Reed-Solomon codes at positions corresponding to the two positions of dummy data and having the same code length as the first Reed-Solomon code to the first Reed-Solomon code,
A plurality of second Reed-Solomon codes are generated, and a second DC signal having a minimum DC component among the plurality of second Reed-Solomon codes is generated.
This is a digital modulation method for setting a Reed-Solomon code for output.

According to a nineteenth aspect of the present invention, in the twentieth aspect, the predetermined two positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing. This is a digital modulation method that is a position in the block corresponding to the head of the latter half of the code length of the Reed-Solomon code to be used as a part.

According to a twentieth aspect of the present invention, in the digital modulation method for modulating a data sequence, four sets of bit data constituting predetermined data are set as dummy data at predetermined four positions in each block in the data sequence. Multiplexing to generate a multiplexed block, Reed-Solomon coding using the multiplexed block as an information part to generate a first Reed-Solomon code, and four sets of bit data constituting data indicating mutually different scrambling methods. Adding a plurality of scrambling Reed-Solomon codes at positions corresponding to four positions of the dummy data and having the same code length as the first Reed-Solomon code to the first Reed-Solomon code,
A plurality of second Reed-Solomon codes are generated, and a second DC signal having a minimum DC component among the plurality of second Reed-Solomon codes is generated.
This is a digital modulation method for setting a Reed-Solomon code for output.

According to a twenty-first aspect of the present invention, in the twentieth aspect, the predetermined four positions in the block to which the dummy data is multiplexed include information indicating a head position of the block and a data length after the dummy data multiplexing. This is a digital modulation method in which each position in the block corresponds to each head of a code length of 1/4 half, 2/4 half, and 3/4 half of a Reed-Solomon code to be set.

According to a twenty-second aspect of the present invention, in a digital modulation method for modulating a data sequence, eight sets of bit data constituting predetermined data are set as dummy data at predetermined eight positions in each block in the data sequence. Multiplexing to generate a multiplexed block; Reed-Solomon encoding using the multiplexed block as an information part to generate a first Reed-Solomon code; Adding a plurality of scrambling Reed-Solomon codes at positions corresponding to the eight positions of the dummy data and having the same code length as the first Reed-Solomon code to the first Reed-Solomon code,
A plurality of second Reed-Solomon codes are generated, and a second DC signal having a minimum DC component among the plurality of second Reed-Solomon codes is generated.
This is a digital modulation method for setting a Reed-Solomon code for output.

According to a twenty-third aspect of the present invention, in the twenty-second aspect, the predetermined eight positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing. 1/8 half, 2/8 half, 3/8 half, 4/8 code length of Reed-Solomon code
This is a digital modulation circuit, which is each position in the block corresponding to each head of half, 5/8 half, 6/8 half, and 7/8 half.

The invention of claim 24 modulates a data sequence.
In a digital modulation method, the Galois field GF (2^Four )
Is defined as the head of each block in the data sequence and 1
Galois body GF (2^Four ) Is added to two elements
Length of Reed-Solomon code with data length as information part
Multiplex each at the position in the block corresponding to the beginning of the latter half.
To generate a multiplexed block and store the multiplexed block in information.
The first Reed-Solomon encoded by Reed-Solomon
And generate different Galois fields GF (2 ^Four )of
Galois fields GF (2^Four )
At the beginning of the latter half of the code length and the first
Multiple scrambles with the same code length as the Dosolomon code
For the first Reed-Solomon code.
Code to generate a plurality of second Reed-Solomon codes.
And a direct current among the plurality of second Reed-Solomon codes.
Set the second Reed-Solomon code with minimum component for output
This is a digital modulation method.

According to a twenty-fifth aspect of the present invention, in a digital modulation method for modulating a data sequence, a Galois field GF (2 ² )
Is defined as the head of each block in the data sequence and 1
The code length of a Reed-Solomon code of 1/4 half, 2/4 half, and 3/4 half each having a data length obtained by adding four elements of Galois field GF (2 ² ) to a block as an information part Each of the multiplexed blocks is multiplexed at each position in the block corresponding to the head to generate a multiplexed block, and the multiplexed block is subjected to Reed-Solomon encoding using the multiplexed block as an information part to generate a first Reed-Solomon code. The element of (2 ² ) at the head and the element of Galois field GF (2 ² ) different from each other
Galois body GF at the beginning of the quarter and different from each other
The element of (2 ² ) is at the head of the code length 2/4 half, and the elements of the Galois field GF (2 ² ) different from each other are the code length 3
A plurality of second Reed-Solomon codes are added to the first Reed-Solomon code, each having a code length equal to that of the first Reed-Solomon code at the beginning of the quarter and being equal to the first Reed-Solomon code. A digital modulation method of generating a code and setting a second Reed-Solomon code having a minimum DC component among the plurality of second Reed-Solomon codes for output.

According to a twenty-sixth aspect of the present invention, there is provided a digital demodulation circuit for demodulating a data sequence of a Reed-Solomon code,
An RS decoder for error-correcting the Reed-Solomon code using a parity part, and scrambling used for conversion to the Reed-Solomon code based on data output from the RS decoder and indicating a scrambling method of a predetermined position of the Reed-Solomon code Demodulation circuit comprising: a detector for detecting a Reed-Solomon code for use; and an adder for adding the Reed-Solomon code for scrambling detected by the detector to the Reed-Solomon code output from the RS decoder and outputting the result. It is.

According to a twenty-seventh aspect, in the twenty-sixth aspect, the predetermined position is any one of a predetermined one position, a predetermined two positions, a predetermined four positions, and a predetermined eight positions. It is.

According to a twenty-eighth aspect of the present invention, in a digital demodulation method for demodulating a data sequence of a Reed-Solomon code,
The Reed-Solomon code is error-corrected using a parity part,
The scrambled Reed-Solomon code used for conversion to the Reed-Solomon code is detected based on data indicating a scramble method at a predetermined position of the error-corrected Reed-Solomon code, and the error-corrected Reed-Solomon code is A digital demodulation method for adding and outputting the detected scrambling Reed-Solomon code.

According to a twenty-ninth aspect of the present invention, in the digital demodulation method according to the thirtieth aspect, the predetermined position is any one of a predetermined one position, a predetermined two positions, a predetermined four positions, and a predetermined eight positions. It is.

According to a thirtieth aspect of the present invention, there is provided a digital modulator for inputting a data stream and converting the data stream into a bit stream, wherein a predetermined data element is multiplexed as dummy data at a predetermined position in a block sequentially cut out from the data stream. A multiplexer that generates a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, and identification information indicating a scrambling method in the same position as the dummy data. A plurality of types of scrambling Reed-Solomon codes, each having a code length of an information part and a parity part equal to the first Reed-Solomon code, are respectively added to the first Reed-Solomon code to form a plurality of types of second Reed-Solomon codes. An adder to be generated and a desired adder among the plurality of types of second Reed-Solomon codes. A second selector for selected Reed-Solomon code output having a characteristic, a digital modulator having.

The invention according to claim 31 is the digital modulator according to claim 30, wherein the selector selects and outputs a second Reed-Solomon code having a minimum DC component after modulation in the bit stream. . The invention according to claim 32 is the digital modulator according to claim 30, wherein the adder has a memory that outputs a pattern for a parity section determined according to a pattern of an information section in the scrambling Reed-Solomon code. is there.

A thirty-third aspect of the present invention is the digital modulator according to the thirty-second aspect, wherein the memory is a ROM. According to a thirty-fourth aspect, in the thirty-fourth aspect, the multiplexer multiplexes a first half and a second half of the predetermined data element at predetermined two positions in the block as dummy data, and The scrambling Reed-Solomon code is a digital modulator having the first half and the second half of the data elements constituting the identification information at the same positions as the two positions of the dummy data.

A thirty-fifth aspect of the present invention is a digital modulation method for inputting a data stream and converting it into a bit stream, wherein a predetermined data element is multiplexed as dummy data at a predetermined position in a block sequentially cut out from the data stream. Generating a first Reed-Solomon code by performing Reed-Solomon encoding by using the multiplexed block as an information part, having identification information indicating a scrambling method at a position corresponding to the dummy data, and A plurality of types of second Reed-Solomon codes are generated by adding a plurality of types of scrambling Reed-Solomon codes each having a code length equal to one Reed-Solomon code to the first Reed-Solomon code, respectively. Select and output a second Reed-Solomon code having desired characteristics A digital modulation method. The invention according to claim 36 is the digital modulation method according to claim 35, wherein the desired characteristic used for selecting the second Reed-Solomon code is a characteristic in which a DC component after modulating a bit stream is a minimum. .

According to a thirty-seventh aspect of the present invention, there is provided a digital demodulator for demodulating a Reed-Solomon code cut out from a bit stream and decoded, wherein the RS decoder corrects an error in the Reed-Solomon code and output from the RS decoder. A detector for detecting a scrambling Reed-Solomon code used for conversion to the Reed-Solomon code based on identification information of a predetermined position in the Reed-Solomon code,
An adder for adding a Reed-Solomon code for scrambling detected by the detector to the Reed-Solomon code output from the RS decoder and outputting the result.

A thirty-eighth aspect of the present invention is a digital demodulation method for demodulating a Reed-Solomon code cut out from a bit stream and decoded, wherein the Reed-Solomon code is error-corrected and a predetermined position of the error-corrected Reed-Solomon code is corrected. The scrambling Reed-Solomon code used for conversion to the Reed-Solomon code is detected based on the identification information, and the detected scrambled Reed-Solomon code is added to the error-corrected Reed-Solomon code to obtain the original data. This is a digital demodulation method for demodulation.

2. Galois field and Reed-Solomon code. The Galois field and Reed-Solomon code used in the present invention will be briefly described. On the Galois field GF (2 ^t ), four arithmetic operations can be performed on 2 ^t types of numbers (elements). Addition / subtraction on the Galois field GF (2 ^t ) is mo in vector representation.
The operation is d2, and the results of addition and subtraction are the same.

In the RS (Reed-Solomon) code, a code word is composed of a Galois field element, and one code word is associated with a t-bit element of the Galois field. In other words, data is handled with t bits as 1 byte, and each 1-byte data is expressed as a Galois field element on GF (2 ^t ).

Code polynomial W which is a polynomial expression of RS code
(X) is obtained by shifting the information polynomial I (x) by 2 s to I (x) x ^2s, and ^{converting the} I (x) x ^2s to the generator polynomial G
The remainder polynomial P (x) is obtained by dividing by (x), and the obtained remainder polynomial P (x) is obtained by connecting the obtained information polynomial I (x) x ^2s after shifting by 2 s bytes. That is,

Obtains a remainder polynomial P (x) as Equation 1] ^{I (x) x 2s modG (} x) = P (x), using the P (x),

## EQU2 ## It is expressed as W (x) = I (x) x ^2s + P (x). Here, AmodB is the remainder when A is divided by B.

The received polynomial R (x), which is a polynomial expression of the received RS code, is:

R (x) = W (x) + E (x) = I (x) x ^2s + P (x) + E (x) Here, E (x) is an error polynomial expressing the error that has occurred.

The syndrome polynomial S (x) for checking whether an error has occurred is obtained by dividing the reception polynomial R (x) by the generator polynomial G (x). That is, as shown at the top of FIG.

S (x) = R (x) modG (x) = {W (x) + E (x)} modG (x) = E (x) modG (x) As is apparent from this [Equation 4],
If an error occurs, the syndrome polynomial S
(X) becomes indivisible by the generator polynomial G (x). As a result, error correction becomes possible. However, the condition is that the error is s bytes or less. [Equation 4] utilizes that the code polynomial W (x) is divisible by the generator polynomial G (x).

3. Principle of the present invention. In the present invention, a plurality of types of scrambling code polynomials Y1 (x) and Y2 (x) are added to a code polynomial W (x) obtained from a block (= a data word (data element) having a predetermined number of bits) sequentially cut out from a data sequence. ), Yj (x) in FIG.
(However, in FIG. 1, these are represented by Y (x) as representatives) and a plurality of types of code polynomials W ″ 1 are added.
(x), W "2 (x), W" j (x) are generated (however, they are represented as W "(x) in FIG. 1), and the plurality of types of code polynomials W" 1 (x), W "2 (x) ,, W"
A code polynomial having desired characteristics is extracted from j (x). For example, a code polynomial W ″ (x) that minimizes the DC component of the recording code is extracted. The extracted code polynomial W ″ (x) is subjected to RLL modulation or NR as needed.
ZI modulation is performed and set for recording.

In the present invention, the original code polynomial W
(X) reception polynomial R (x) and syndrome polynomial S
The above discussion on (x) is based on the above-mentioned plural types of code polynomials W ″ 1 (x), W ″ 2 generated by scrambling.
(x), and the reception polynomial R "i (x) and the syndrome polynomial S" i (x) of W "i (x), which are code polynomials extracted from W" j (x) (here, , I indicate the extracted ones). That is, the same holds true, that is, the lowermost equation in FIG.

S "(x) = R" (x) modG (x) = {W "(x) + E (x)} modG (x) = E (x) modG (x) becomes W" i ( Using the fact that the reception polynomial R ″ i (x) of x) and the syndrome polynomial S ″ i (x) are satisfied, the reception polynomial R ″ i (x) is decoded on the decoder side that decodes the original data sequence from the reproduced signal. After correcting the error, the code polynomial W ″ i
(x) is obtained. FIG. 2 shows W ″ (x), E
(X) and R ″ (x).

According to the present invention, on the decoder side for decoding the original data sequence from the reproduced signal, the code polynomial W "i (x) is replaced by the error-corrected code polynomial W" i (x).
The original code polynomial W (x) is obtained by adding the scrambling code polynomial Yi (x) used for the generation of.

Further, in the present invention, since the scramble code polynomial Yi (x) needs to be added on the decoder side for decoding the original data sequence from the reproduced signal, the scramble code polynomial Yi (x) Is detected from the error-corrected code polynomial W ″ i (x). In other words, the identification information is added to the code polynomial W ″ i (x). Specifically, the data in the code polynomial W ″ i (x) at the same position as the dummy data added in the original code polynomial W (x) is detected as identification information. Will be described later.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION Circuit configuration. FIG. 5 is a block diagram of a modulation circuit according to the embodiment, and FIG.
FIG. 3 is a block diagram showing details of the vicinity of a j-type EX-OR unit 20 in FIG. FIG. 4 shows the dummy data multiplexer 11 in FIG.
3 shows the data structures of the input / output signals (a) and (b), the input / output signals (b) and (c) of the RS encoder 13 and the output signal (d) of the first EX-OR unit 21.

The modulation circuit shown is a circuit that extracts and modulates a code polynomial W ″ (x) that minimizes the DC component of the recording signal. That is, each block in the data sequence input from the input terminal 10 As shown in the second row of FIG. 4, a predetermined element of the Galois field GF (2 ^t ) (for example:
A multiplexer 11 for multiplexing the zero element “00000000” of the Galois field GF (2 ⁸ )) as dummy data, and Reed-Solomon encoding of the multiplexed block after the dummy data multiplexing as an information part are shown in the third row of FIG. RS encoder 13 for generating Reed-Solomon code (first Reed-Solomon code)
Then, a plurality of types (j types) of Reed-Solomon codes for scrambling are added to the first Reed-Solomon code output from the RS encoder 13, and j types of second Reed-Solomon codes shown in the fourth stage (d) of FIG. J-type EX-OR unit 20 for generating
(Including a j-type conversion data generator 25 and a first EX-OR unit 21) and a D-type
A j-type DSV calculator / comparator 23 for selecting a second Reed-Solomon code that minimizes the absolute value of the SV (Digital Sum Value), and a scrambling Reed-Solomon code for providing the selected second Reed-Solomon code are output. A j-type conversion data generator 25 in the j-type EX-OR unit 20, a memory 15 for storing a first Reed-Solomon code output from the RS encoder 13, and a first Reed-Solomon read from the memory 15. A second EX-OR unit 31 that adds the code and the scrambling Reed-Solomon code output from the j-type conversion data generator 25 and outputs a second Reed-Solomon code having the minimum absolute value of DSV; OR
An RLL encoder 33 for RLL modulating the output of the encoder 31;
It has an NRZI modulator 35 for performing NRZI modulation on the output of the LL encoder 33, and an output terminal 40 for outputting the output of the NRZI modulator 35 to the outside.

The dummy data multiplexer 11 is provided at the beginning of a block of a predetermined number of bits (see the uppermost row in FIG. 4) which is sequentially cut out from the data sequence (data stream) input from the input terminal 10, and the second row in FIG. As shown in the figure, the Galois field G
A predetermined element of F (2 ^t ) (eg, 0 of Galois field GF (2 ⁸ )
The original “00000000”) is multiplexed as dummy data. The block after the dummy data multiplexing is referred to as a multiplexed block in this specification.

The RS encoder 13 performs Reed-Solomon encoding using the multiplexed block as an information part to generate a Reed-Solomon code (hereinafter, referred to as a “first Reed-Solomon code”) shown in the third row of FIG.

The j-type EX-OR unit 20 adds a plurality of types (j types) of scrambling Reed-Solomon codes to the first Reed-Solomon code, and outputs a plurality of types (j) shown in the fourth row (d) of FIG. j types) of Reed-Solomon codes (hereinafter referred to as “second
Reed-Solomon code "). That is, j
A plurality of types (j types) of Reed-Solomon codes for scrambling are supplied from the type conversion data generator 25 to the first EX-OR unit 21.
Then, the first EX-OR unit 21 adds the first Reed-Solomon code to the first Reed-Solomon code to generate a plurality of types (j types) of second Reed-Solomon codes. Note that a plurality of types (j
) Corresponds to the aforementioned Y1 (x), Y2 (x),..., Yj (x). Also,
A plurality of types (j types) of second Reed-Solomon codes correspond to the aforementioned W ″ 1 (x), W ″ 2 (x),..., W ″ j (x).

The j-type DSV calculator / comparator 23 selects one of a plurality of types (j types) of second Reed-Solomon codes from the DS
The second Reed-Solomon code that minimizes the absolute value of V (Digital Sum Value) is extracted. That is, the second Reed-Solomon code that minimizes the DC component and the low frequency component of the recording signal is extracted. Also, information indicating the scrambling Reed-Solomon code used for generating the second Reed-Solomon code is j
The data is output to the type conversion data generator 25. The second Reed-Solomon code having the minimum absolute value of DSV corresponds to the aforementioned W ″ i (x). Hereinafter, this is referred to as the minimum second Reed-Solomon code. Since the second Reed-Solomon code having the minimum DC component after modulation in the bit stream is selected as the Solomon code, j-type DSV calculator / comparator 23 is provided. If another characteristic is adopted as the characteristic when selecting the above, a circuit element corresponding to the other characteristic may be provided instead of the j-type DSV calculator / comparator 23.

The j-type conversion data generator 25 sequentially outputs a plurality of (j-type) scrambling Reed-Solomon codes to the first EX-OR unit 21 as described above.
j kinds of scramble leads specified by information (information indicating a scramble Reed-Solomon code used when generating the minimum second Reed-Solomon code from the first Reed-Solomon code) from the DSV calculator / comparator 23 The Solomon code is output to the second EX-OR unit 31. The scrambling Reed-Solomon code used for generating the minimum second Reed-Solomon code corresponds to Yi (x) described above.

The memory 15 stores the first Reed-Solomon code input from the RS encoder 13.

The second EX-OR unit 31 adds the first Reed-Solomon code and the scrambling Reed-Solomon code used for generating the minimum second Reed-Solomon code, and performs RLL.
Output to encoder 33. That is, the minimum second Reed-Solomon code is output to the RLL encoder 33.

The RLL encoder 33 is a second EX-OR unit.
The minimum second Reed-Solomon code output from 31 is RLL-modulated and output to the NRZI modulator 35.

The NRZI modulator 35 is an RLL encoder 33
Is subjected to NRZI modulation and output to the outside via an output terminal 40.

Next, a predetermined 8-bit data element "00"
The case where two sets of 4-bit data elements “0000” and “0000” constituting “00000000” are multiplexed at two predetermined positions (the head and the center in this example) in a block cut out from the data stream is described with the above circuit. This will be described with reference to FIGS.

First, in the multiplexer 11, two sets of 4-bit data elements "0000" and "0000" constituting a predetermined 8-bit data element "00000000" are cut out from the data stream (data sequence) ( k-1) The beginning of a block of bytes and the latter half of the code length of a u-byte Reed-Solomon code having a data length of k bytes, which is a data length obtained by adding two 4-bit data to one block, that is, 1 byte in total. Position in the block corresponding to the head (position of (k- (u-1) / 2) bytes from the end in the block)
Are multiplexed as dummy data (see the top row of FIG. 7). Note that the data length of this multiplexed block is k bytes.

Next, the RS encoder 13 generates a u-byte first Reed-Solomon code using the multiplexed block as an information part (see the middle part of FIG. 7). That is, (uk)
A byte parity code is added. Hereinafter, the first half of the first Reed-Solomon code is referred to as a first data item, and the second half is referred to as a second data item (see the lowermost part of FIG. 7).

While storing the first data item in the memory 15, the first data item is scrambled as follows.

First, j-type conversion data information section generator 25
3 shows that 16 types of 4-bit data shown in the upper part of FIG.
u times, and the first EX-
Sent to OR unit 21. That is, 16 types of (u / 2) bytes of data are sent to the first EX-OR unit 21.

In the first EX-OR unit 21, E for each bit
X-OR processing is performed. As a result, 16 types of first data items (the first half of the second Reed-Solomon code) are generated for the first data items shown in the lower part of FIG.
At this time, the first 4 items of each of the 16 types of first data items
Since the dummy data is “0000” as described above, the bit becomes the identification information as it is.

The 16 types of first data items (the first half of the second Reed-Solomon code) generated as described above are j
Kind is sent to the DSV calculator / comparator 23, from which D
The first data item (the first half of the minimum second Reed-Solomon code) having the smallest absolute value of SV is obtained. That is, the first data item (the first half of the minimum second Reed-Solomon code) in which the DC component and the low frequency component of the recording signal are minimized is obtained. Further, the scramble pattern used to generate the data item is stored in the conversion data storage 251.

Subsequently, the second data item is scrambled. At the same time, the second EX-OR unit 31 converts the first data item stored in the memory 15 using the scramble pattern stored in the conversion data storage unit 251. That is, the first stored in the memory 15
The data item is read and sent to the second EX-OR unit 31, and the scramble pattern stored in the conversion data storage unit 251 is repeated u times and sent to the second EX-OR unit 31, where it is sent to the second EX-OR unit 31. Add (EX-OR)
Processing is performed. As a result, the first half of the second Reed-Solomon code is generated. This first half is indicated by “****” in FIG.

On the other hand, the j-type conversion data information section generator 25
8, the 16 types of 4-bit data shown in the lower part of FIG. 8 are repeated (2ku) times and sent to the first EX-OR unit 21 via the first selector 257, and then the j types of The 16 kinds of data of the parity units (0) to (15) shown in FIG. 9 are sent from the conversion data parity unit generator 255 to the first EX-OR unit 21 via the first selector 257. As a result, scrambling for the second data item is performed.

The data of the parity units (0) to (15) are generated as shown in FIG. That is, the scramble pattern “*” that minimizes the absolute value of the DSV for the first data item
*** "in the first half and 16 types of scramble patterns shown in the lower part of FIG. 8 in the latter half of the information word part (for 4 bits (2k-u) times) are read. Generated by performing Solomon encoding, where the scramble pattern “****” is used.
Is supplied from the conversion data storage 251 to the j-type conversion parity generator 255. Note that the j-type conversion data parity part generator 255 uses a combination of the scramble pattern "****" for the first data item and the scramble patterns "0000" to "1111" for the information part in the second data item. , The parity (0) to the parity (1)
It may be composed of a ROM or the like that outputs 16 types of data items for the parity section 5).

For the second data item thus generated, a scramble pattern that minimizes the absolute value of the DSV is obtained and stored in the conversion data storage 251 in substantially the same manner as in the case of the first data item. That is, a scramble pattern that minimizes the DC component and the low frequency component of the recording signal is obtained and stored. In the case of the second data item, a scramble pattern “####” for 4 (2ku) bits of the information part in the second data item is stored.

Next, when the first data item of the next block is scrambled in the same manner as described above, the scramble pattern "####" is transferred from the conversion data storage unit 251 (2ku) times. 2nd EX via 2 selector 259
The first sent to the OR unit 31 and read from the memory 15
It is added to the information part in the second data item of the Reed-Solomon code. Subsequently, the scramble pattern “****” for the first data item and the scramble pattern “####” for the second data item are sent to the j-type conversion data parity part generator 255. (****, ##
##), the data item of the conversion data parity part (any of parity (0) to parity (15)) is j
The data is sent from the type conversion data parity part generator 255 to the second EX-OR unit 31 via the second selector 259,
15 is added to the parity part in the second data item of the first Reed-Solomon code. The minimum second Reed-Solomon code thus generated is RLL-modulated and N
RZI modulated.

In the above description, two sets of 4-bit data elements “0000” and “0000” constituting a predetermined 8-bit data element “00000000” are stored in two predetermined positions in the block (in the above example, read This is a process for multiplexing data at the start position and the center position in the Solomon code. A predetermined 8-bit data element "00000000" is multiplexed at one predetermined position in the block (for example, the start position in the Reed-Solomon code). 12 or four sets of 2-bit data elements "00", "00", "00", and "0" constituting a predetermined 8-bit data element "00000000".
0 ”is assigned to four predetermined positions in the block (for example, the start position, the ４ position, the 位置 position, and the 3 position in the Reed-Solomon code).
In the case shown in FIG. 14 where data is multiplexed at (/ 4 position), the processing can be performed in substantially the same manner. Also, a predetermined 8-bit data element "0"
00000000 ”to“ 000 ”“ 00000 ”
In the case of multiplexing as a 5-bit data element with a 5-bit data element, or in the case of multiplexing with a 2-bit data element of "00" and "000000" as a 6-bit data element, processing can be performed in substantially the same manner. Although not shown, the same processing can be performed in the case of multiplexing at predetermined eight positions in a block.

The bit width t constituting the element of the Galois field of the RS code may be any value. When t is changed, the configurations of the RS encoder 13 and the j-type conversion parity part generator 255 are different from those in the above example. In other words, R
S encoder 13 and j-type conversion parity part generator 255
The circuit configuration is different for GF (2 ⁸ ), GF (2 ⁴ ), GF (2 ² ), etc., but the above processing method does not change. In the RLL decoding, the RS decoding, and the inverse transform using the RS code, it is assumed that bit synchronization is established. For this reason, in the figure, SYNC is added before the RS code to aid understanding. If the bit synchronization can be achieved, the SYNC insertion interval may be made longer.

FIG. 10 shows a modification of the modulation circuit.
[A] is an example configured in the same way as FIG. 5, and [B] is j
This is an example in which all kinds of second Reed-Solomon codes (W ″ (x)) are stored in the memory 150. [A]
There is an advantage that the memory 15 needs only a small capacity.
[B] has an advantage that the second EX-OR unit 31 of [A] becomes unnecessary.

The code modulated as described above is shown in FIG.
1 is demodulated by the demodulation circuit shown in FIG. That is, the input terminal
The reproduction signal (bit stream) input from 50 is converted to NR
An NRZI demodulator 51 for ZI demodulation, an RLL decoder 52 for RLL demodulation of the NRZI demodulated signal, an RS decoder 53 for error correction of the RLL demodulated Reed-Solomon code using a parity part, and an error corrected and output from the RS decoder 53 Based on information multiplexed at the position of the dummy data of the Reed-Solomon code (corresponding to the above-mentioned minimum second Reed-Solomon code), the scrambling Reed-Solomon code used for conversion to the Reed-Solomon code is detected. EX-OR for adding a Reed-Solomon code for scrambling detected by the detector 54 to the Reed-Solomon code output from the RS decoder 53 after error correction.
The signal output from the EX-OR device 55 and the output terminal 60 is demodulated by a digital demodulation circuit having an output terminal 60 for outputting the signal to the outside.

Note that the detector 54 is a scramble pattern of the above-described modulation circuit (for example, 16 types of patterns in FIG. 8).
It is assumed that data necessary for identifying the data is built in in common with the modulation circuit, and also has information (for example, “0000”) on the dummy data in common.

FIGS. 15 to 17 are characteristic diagrams showing the effect of the convolution process and the effect of the Galois field addition type process of the present invention in comparison with the Galois field multiplication type process.
Is a characteristic diagram showing the RS code and GF each symbol error rate ⁽²⁸⁾ Galois addition on (the block 1 located multiplex) type and convolution (1,2,4,8 bits). Note that the symbol error rate of the Galois field multiplication type is almost the same as that of the Galois field addition type, and is not shown.

The convolution process means that a plurality of types (j types) of a bits added to the head of a target block are used as a code conversion unit, and EX-OR data conversion is sequentially performed from the top a bits to j types of conversion blocks. This is a processing method in which a DC block having a minimum DC component is selected and output from the generated block, thereby suppressing the DC component of the signal waveform sequence and preventing error propagation. Demodulation of convolution processing
EX-OR data conversion (reverse conversion) in order from the head a bit using the head a bit of the reproduction block as a code conversion unit
Is performed. The convolution processing is described in Japanese Patent Application No. 8-87335 filed by the present applicant.
It is described in Japanese Patent Application Nos. 8-291171 and 8-314306.

The Galois field multiplication type processing is a Galois field GF
The target block to which (2 ^t ) dummy data (eg, “11111111”) is added at the beginning is multiplied by a plurality of types (j types) of Galois fields to generate j types of conversion data, and the DC component is minimized from the converted data. Is a processing method that suppresses the DC component of the signal waveform sequence and enables error correction by selecting and outputting the conversion block of (1). The demodulation of the Galois field multiplication type processing is performed by identifying the Galois field multiplied based on the t bits at the head of the reproduction block and dividing by the Galois field. As for the Galois field multiplication type processing, Japanese Patent Application No. Hei 7-262141 filed by the present applicant,
Japanese Patent Application No. 8-87335, Japanese Patent Application No. 8-291171,
It is described in Japanese Patent Application No. 8-314306.

As can be seen from FIGS.
2 constituting a bit data element "00000000"
Processing of the present invention for multiplexing a set of bit data elements "0000" and "0000" at two predetermined positions in a block, or for multiplexing a predetermined 8-bit data element "00000000" at a predetermined one position in a block Has the same characteristics as the 255 types of Galois field multiplication types, and the circuit configuration in that case can be greatly simplified as compared with the 255 types of Galois field multiplication types. Further, four sets of 2s constituting a predetermined 8-bit data element “00000000”
Bit data element “00” “00” “00” “00”
Is multiplexed at predetermined four positions in the block, the circuit configuration can be further simplified and the characteristics can be satisfied. FIGS. 16 and 17 show the results of a simulation using an element on GF (2 ⁸ ) and a code length of 80 bytes as the RS code. FIG.
As can be seen from the above, the characteristics of the symbol error rate of the Galois field addition type are close to the characteristics of the RS code, and are better than the convolution processing. However, FIG. 18 shows the result of a simulation using 72 bytes of information bytes and 8 bytes of parity bytes.

In the above description, the second Reed-Solomon code having the minimum DC component after the NRZI modulation is the second Reed-Solomon code having the desired characteristics after the NRZI modulation among the second Reed-Solomon codes. Selected,
Alternatively, for example, (d, ∞) R
It is also possible to use an LL code and select a second Reed-Solomon code that minimizes the maximum inversion interval k after modulation. In that case, there is an effect that an accurate clock can be easily extracted. A configuration is also conceivable in which a new parameter is generated by adding a certain weight to the parameter k and the parameter DSV, and the second Reed-Solomon code that minimizes the parameter is selected. In that case,
There is an effect that the DC component of the modulation data can be suppressed while extracting an accurate clock.

[0091]

According to the present invention, a multiplexed block is generated by multiplexing dummy data at an arbitrary position in a block cut out sequentially from a data sequence, and this multiplexed block is subjected to Reed-Solomon encoding as an information part to perform a first read. Generating a Solomon code, having a data element indicating a mutually different scrambling method at the same position as the dummy data, and
A plurality of second Reed-Solomon codes are generated by adding a plurality of Reed-Solomon codes, a plurality of scrambling Reed-Solomon codes having the same data length of the information section and the parity section to the first Reed-Solomon code, respectively, Since a second Reed-Solomon code having a desired characteristic among a plurality of second Reed-Solomon codes (for example, a second Reed-Solomon code having a minimum DC component of a recording signal) is set for output, it is used for recording or transmission. Signal waveform sequence having desired characteristics can be obtained. For example, when the second Reed-Solomon code having the minimum DC component of the recording signal is selected, the reproduction error can be reduced, the propagation thereof can be reduced, and these can be achieved with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 shows a code polynomial W ″ (x) after conversion by adding a scramble polynomial Y (x) to a code polynomial W (x) before conversion.
FIG. 3 is an explanatory diagram showing the concept of the present invention for generating a slash.

FIG. 2 is a reception polynomial R ″ of the present invention in a form in which an error polynomial E (x) is added to a converted code polynomial W ″ (x).
Explanatory drawing showing that (x) is described.

FIG. 3 shows a syndrome polynomial S (x) of a code polynomial W (x) before conversion and a scramble code Y for the W (x).
(X) and the converted code polynomial W ″ obtained by adding
Explanatory drawing which shows that the syndrome polynomial S "(x) of (x) is equal.

FIG. 4 is an explanatory diagram showing an output of each block in the circuit of FIG. 5;

FIG. 5 is a block diagram of a modulation circuit according to an embodiment;

FIG. 6 is a block diagram showing a j-type conversion data generator 25 of FIG. 5;

FIG. 7 is an explanatory diagram showing a scrambling method when dummy data added to the head of a block is 4 bits.

FIG. 8 is an explanatory diagram showing a part of the scramble pattern for the first data and the scramble pattern for the second data in FIG. 7;

FIG. 9 is an explanatory diagram showing the rest of the scramble pattern for the second data in FIG. 7;

FIG. 10 is a block diagram showing a modification of the modulation circuit of the embodiment.

FIG. 11 is a block diagram of a demodulation circuit according to an embodiment;

FIG. 12 is an explanatory diagram showing a scrambling method and identification information when dummy data added to the head of a block is 8 bits.

FIG. 13 is an explanatory diagram showing a scrambling method and identification information when dummy data added to the head of a block is 4 bits.

FIG. 14 is an explanatory diagram showing a scrambling method and identification information when dummy data added to the head of a block is 2 bits.

FIG. 15 shows a convolution scheme of 1, 2, 4, and 8 bits, and 2
The characteristic comparison figure of the conversion by 55 types of Galois field multiplication methods.

FIG. 16 is a characteristic comparison diagram of conversion between a Galois field addition method using dummy data of 1, 2, 4, and 8 bits and a 255-type Galois field multiplication method.

FIG. 17 is a characteristic comparison diagram of conversion by a 4-bit convolution method, a Galois field addition method using 4-bit dummy data, and 255 types of Galois field multiplication methods.

FIG. 18 shows an RS code, Galois field addition (one-position multiplexing in a block) type on GF (2 ⁸ ), convolution processing (1, 2, 2,
4 is a characteristic diagram showing each symbol error rate (4, 8 bits).

[Explanation of symbols]

 10 Modulation circuit input terminal 40 Modulation circuit output terminal 50 Demodulation circuit input terminal 60 Demodulation circuit output terminal

Claims (38)

[Claims] 1. A digital modulation circuit for modulating a data sequence, comprising: a multiplexer for multiplexing predetermined data as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block; Encoder that generates a first Reed-Solomon code by performing Reed-Solomon encoding by using the encoded block as an information part, and data indicating a mutually different scrambling method at a position corresponding to the dummy data, and the first Reed-Solomon code An adder for adding a plurality of Reed-Solomon codes for scrambling having the same code length to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes; Of the DC components with the smallest DC component
A setting device for setting a Reed-Solomon code for output. 2. A digital modulation circuit for modulating a data sequence, comprising: a multiplexer for multiplexing predetermined data as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block; An RS encoder that generates a first Reed-Solomon code by performing Reed-Solomon coding by using a converted block as an information portion, a memory that stores the first Reed-Solomon code, and data indicating a different scrambling method corresponding to the dummy data. A plurality of second Reed-Solomon codes for generating a plurality of second Reed-Solomon codes by adding a plurality of Reed-Solomon codes for scrambling having a position and having the same code length as the first Reed-Solomon code to the first Reed-Solomon code, respectively. 1 adder, and a second adder having a minimum DC component among the plurality of second Reed-Solomon codes.
A selector for selecting a scrambling Reed-Solomon code to give a Reed-Solomon code, and a second addition for adding the scrambling Reed-Solomon code selected by the selector to the first Reed-Solomon code read from the memory and outputting the result. And a digital modulation circuit comprising: 3. A digital modulation circuit for modulating a data sequence, comprising: a multiplexer for multiplexing predetermined data as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block; Encoder that generates a first Reed-Solomon code by performing Reed-Solomon coding by using the coded block as an information part, and data indicating a mutually different scrambling method at a position corresponding to the dummy data, and the first Reed-Solomon code An adder for adding a plurality of Reed-Solomon codes for scrambling having the same code length to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes; And a second Reed-Solomon having a minimum DC component among the plurality of second Reed-Solomon codes. A digital modulation circuit, comprising: a selector for selecting a code; and a reader for reading out and outputting the second Reed-Solomon code selected by the selector from the memory. 4. The method according to claim 1, wherein
A digital modulation circuit, wherein the adder or the first adder has a ROM that outputs a pattern for a parity part determined according to a pattern of an information part in a Reed-Solomon code for scrambling. 5. The method according to claim 1, wherein
A digital modulation circuit, wherein the predetermined data and the data indicating the scrambling method are each 8-bit data. 6. The method according to claim 1, wherein:
A digital modulation circuit, wherein a predetermined position in a block to which the dummy data is multiplexed is a head position of the block. 7. The method according to claim 1, wherein
The multiplexer multiplexes two sets of bit data constituting the predetermined data at predetermined two positions in each block in a data sequence, and the plurality of scrambling Reed-Solomon codes are different from each other. A digital modulation circuit having two sets of bit data constituting data indicating a method at positions corresponding to the two positions of dummy data. 8. The Reed-Solomon according to claim 7, wherein the predetermined two positions in the block to which the dummy data are multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. A digital modulation circuit which is a position in the block corresponding to the head of the latter half of the code length of the code. 9. The method according to claim 1, wherein
The multiplexer multiplexes four sets of bit data constituting the predetermined data at predetermined four positions in each block in a data sequence, and the plurality of scrambling Reed-Solomon codes are different from each other. A digital modulation circuit having four sets of bit data constituting data indicating a method at positions corresponding to the four positions of dummy data. 10. The Reed-Solomon according to claim 9, wherein the predetermined four positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. 1/4 half of the code length of the code,
A digital modulation circuit which is each position in the block corresponding to each head of 2/4 half and 3/4 half. 11. The multiplexer according to claim 1, wherein the multiplexer converts eight sets of bit data constituting the predetermined data into predetermined eight bits in each block in a data sequence.
A plurality of Reed-Solomon codes for scrambling, wherein each of the plurality of Reed-Solomon codes for scrambling has eight sets of bit data constituting data indicating a mutually different scrambling method at positions corresponding to the eight positions of dummy data. circuit. 12. The Reed-Solomon according to claim 11, wherein the predetermined eight positions in the block to which the dummy data are multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. Code length of code 1/8 half, 2/8 half, 3/8 half, 4/8 half, 5/8 half, 6/8 half, 7/8 half A digital modulation circuit at each position in the block. 13. The method according to claim 1, wherein said t is 4, and said multiplexer is a Galois field GF.
The predetermined element of (2 ⁴ ) is the head of each block in the data sequence and the information length of a Reed-Solomon code whose data part is obtained by adding two elements of the Galois field GF (2 ⁴ ) to one block. Each is multiplexed at a position in a block corresponding to the head of the second half of the code length to generate a multiplexed block, and the adder or the first adder is different from the Galois field GF (2 ⁴ )
GF (2)
⁴ ) has an element at the beginning of the latter half of the code length, and
A digital modulation circuit for adding a plurality of Reed-Solomon codes for scrambling having the same code length as the Reed-Solomon code to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes. 14. The method according to claim 1, wherein said t is 2, and said multiplexer is a Galois field GF.
The predetermined element of (2 ² ) is defined as the head of each block in the data sequence and the Reed-Solomon code whose information part is a data length obtained by adding four elements of Galois field GF (2 ² ) to one block as an information part. The code length is multiplexed at each position in the block corresponding to the first half of the 1/4 half, the 2/4 half and the 3/4 half to generate a multiplexed block, and the adder or the first The adder is
Galois fields GF (2 ² ) different from each other at the beginning and Galois fields GF (2 ² ) different from each other at the beginning of the quarter of the code length and Galois fields different from each other GF
The element of (2 ² ) is at the head of the code length 2/4 half, and the elements of the Galois field GF (2 ² ) different from each other are the code length 3
A plurality of second Reed-Solomon codes are added to the first Reed-Solomon code, each having a code length equal to that of the first Reed-Solomon code at the beginning of the quarter and being equal to the first Reed-Solomon code. A digital modulation circuit that generates a code. 15. In a digital modulation method for modulating a data sequence, a predetermined data is multiplexed as dummy data at a predetermined position in each block in the data sequence to generate a multiplexed block, and the multiplexed block is generated. A first Reed-Solomon code is generated by performing Reed-Solomon coding as an information part, and a plurality of pieces of data indicating mutually different scrambling methods are provided at positions corresponding to the dummy data and have the same code length as the first Reed-Solomon code. Are added to the first Reed-Solomon code, respectively, to generate a plurality of second Reed-Solomon codes, and a second DC code component having the smallest DC component among the plurality of second Reed-Solomon codes is generated. 2. A digital modulation method for setting a Reed-Solomon code for output. 16. The digital modulation method according to claim 15, wherein the predetermined data and the data indicating the scrambling method are each 8-bit data. 17. The digital modulation method according to claim 15, wherein the predetermined position in the block to which the dummy data is multiplexed is a head position of the block. 18. A digital modulation method for modulating a data sequence, wherein two sets of bit data constituting predetermined data are multiplexed and multiplexed as dummy data at two predetermined positions in each block in the data sequence. Generating a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, and converting two sets of bit data constituting data indicating mutually different scrambling methods into dummy data at the two positions. And a plurality of scrambling Reed-Solomon codes each having a code length equal to the first Reed-Solomon code,
Digital modulation for adding to the Reed-Solomon code to generate a plurality of second Reed-Solomon codes and setting, for output, a second Reed-Solomon code having a minimum DC component among the plurality of second Reed-Solomon codes; Method. 19. The Reed-Solomon according to claim 18, wherein the predetermined two positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. A digital modulation method that is a position in the block corresponding to the head of the latter half of the code length of the code. 20. In a digital modulation method for modulating a data sequence, four sets of bit data constituting predetermined data are multiplexed and multiplexed as dummy data at predetermined four positions in each block in the data sequence. Generating a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, and converting four sets of bit data constituting data indicating mutually different scrambling methods into dummy data at the four positions. And a plurality of scrambling Reed-Solomon codes each having a code length equal to the first Reed-Solomon code,
Digital modulation for adding to the Reed-Solomon code to generate a plurality of second Reed-Solomon codes and setting, for output, a second Reed-Solomon code having a minimum DC component among the plurality of second Reed-Solomon codes; Method. 21. The Reed-Solomon according to claim 20, wherein the predetermined four positions in the block to which the dummy data is multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. A digital modulation method, which is each position in the block corresponding to each head of the code length of 1/4 half, 2/4 half, and 3/4 half. 22. In a digital modulation method for modulating a data sequence, eight sets of bit data constituting predetermined data are multiplexed and multiplexed as dummy data at predetermined eight positions in each block in the data sequence. Generating a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, and converting eight sets of bit data constituting data indicating mutually different scrambling methods into dummy data at the eight positions. And a plurality of scrambling Reed-Solomon codes each having a code length equal to the first Reed-Solomon code,
Digital modulation for adding to the Reed-Solomon code to generate a plurality of second Reed-Solomon codes and setting, for output, a second Reed-Solomon code having a minimum DC component among the plurality of second Reed-Solomon codes; Method. 23. The Reed-Solomon according to claim 22, wherein the predetermined eight positions in the block to which the dummy data are multiplexed include a head position of the block and a data length after the dummy data multiplexing as an information part. Code length of code 1/8 half, 2/8 half, 3/8 half, 4/8 half, 5/8 half, 6/8 half, 7/8 half A digital modulation circuit at each position in the block. 24. In a digital modulation method for modulating a data sequence, a predetermined element of a Galois field GF (2 ⁴ ) is used as a head of each block in the data sequence and one block of the Galois field GF (2 ⁴ ). Are respectively multiplexed at positions in a block corresponding to the head of the latter half of the code length of the Reed-Solomon code having the data length obtained by adding two elements to the multiplexed block to generate a multiplexed block. As an information part to generate a first Reed-Solomon code,
It has an element of a different Galois field GF (2 ⁴ ) at the beginning and an element of a different Galois field GF (2 ⁴ ) at the beginning of the latter half of the code length, and is different from the first Reed-Solomon code. Adding a plurality of Reed-Solomon codes for scrambling having the same length to the first Reed-Solomon code,
A plurality of second Reed-Solomon codes are generated, and a second DC signal having a minimum DC component among the plurality of second Reed-Solomon codes is generated.
A digital modulation method that sets a Reed-Solomon code for output. 25. In a digital modulation method for modulating a data sequence, a predetermined element of a Galois field GF (2 ² ) is used as a head of each block in the data sequence and one block as a Galois field GF (2 ² ). Of a Reed-Solomon code having a data length obtained by adding four elements of
Each multiplex is multiplexed at each position in a block corresponding to the beginning of each of the quarters and the quarters to generate a multiplexed block, and the multiplexed block is subjected to Reed-Solomon encoding as an information part to perform first Reed-Solomon encoding. A code is generated, and an element of a mutually different Galois field GF (2 ² ) is at the head and an element of a mutually different Galois field GF (2 ² ) is at the beginning of the code length 符号. An element of a mutually different Galois field GF (2 ² ) is provided at the beginning of the code length 2/4 half, and an element of a mutually different Galois field GF (2 ² ) is provided at the beginning of the code length 3/4 half. And adding a plurality of scrambling Reed-Solomon codes each having a code length equal to the first Reed-Solomon code to the first Reed-Solomon code to generate a plurality of second Reed-Solomon codes, Directly among a plurality of second Reed-Solomon codes Component is configured for outputting the minimum of the second Reed-Solomon codes, digital modulation methods. 26. A digital demodulation circuit for demodulating a data sequence of a Reed-Solomon code, comprising: an RS decoder for error-correcting the Reed-Solomon code using a parity unit;
A detector for detecting a scrambling Reed-Solomon code used for conversion to the Reed-Solomon code based on data indicating a scrambling method of a predetermined position of the Reed-Solomon code output from the RS decoder;
A digital demodulation circuit comprising: an adder for adding a Reed-Solomon code for scrambling detected by the detector to a Reed-Solomon code output from a decoder and outputting the result. 27. The digital demodulation circuit according to claim 26, wherein the predetermined position is one of a predetermined one position, a predetermined two positions, a predetermined four positions, and a predetermined eight positions. 28. A digital demodulation method for demodulating a data sequence of a Reed-Solomon code, wherein the error correction of the Reed-Solomon code using a parity unit and a scrambling method of a predetermined position of the error-corrected Reed-Solomon code are shown. Detecting the scrambling Reed-Solomon code used for conversion to the Reed-Solomon code based on the data, adding the detected scrambled Reed-Solomon code to the error-corrected Reed-Solomon code, and outputting the result. Digital demodulation method. 29. The digital demodulation method according to claim 28, wherein the predetermined position is one of a predetermined one position, a predetermined two positions, a predetermined four positions, and a predetermined eight positions. 30. A digital modulator for inputting a data stream and converting it into a bit stream, wherein a predetermined data element is multiplexed as dummy data at a predetermined position in a block sequentially cut out from the data stream to form a multiplexed block. A generating unit, an RS encoder that generates a first Reed-Solomon code by performing Reed-Solomon encoding by using the multiplexed block as an information unit, and an information unit that has identification information indicating a scrambling method at the same position as the dummy data, and An adder for adding a plurality of types of scrambling Reed-Solomon codes each having a code length of a parity part equal to the first Reed-Solomon code to the first Reed-Solomon code to generate a plurality of types of second Reed-Solomon codes; Among the plurality of types of second Reed-Solomon codes, A selector for selecting and outputting a Reed-Solomon code. 31. The method according to claim 30, wherein the selector comprises:
A digital modulator that selects and outputs a second Reed-Solomon code having a minimum DC component after modulation in a bit stream. 32. The apparatus according to claim 30, wherein the adder comprises:
A digital modulator having a memory for outputting a pattern for a parity part determined according to a pattern of an information part in a Reed-Solomon code for scrambling. 33. The memory of claim 32, wherein the memory is
Digital modulator, which is OM. 34. The multiplexer according to claim 30, wherein:
The first half and the second half of the predetermined data element are multiplexed as dummy data at predetermined two positions in the block, and the plurality of types of scrambling Reed-Solomon codes are the first half of the data element constituting the identification information. The second half is 2
A digital modulator having the same position as the dummy data of the position. 35. A digital modulation method for inputting a data stream and converting it into a bit stream, wherein a predetermined data element is multiplexed as dummy data at a predetermined position in a block sequentially cut out from the data stream to form a multiplexed block. And generating a first Reed-Solomon code by performing Reed-Solomon encoding using the multiplexed block as an information part, having identification information indicating a scrambling method at a position corresponding to the dummy data, and generating a first Reed-Solomon code. Adding a plurality of types of scrambling Reed-Solomon codes having the same code length to the first Reed-Solomon code to generate a plurality of types of second Reed-Solomon codes;
A digital modulation method for selecting and outputting a second Reed-Solomon code having desired characteristics from the plurality of types of second Reed-Solomon codes. 36. The digital modulation method according to claim 35, wherein the desired characteristic used for selecting the second Reed-Solomon code is a characteristic in which a DC component after modulating a bit stream is a minimum. 37. A digital demodulator for demodulating a Reed-Solomon code cut out from a bit stream and decoded, comprising: an RS decoder for error-correcting the Reed-Solomon code; and a Reed-Solomon code output from the RS decoder. A detector that detects the Reed-Solomon code for scrambling used for conversion to the Reed-Solomon code based on the identification information of the predetermined position, and a Reed-Solomon code output from the RS decoder. A digital demodulator having an adder for adding and outputting a scrambling Reed-Solomon code. 38. A digital demodulation method for demodulating a Reed-Solomon code cut out from a bit stream and decoded, based on the identification information of a predetermined position of the Reed-Solomon code after error correction. Digital demodulation for detecting the Reed-Solomon code for scrambling used for the conversion to the Reed-Solomon code, adding the detected Reed-Solomon code for error correction to the Reed-Solomon code after error correction, and demodulating the original data. Method.