JPH08204573A - Code conversion method - Google Patents

Abstract

PURPOSE: To improve the conversion rate and the error detection capability by simultaneous execution of encoding for shift error detection and encoding to a run length limit code. CONSTITUTION: Input data is converted into an error correction code by an ECC encoder 1, and this code is converted into a shift error control RLL by a shift error control RLL encoder 2 based on a conversion table. This RLL is precoded by a precoder 3 and is recorded in a recording system. The code read out from the recording system 4 passes an equalization detector 5 and is converted into the original error correction code by a shift error control RLL decoder 6. In this case, one-bit shift error extended to two code words is corrected by the decoder 6; and in the case of one-bit shift error in one code word, a pointer is set to the bit where there is the probability of error, and it is sent to an ECC decoder 7, and the pointer is referred to perform the error correction processing, and reproduced data is outputted. Thus, one-bit shift error in one block is detected, and the correction code of one-bit shift error extended to two blocks is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for encoding digital data, and is a code conversion method for generating a code having an error control function corresponding to a shift error while satisfying a run length limit. It is about.

[0002]

2. Description of the Related Art It has been well practiced to use a run-length limited code when encoding digital data, especially when recording digital data. By limiting the number of consecutive bits of the same binary value by using the run-length limited code, the self-synchronization for reading the information signal can be easily extracted from the reproduction signal, and the signal transmission band can be narrowed. is there. The run-length limited code in which the minimum distance between the codewords is 1 has neither error correction ability nor error detection ability, but to compensate for it, run-length limited code including various error correction ability is proposed. ing. IEEE Transactions on Magnetics, Vo
H.M.Hilden, "Shift Error Correcting Modul", H.M.Hilden, "Shift Error Correcting Modul"
ation Codes "), an error correction code corresponding to a shift error having a high error occurrence rate at the time of disc recording is described. In the shift error correction code, for example, 2
-19 sequences of run lengths are obtained for -7 modulated code data, 7 parity blocks corresponding to the sequence are added, and up to 2 shift errors can be corrected by parity check. There is.

[0003]

As described above, the most prominent error when digitally recording on a disk or magnetic tape for encoding digital data is a shift error caused by the influence of signal interference and jitter. Including the run length limited shift error correction code in the prior art,
Generally, the run-length limited error correction code has insufficient conversion rate and error correction capability. Therefore, an object of the present invention is to generate a run-length limited code with high efficiency and high error processing capability. Since the code error including the shift error increases as the recording density becomes higher, it is necessary to improve the error correction capability for higher density.

[0004]

In order to solve the above problems, the present invention has a structure in which a code word satisfying the following conditions is associated with each information word. (1) Each codeword satisfies the minimum run length restriction d including the concatenated part of the codeword. (2) Each codeword has a predetermined minimum shift distance p. However, it includes the case where the code words concatenated by a predetermined number have the above-mentioned minimum shift distance p. (3) There is no set of codewords forming a codeword string that appears when a shift within (p-1) bits across two codewords occurs.

[0005]

By generating codewords based on the above conditions, the runlength of a series of codeword strings is limited, and a predetermined minimum shift distance p is provided for each codeword or for each predetermined number of codewords. Therefore, it is possible to detect a codeword string generated by shifting within one codeword or up to (p-1) bits for each predetermined number of codewords as a codeword string including an error. Further, when a shift error within (p-1) bits that spans two concatenated code words occurs, it can be uniquely corrected.

[0006]

First Embodiment A method for converting a 4-bit information word into an 8-bit code word will be described below as a first embodiment of the present invention. In this embodiment, the minimum run length limit d
Is 1, the minimum shift distance p (the minimum value of the number of shifts of code 1 required for one codeword to become another codeword with the same weight)
Is 2.

In order to satisfy the minimum run length limit of 1 even in the concatenated part of code words, the last bit or the head bit of each code word is always 0. In this embodiment, the last bit of each codeword is always 0. At this time, since the last bit of the 8-bit code word is fixed to 0, the undecided part of the code word is a 7-bit code string.

Out of 128 7-bit code strings, 34 code strings satisfy the minimum run length restriction 1 in the code string. In general, when the minimum run length limit is 1, and the number of those satisfying the minimum run length limit 1 in an n-bit codeword is An, An is (n-1)
Since it is the sum of the bit code word with 0 added and the (n-2) bit code word with 01 added, the following equation is established.

An = An-1 + An-2 When the code length is 1, the codeword is 0, 1, so A1 = 2,
When the code length is 2, the codewords are 00, 01 and 10, so that A2 = 3, and the value of An and the code group are recursively obtained.

Next, 34 7-bit code words obtained above are divided into two groups so that the minimum shift distance becomes 2 for each weight (the number of 1's included in the code word). Like

[0011]

[Table 1]

It should be noted that an 8-bit code word obtained by adding 0 to a 7-bit code word is used. As a result, all the code groups formed by selecting one of the code groups for each weight in Table 1 have the minimum shift distance 2. The code group selection method for each weight is determined in consideration of the following conditions.

When a code group having a minimum shift distance of 2 is formed, a code string when a 1-bit shift occurs in a certain code word in the code group does not exist in the code group. The code string can be detected as containing an error. Therefore, next, it is considered to deal with the case where a 1-bit shift occurs across two codes.

When a 1-bit shift extending between two codes occurs, what was 0 in the first bit or last bit of each code word can be 1, and what was 1 can be 0. Therefore, if the first bit or the last bit of each code word is inverted (the first bit 0 is not 1 in this embodiment) does not exist as a code word, it is possible to correct a shift error extending between two codes. Become. The code group for each weight in Table 1 is selected in consideration of the above conditions. If a codeword of the A group having a weight of 1 (hereinafter expressed as 1-A) is selected, it is inevitably 2
-B is selected. Because 1-A 00000010
If the leading bit of the sign is inverted, 1000 of 2-A
This is because the code is 0010. Similarly, 3-A is selected. For selecting 1-B, 2-A, 3
With B. 0-A belongs to the latter group, and 4-
A also belongs to the latter group. As a result, as shown in (Table 2), it is divided into two groups, and the optimum 16 code words are determined in consideration of the fact that the maximum run length k becomes the minimum.

[0015]

[Table 2]

Therefore, in code group 1, 0000
If 16 code words are used as they are in code group 2 except for 0000 and 01000000, the maximum run length of code group 1 is 10 and the maximum run length of code group 2 is 13. Therefore, if the 16 codewords of the code group 1 excluding the codewords are associated with the respective information words, the optimum code group in this embodiment is obtained. (Table 3) shows these code groups.

[0017]

[Table 3]

Next, an example of an implementation method of this embodiment and an error control method will be described with reference to FIG. In FIG. 1, 1 is an ECC (error correction code) encoder, 2 is a shift error control RLL (run length limited) encoder, 3 is a precoder, 4 is a recording system such as a disk, 5 is an equalization detector, 6
Is a shift error control RLL decoder, and 7 is an ECC decoder. The input data is converted into an error correction code by the ECC encoder 1 such as Reed-Solomon code, and converted into a shift error control RLL code by the shift error control RLL encoder 2 based on the conversion table generated in the above-mentioned procedure.
It is precoded by the precoder 3 and then recorded in the recording system 4. The code read from the recording system 4 is
After passing through the equalization detector 5, it is converted into the original error correction code by the shift error control RLL decoder 6. At this time, the shift error control RLL decoder 6 corrects a 1-bit shift error that extends over two codewords. Further, with respect to a 1-bit shift error in one code word, it is detected, a pointer is arranged at a bit having an error possibility, and the pointer is also sent to the ECC decoder 7. The ECC decoder 7 performs error correction processing while referring to the pointer, and outputs reproduced data.

According to the present embodiment, while satisfying the same predetermined minimum run length limit as in the prior art, a 1-bit shift error is detected in one block, and a code for correcting a 1-bit shift error in two blocks is generated. There is.
Although the 4/8 conversion is described in the present embodiment, this is also possible at the conversion rates of 8/14 and 20/31. In general, at the conversion rate m / n (n-
1) 2m + number of code words with minimum run length of 1
If it is larger than 1, this embodiment can be executed.

(Embodiment 2) A method of converting a 4-bit information word into a 7-bit code word in the second embodiment of the present invention will be described below. Also in this embodiment, the minimum run length limit d is 1 and the minimum shift distance p is 2.

Those which satisfy the minimum run length restriction 1 in the 7-bit code word are as described in the first embodiment.
There are a plurality of them, and those are grouped so as to have the minimum shift distance of 2 for each code weight. In order to correct a 1-bit shift error that also extends over two codewords, a code in which the first bit or the last bit of the codeword is inverted does not exist in the same codeword group (Table 1).
If a code group is selected for each code weight from the last bit of all code words except 0, (0-A, 1
-B, 2-A, 3-B, 4-A) and (1-A, 2-B,
3-A). The former is referred to as code group 1 and the latter is referred to as code group 2, which are shown in (Table 4).

[0022]

[Table 4]

Code groups 1 through 0000000 and 10
When 16 except for 00001 are selected, there are 5 codewords that end with 1 and 5 codewords that start with 1, so that there are a total of 25 concatenations of codewords that do not satisfy the run length restriction. In that case, the preceding code word and the current code word are replaced with the code word of code group 2 as the sub-conversion table. In two codewords concatenated as a codeword selection condition from code group 2, the first bit of the preceding codeword is 0 and the last bit of the current codeword is 0. Needed to meet. An example of the sub-conversion table of the preceding code word and the current code word is shown in (Table 5).

[0024]

[Table 5]

Although the same code word exists in the preceding code word and the current code word, it is possible to distinguish between the code word before and after the code word string of two consecutive code words. 0101001 to 000
Even if it is replaced with 0000, it is possible, but the maximum run length becomes infinite, which is inappropriate. The maximum run length when using the main conversion table and the sub conversion table is 16.

Next, consider the case where the code word of the main conversion table is composed of the code group 2. 16 of code groups 2
7 codewords ending with 1,
Since there are seven code words starting with 1, these are replaced with the code of code group 1. Since there are eight codewords that start with 0 and end with 0 in code group 1, if the preceding codeword and the current codeword are replaced with seven codewords excluding, for example, 0000010 (Table 6), Good.

[0027]

[Table 6]

Since the maximum run length is 12 when the main conversion table and the sub conversion table are used, it is better to select the code word of the main conversion table from the code group 2 in this case.

When the error control capability of this embodiment is obtained, every two codewords have the minimum shift distance of 2.
Since two consecutive codewords converted by the sub-conversion table may be the same codeword, when the codeword of the main conversion table is selected from the code group 2, for example, the codeword string 00001000100000000.
If 0100 occurs, there is a possibility of 1-bit shift error in any codeword. Therefore, this embodiment has the ability to detect a 1-bit shift error in 3 code words, that is, 21 bits.

Next, an example of a method of implementing this embodiment will be described with reference to FIGS. FIG. 2 constitutes the shift error control RLL encoder 2 in FIG. 1, and 8 and 9 are codeword generation circuits based on the main conversion table and the sub conversion table, respectively.
Reference numeral 10 denotes a holding circuit, which holds the value of the last bit of the current codeword, and the determination circuit 13 determines whether or not 1 continues in the concatenation part with the next codeword. Reference numerals 11 and 12 are delay circuits, and the codewords generated by the codeword generation circuits 8 and 9 are sent to the codeword determination circuit 14 at the same time as the determination result of the determination circuit 13 and the determined codewords are output. .

FIG. 3 shows the shift error control RL in FIG.
The L code decoder 6 is configured, the input codeword is decoded by the decoding circuit 15 based on both the main conversion table and the sub conversion table, and the decoded code word corresponds to the preceding code word of the sub conversion table. It is determined by the determination circuit 16 whether or not it is the one, and the determination result is sent to the decoding circuit 15 to discriminate between the preceding code word and the subsequent code word when the code words for the sub-conversion table are continuous. Reference numeral 17 denotes a delay circuit, which determines the preceding codeword and the current codeword at the same time.
The error detection flag setting is determined by sending the result to and output with the decoding result.

This embodiment has the effect of generating a code that detects a 1-bit shift error in 3 blocks and corrects a 1-bit shift error in 2 blocks while satisfying the same predetermined minimum run length limit as in the prior art. is there. Although the present embodiment has described the 4/7 conversion, this is also possible at conversion rates of 8/13 and 20/30. That is, the conventional 1-7 modulation is 2/3 conversion,
It means that if it is expanded to 20/30 conversion, error detection capability can be added with the same conversion rate and the same minimum run length. In general, n at a conversion rate m / n
If the number of code words having a minimum run length of 1 is larger than 2m + 1, this embodiment can be executed.

[0033]

INDUSTRIAL APPLICABILITY The present invention relates to a highly efficient code generation method for simultaneously performing shift error detection coding and run length limited coding in a digital code conversion method, and improves a conversion rate and an error detection capability. I showed what I aimed for. According to the present invention even when the minimum run is 2,
It is possible to detect a shift error of 1 bit per 18 bits at a conversion rate of 8/18, which is a significant improvement over the conventional one.
Such a shift error has a very high error occurrence rate especially in the disc recording system, and by adding the ability to detect the shift error to the code conversion process, the error correction process performed separately from the code conversion process can be performed. This has the effect of improving the error correction capability and increasing the density of digital recording.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration for realizing a first embodiment.

FIG. 2 is a block diagram showing a circuit configuration of an encoding unit according to a second embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a decoding unit in the second embodiment.

Claims (3)

[Claims] 1. A m / n code conversion method for converting m bits of information words into n bits of code words, wherein a sequence of the code words satisfies a predetermined run length restriction including a concatenation portion of the code words, and the code A codeword string having a predetermined minimum shift distance p for each word or for each of a predetermined number of the codewords and generated by bit shifting within (p-1) bits across the two concatenated codewords is the codeword A code conversion method characterized by not existing as a sequence of. 2. A minimum run length limit d in each codeword.
2. The code conversion method according to claim 1, wherein the bit satisfying the above condition and the bit at any specified position of the d bits from the beginning and the end of each code word is 0. 3. A code word satisfying the minimum run length restriction d is selected from all code words having a code length n, code words satisfying the minimum run length restriction d are divided into two groups having a shift distance p from each other, and A main conversion table that determines a code word corresponding to an information word is selected from one of the two groups, and the minimum run length restriction d is not satisfied at the concatenation part of the code words converted by the main conversion table. If the preceding information word and the current information word corresponding to the concatenated code word sequence are
Sub-conversion in which the code word having the leading bit of 0 is made to correspond to the preceding information word and the code word having the last bit of 0 is made to correspond to the current information word from the other one of the groups A concatenated two using a table and generated by the main conversion table or the sub conversion table
2. The two codeword strings generated by the bit shift within (p−1) bits across one codeword string do not exist as codewords generated by one of the conversion tables. Code conversion method.