JP2000149457A - Modulation device and method therefor, demodulation device and method therefor, and distribution medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable recording and reproducing with a high line density to be performed. SOLUTION: A DSV control bit decision/insertion section 11 inserts a DSV control bit for DSV control into an inputted data train, and outputs it to a modulation section 12. A modulation section 12 converts data of which basic data length is 2 bits to a variable length code of which basic code length is 3 bits, and outputs it to a NRZI 13. A conversion table provided in the modulation section 12 has a replacing code for limiting continuity of the minimum run to a prescribed number of times or less and a replacing code for protecting run length limit, replacement limit is added to the replacing code, further the table has conversion regulations in which both of the surplus when the number of pieces of '1' in an element of a data train is divided by 2 and the surplus when the number of pieces of '1' in an element of a code word train is divided by 2 are coincident with '1' or '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation device and method, a demodulation device and method, and a providing medium, and more particularly to a recording medium for recording data on a recording medium at a high density or recording data at a high density. TECHNICAL FIELD The present invention relates to a modulation device and a method, a demodulation device and a method, and a providing medium that are suitable for use when reproducing from a device.

[0002]

2. Description of the Related Art When data is transmitted to a predetermined transmission path or recorded on a recording medium such as a magnetic disk, an optical disk or a magneto-optical disk, the data is modulated so as to be suitable for the transmission path or the recording medium. Done. A block code is known as one of such modulation methods. The block code divides a data string into units of m × i bits (hereinafter referred to as data words) and converts the data words into code words of n × i bits according to an appropriate coding rule. This code is a fixed-length code when i = 1, and when a plurality of i can be selected, that is, when a predetermined i in a range of 1 to imax (maximum i) is selected and converted, the variable-length code is used. Become. This block-coded code is a variable-length code (d, k; m, n;
r).

Here, i is called a constraint length, and imax is r
(Maximum constraint length). The minimum run d indicates the minimum number of consecutive “0” s between consecutive “1” s in the code sequence, and the maximum run k is the maximum number of “0” s between consecutive “1s” in the code sequence. This shows the maximum number of continuous frames.

When the variable length code obtained as described above is recorded on an optical disk or a magneto-optical disk, for example, a compact disk (CD) or a mini disk (MD) (trademark), the variable length code obtained as described above is obtained. NRZI (NonReturn t) which inverts the variable length code with "1" and does not invert with "0"
o Zero Inverted) modulation is performed, and an NRZI-modulated variable-length code (hereinafter, referred to as a recording waveform sequence) is recorded. This is also called mark edge recording. On the contrary,
On a magneto-optical disk or the like having a capacity of 3.5 inches and 230 MB according to the ISO standard, a code string subjected to recording modulation is recorded as it is without NRZI modulation. This is called mark position recording.
In a recording medium having a high recording density as at present, mark edge recording is often used.

The minimum inversion interval of the recording waveform sequence is Tmin,
When the maximum inversion interval is Tmax, in order to perform high-density recording in the linear velocity direction, it is better that the minimum inversion interval Tmin is long, in other words, it is better that the minimum run d is large. From the viewpoint of clock reproduction, it is better that the maximum inversion interval Tmax is shorter, in other words, the smaller the maximum run k is, the better. When considering the overwrite characteristics, it is desirable that Tmax / Tmin is small. Further, from the viewpoint of jitter and S / N, it is important that the detection window width Tw = m / n is large, and various modulation methods have been proposed and put into practical use in consideration of the conditions of the medium (recording medium). ing.

[0006] Here, specifically, for optical disks, magnetic disks, magneto-optical disks and the like,
Alternatively, the modulation scheme actually used will be described. EFM (Eight to Fourteen M) used for CD and MD
odulation) code (also written as (2,10; 8,17; 1)), DVD
8-16 code used in (Digital Video Disc) ((2,10;
1,2; 1)) or PD (Phase Change Opt
RLL (Run Len) used in ical Disk; 120mm, 650MB capacity
gth Limited code) (2,7) (Also written as (2,7; m, n; r))
Is an RLL code with a minimum run d = 2.

Also, a 3.5 inch MO (Magneto Opt.
RLL (1,7) (also referred to as (1,7; 2,3; r)) used in the RL; is the RLL code of the minimum run d = 1, and also has the recording density In a recording / reproducing disk device such as an optical disk or a magneto-optical disk having a high performance, an RLL code having a minimum run d = 1 is used, which balances the size of the minimum mark and the conversion efficiency.

The conversion table of the variable length RLL (1-7) code is, for example, the following table.

Here, the symbol x in the conversion table is set to "1" when the following channel bit is "0",
It is set to "0" when the subsequent channel bit is "1" (the same applies hereinafter). The maximum constraint length r is 2.

The parameters of the variable length RLL (1,7) are (1,7; 2,3,
2), and assuming that the bit interval of the recording waveform sequence is T, (d
The minimum inversion interval Tmin represented by (+1) T is 2 (= 1 + 1) T. Assuming that the data string bit interval is Tdata, (m /
n) × 2, the minimum inversion interval Tmin is 1.33 (= (2/3)
× 2) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is 8 (= 7 + 1) T (= (m / n) × 8Tdata = (2/3) ×
8Tdata = 5.33Tdata). Further, the detection window width Tw is (m /
n) × Tdata, and its value is 0.67 (= 2/3) Tdata.

In the channel bit string modulated by RLL (1,7) in Table 1, the frequency of occurrence is T
The minimum is 2T, followed by 3T and 4T. 2
The fact that a large amount of edge information such as T or 3T is generated in an early cycle is often advantageous for clock reproduction.

[0012] However, when the linear recording density is further increased, short marks become a problem. That is, if 2T, which is the minimum run, continues to occur, the recording waveform is likely to be distorted. This is because the 2T waveform output is smaller than other waveform outputs, and is easily affected by, for example, defocus or tangential tilt. Also, at high recording density, the minimum mark (2
The continuous recording of T) is easily affected by disturbance such as noise. Therefore, such a pattern sequence is likely to cause an error during data reproduction. As a pattern of the data reproduction error in this case, the head and the end of the continuous minimum mark are often shifted and erroneous, so that the error propagation length becomes long.

On the other hand, when data is recorded on a recording medium or when data is transmitted, coded modulation suitable for the recording medium or transmission path is performed, and these modulation codes include low-frequency components. In such a case, for example, various error signals such as a tracking error in the servo control of the disk device tend to fluctuate or jitter tends to occur. Therefore, it is desirable for the modulation code to suppress low-frequency components as much as possible.

As a method of suppressing low frequency components, DSV (Digi
tal Sum Value) control. The DSV means that a channel bit sequence is converted into NRZI (level coding) to be a recording code sequence, and "1" of the bit sequence (data symbol) is changed to "+1", "
"0" is set to "-1", which means the sum when the codes are added. DSV is a measure of the low-frequency component of the recording code string, and reducing the absolute value of the positive / negative fluctuation of DSV, that is, performing DSV control, suppresses the low-frequency component except for the DC component of the recording code string. Will be.

The modulation codes based on the variable length RLL (1, 7) table shown in Table 1 are not subjected to DSV control. In such a case, the DSV control performs DSV calculation at a predetermined interval in a coded sequence (channel bit sequence) after modulation, and performs a predetermined DV calculation.
This is realized by inserting an SV control bit into a coded sequence (channel bit sequence).

However, since the DSV control bits are redundant bits, the number of DSV control bits should be as small as possible from the viewpoint of code conversion efficiency.
Depending on the V control bit, the minimum run d and the maximum run k
It is better not to change. This is because a change in (d, k) affects the recording / reproducing characteristics.

The applicant of the present invention has proposed, for example, in Japanese Patent Application No. 10-150280 filed earlier, that (d, k) = (1,7)
Table 2 shows a modulation method corresponding to a higher recording density.
1,7PP code is proposed. <Table 2> 1,7PP (1,7; 2,3; 4) Data code 11 * 0 * 10 001 01 010 0011 010 100 0010 010 000 0001 000 100 000011 000 100 100 000010 000 100 000 000001 010 100 100 000000 010 100 000 "110111 001 000 000 (next 010) 00001000 000 100 100 100 00000000 010 100 100 100 if xx1 then * 0 * = 000 xx0 then * 0 * = 101 ____________________________ Sync & Termination # 01 000 000 001 (12 channtl bits ) or # 01 001 000 000 001 000 000 001 (24 channel bits) # = 0 not terminate case # = 1 terminate case ___________________________Termination table 00 000 0000 010 100 "110111 001 000 000 (next010): When next channel bits are ' 010 ', convert '11 01 11' to '001 000 000' after using main table and termination table ._______________________

The conversion table shown in Table 2 has basic codes (codes from data strings (11) to (000000)) that cannot be converted without conversion codes, and conversion processing is possible without the conversion codes. But when it is,
Replacement codes (data strings (110111), (00001000), (0
00000000)) and a termination code (data string (00),
(0000) code).

Table 2 shows that the minimum run d = 1 and the maximum run k = 7, and the elements of the basic code include indeterminate codes (codes including *). The uncertain code is determined to be “0” or “1” so as to keep the minimum run d and the maximum run k irrespective of the immediately preceding and succeeding code word strings. That is, Table 2
In (2), when the 2-bit data string to be converted is (11), "000" or "101" is selected according to the codeword string immediately before it, and is converted into either of them. For example, if one channel bit of the immediately preceding codeword string is "
In the case of "1", the 2-bit data (11) is converted into a code word "000" in order to keep the minimum run d, and when one channel bit of the immediately preceding code word string is "0", the maximum is 1. It is converted into a code word "101" so that the run k is maintained.

The basic code of the conversion table in Table 2 has a variable length structure. That is, the basic code at the constraint length i = 1 is composed of three (* 0 *, 001, 010) less than the required number of four (2 ^ m = 2 ^ 2 = 4). As a result, when converting the data string, the constraint length i = 1
There will be data strings that cannot be converted by themselves.
After all, in Table 2, in order to convert all the data strings (to be satisfied as a conversion table), the constraint length i =
It is necessary to refer to up to three basic codes.

The conversion table of Table 2 shows that the minimum run d
Since the data string is (110111), the subsequent code word string is referred to, and when it is "010",
This data string is replaced with the code word “001 000 000”. Also, this data string is a 2-bit unit ((1
1), (01), and (11)), so that it is converted into a codeword “* 0 * 010 * 0 *”. As a result, in the code word string obtained by converting the data, the continuation of the minimum run is limited, and the minimum run repetition is performed up to six times.

Further, the conversion table in Table 2 has a maximum constraint length r = 4. A code with a constraint length i = 4 has a maximum run k =
7 is realized by a replacement code (maximum run compensation code). That is, the data (0000)
1000) is converted to a code word “000100100100”, and the data (00000000) is converted to a code word “0”.
10100100100 ". Also in this case, the minimum run d = 1 is maintained.

By the way, the conversion code of Table 2 is obtained by dividing the number of "1" in the element of the data string by 2 and the number of "1" in the element of the code word string to be converted by two. Have a conversion rule such that the remainder when divided by is either 1 or 0 and the same (any corresponding element has an odd or even number of “1” s). For example, the element (000001) of the data string in the conversion code is “010 10
It corresponds to the element of the code word string of 0 100 ", but the number of" 1 "of each element is 1 in the data string and 3 in the corresponding code word string, and both are divided by 2. The remainder of the time is equal to 1 (odd number). Similarly, the element (000000) of the data string in the conversion code is “01”.
0 100 000 "corresponds to the element of the code word string, but the number of" 1 "is 0 in the data string and 2 in the corresponding code word string. The remainder matches at 0 (even number).

Next, a method of performing DSV control will be described. The conversion table, such as the RLL (1,7) code in Table 1, has a DSV
As an example of the conventional DSV control method when control is not performed, after modulating a data sequence, at least (d + 1) bits of DSV control bits are added to a modulated channel bit sequence at predetermined intervals. It was done by

In the conversion table as shown in Table 2, DSV control can be efficiently performed by making use of the relationship between the data string and the code word string to be converted. That is, when the conversion table divides the number of “1” in the element of the data string and the number of “1” in the element of the code word string to be converted by 2 into 1 or 0, And have the same conversion rule in the channel bit string as above,
"1" for "inversion" or "for non-inversion"
Inserting a DSV control bit of "0" is equivalent to inserting a DSV control bit of (1) if "inverted" and (0) if "non-inverted" in a data bit string. Become.

For example, in Table 2, 3
When the bit continues with (001),
Assuming that the DSV control bit is interposed, the data is (00
1-x) (x is one bit, "0" or "1"). Here, if “0” is given to x, the conversion of the data sequence codeword sequence 0010 010 000 is performed in the conversion table of Table 2, and if “1” is given, the data sequence codeword sequence 0011 010 100 Conversion is performed. When the codeword string is NRZI-converted and level-encoded, these are data string codeword string level code string 0010 01000 001 1
111 0011 010 100 011
000, and the last three bits of the level code string are mutually inverted. This means that DSV control can be performed even in a data string by selecting (1) and (0) of the DSV control bit x.

Considering the redundancy by DSV control, performing DSV control with one bit in a data string means that, when expressed in a channel bit string, from the conversion rate (m / n = 2/3) in Table 2. This is equivalent to performing DSV control with 1.5 channel bits. On the other hand, in the RLL (1,7) table as shown in Table 1,
In order to perform DSV control, DSV
At this time, at least two channel bits are required to keep the minimum run.
As compared with the DSV control, the redundancy becomes larger. In other words, when having the table structure of Table 2, DSV control can be efficiently performed by performing DSV control within the data string.

In general, as the maximum constraint length r increases, the propagation of demodulation errors during bit shifting (errors caused by shifting the edge bit position by one bit forward or backward from the normal position). The characteristics deteriorate.

When Table 1 and Table 2 are compared, RLL (1,7) in Table 1 is obtained.
In the code, the maximum constraint length r is 2, whereas in Table 2,
In the case of the 7PP code, the maximum constraint length r is as large as 4, and the worst propagation length of the demodulation error propagation for the bit shift is 2 bytes in Table 1 but 3 bytes in Table 2. The 1,7PP code is a (d, k) = (1,7) code corresponding to a high recording density, and has a compact configuration, but still has a better error propagation characteristic than the conventional RLL (1,7) code. Was disadvantageous.

[0030]

As described above, when recording and reproducing an RLL code on a disk at a high linear density, a long error is likely to occur if there is a continuous pattern of the minimum run d. Further, in order to perform the DSV control in the (1,7; 2,3) code, it was necessary to sandwich redundant bits, but it was necessary to reduce the number of redundant bits as much as possible. Based on such a situation, as described above, the RLL code (d,
(k; m, n) = (1,7; 2,3), DSV control with efficient control bits while limiting the number of consecutive minimum runs and keeping the minimum and maximum runs Can be 1,7
Although the PP code was developed, the 1,7PP code had a longer error propagation characteristic than the conventional RLL (1,7) code, despite having a simple conversion table.

The present invention has been made in view of such a situation, and uses a table for limiting the number of times of occurrence of a conversion code that easily causes a long error propagation. By using a table that limits the number of occurrences, long error propagation is prevented from occurring.

[0032]

According to a first aspect of the present invention, there is provided a modulation apparatus comprising conversion means for converting input data into a code in accordance with a conversion table, wherein the conversion code in the conversion table is included in a data string element. The remainder obtained by dividing the number of “1” in “2” by 2 and the remainder obtained by dividing the number of “1” in the element of the codeword string to be converted by 2 are both equal to 1 or 0. Conversion rule, a first replacement code for limiting the continuation of the minimum run d to a predetermined number or less, a second replacement code for keeping the run length limit, a first replacement code, and a second replacement code. And the first replacement code or the second replacement code is subject to replacement restrictions.

According to a sixth aspect of the present invention, the modulation method includes a conversion step of converting input data into a code according to a conversion table, wherein the conversion code in the conversion table is the number of “1” in an element of the data string. And the remainder when dividing the number of “1” in the element of the code word string to be converted by 2 is equal to 1 or 0, A first replacement code for limiting the continuation of the run d to a predetermined number of times or less, a second replacement code for maintaining the run length limitation, and a basic code different from the first replacement code and the second replacement code. And the first replacement code or the second replacement code is characterized in that replacement restrictions are added.

According to a seventh aspect of the present invention, there is provided a providing medium for providing a program for executing a process including a conversion step of converting input data into a code according to a conversion table, wherein the conversion code of the conversion table is provided. Is the remainder when dividing the number of "1" in the element of the data string by 2;
The conversion rule that the remainder when dividing the number of "1" in the element of the code word string to be converted by 2 is equal to 1 or 0, and the continuation of the minimum run d is reduced to a predetermined number or less. A first replacement code to be restricted, a second replacement code to keep the run length restriction, a first replacement code, and a second replacement code.
And a base code different from the replacement code of
Or the second replacement code is characterized in that a replacement restriction is added.

The demodulating device according to the present invention comprises a conversion means for converting an input code into data in accordance with a conversion table, wherein the conversion code in the conversion table is the number of "1" in the element of the data string. And the remainder when dividing the number of “1” in the element of the code word string to be converted by 2 is equal to 1 or 0, A first replacement code for limiting the continuation of the run d to a predetermined number of times or less, a second replacement code for maintaining the run length limitation, and a basic code different from the first replacement code and the second replacement code. And the first replacement code or the second replacement code is characterized in that replacement restrictions are added.

A demodulation method according to a ninth aspect includes a conversion step of converting an input code into data according to a conversion table, wherein the conversion code in the conversion table is the number of “1” in the elements of the data string. And the remainder when dividing the number of “1” in the element of the code word string to be converted by 2 is equal to 1 or 0, A first replacement code for limiting the continuation of the run d to a predetermined number of times or less, a second replacement code for maintaining the run length limitation, and a basic code different from the first replacement code and the second replacement code. And the first replacement code or the second replacement code is characterized in that replacement restrictions are added.

According to a tenth aspect of the present invention, there is provided a providing medium for providing a program for executing a process including a conversion step of converting an input code into data according to a conversion table, wherein the conversion code of the conversion table is provided. Is the remainder when dividing the number of "1" in the element of the data string by 2 and the remainder when dividing the number of "1" in the element of the codeword string to be converted by 2 A conversion rule that matches with 1 or 0, a first replacement code for limiting the continuation of the minimum run d to a predetermined number or less, a second replacement code for keeping the run length limit, and a first replacement code A code and a base code different from the second replacement code,
The first replacement code or the second replacement code is characterized in that a replacement restriction is added.

In the modulation device according to the first aspect, the modulation method according to the sixth aspect, and the providing medium according to the seventh aspect, the input data is converted into a code according to a conversion table, and the conversion is performed. The conversion code of the table is the remainder when the number of “1” in the element of the data string is divided by 2,
The conversion rule that the remainder when dividing the number of "1" in the element of the code word string to be converted by 2 is equal to 1 or 0, and the continuation of the minimum run d is reduced to a predetermined number or less. A first replacement code to be restricted, a second replacement code to keep the run length restriction, a first replacement code, and a second replacement code.
And a base code different from the replacement code of
Or the second replacement code is subject to replacement restrictions.

In the demodulation device according to the eighth aspect, the demodulation method according to the ninth aspect, and the providing medium according to the tenth aspect, the input code is converted into data according to the conversion table, Is the remainder when dividing the number of “1” in the element of the data string by 2 and the remainder when dividing the number of “1” in the element of the codeword string to be transformed by 2. , A first replacement code for limiting the continuation of the minimum run d to a predetermined number of times or less, a second replacement code for keeping the run length limitation, The first replacement code and the second replacement code have different base codes, and the first replacement code or the second replacement code is subject to replacement restrictions.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

The modulation device according to the first aspect includes a conversion unit (for example, a modulation unit 12 in FIG. 1) that converts input data into a code according to a conversion table, and the conversion code in the conversion table is a data conversion code. The remainder when dividing the number of “1” in the element of the column by 2 and the remainder when dividing the number of “1” in the element of the codeword string to be converted are both 1 or 0. And a first replacement code that limits the continuation of the minimum run d to no more than a predetermined number of times.
A second replacement code for maintaining the run length restriction;
And a base code different from the second replacement code, and the first replacement code or the second replacement code
Is characterized by being subject to replacement restrictions.

The demodulation device according to the eighth aspect includes a conversion means (for example, the demodulation unit 53 in FIG. 6) for converting the input code into data in accordance with the conversion table, and the conversion code in the conversion table is The remainder when dividing the number of “1” in the element of the column by 2 and the remainder when dividing the number of “1” in the element of the codeword string to be converted are both 1 or 0. And a first replacement code that limits the continuation of the minimum run d to no more than a predetermined number of times.
A second replacement code for maintaining the run length restriction;
And a base code different from the second replacement code, and the first replacement code or the second replacement code
Is characterized by being subject to replacement restrictions.

An embodiment of the present invention will be described.
In the following, for convenience of description, the arrangement of data “0” and “1” before conversion (data string before conversion) is represented by (0
00011), the sequence (codeword sequence) of “0” and “1” after conversion is represented by “00”.
For example, 0100100 "is delimited by“ ”.

The following table shows an example of a conversion table for converting data of the present invention into codes.

The conversion table in Table 3 is a 1,7PP code. Further, when compared with Table 2, the code word strings immediately before and immediately after are converted so as to suppress the number of generations of the conversion code for limiting the continuation of the minimum run. By reference, the replacement is restricted.

Table 3 shows that the minimum run d = 1 and the maximum run k = 7.
Has an indeterminate code (a code including *) as an element of the basic code. The uncertain code is set to “0” so as to keep the minimum run d and the maximum run k irrespective of the code word strings immediately before and after.
Or “1”. That is, in Table 3, when the 2-bit data string to be converted is (11), “000” or “101” is determined according to the code word string immediately before it.
Is selected and converted to either of them. For example, when one channel bit of the immediately preceding code word string is “1”, 2-bit data (11) is
If it is converted to a code word "000" and one channel bit of the immediately preceding code word string is "0", it is converted to a code word "101" so that the maximum run k is maintained.

The conversion table of Table 3 has a variable length structure, and its basic code has i = 1 to 3. Further, since the conversion table in Table 3 has a replacement code for limiting the continuation of the minimum run d, the data string is (11).
0111), the immediately preceding and succeeding codewords are referred to. When the immediately preceding code word is “0” and the succeeding code word string is “010”, this data string is replaced with the code word “001 000 000”. Also, this data string is a 2-bit unit ((11),
(01), (11)), and is converted into a code word “*”.
0 * 010 * 0 * ". In this way, in the codeword string obtained by converting the data, the continuation of the minimum run is restricted.
The minimum run is repeated up to six times.

The replacement code for limiting the continuation of the minimum run d in Table 3 is determined with reference to both the immediately preceding code word sequence and the immediately succeeding code word sequence. Of these, the immediately preceding codeword string is
Although the sequence of the minimum run d is limited to six times even if it is not referred at the time of conversion, the number of occurrences of the replacement code can be reduced by making it as shown in Table 3.

In the conversion code shown in Table 3, the maximum constraint length r = 4. The code having the constraint length i = 4 is constituted by a replacement code (maximum run compensation code) for realizing the maximum run k = 7. That is, the data (0
0001000) is the code word "00010010010
0 ", and the data (00000000) is converted into a code word" 010100100100 ".
Also in this case, the minimum run d = 1 is maintained.

The conversion code in Table 3 is obtained by dividing the number of “1” in the elements of the data string by 2 and the number of “1” in the element of the code word string to be converted by 2 Have a conversion rule such that the remainder when divided by is either 1 or 0 and the same (any corresponding element has an odd or even number of “1” s). For example, the element (000001) of the data string in the conversion code is “010 100 1
It corresponds to the element of the code word string of "00", but the number of "1" of each element is one in the data string and three in the corresponding code word string. Are the same as 1 (odd number). Similarly, the element (000000) of the data string in the conversion code is “010”
100 000 ", which corresponds to the elements of the code word string.
The number of “1” s is 0 in the data sequence and 2 in the corresponding codeword sequence, and the remainder when divided by 2 matches 0 (even number).

[0051]

The conversion table shown in Table 4 is a 1,7PP code. Further, when compared with Table 2, the code word string (data string) ) To limit the replacement.

Table 4 shows that the minimum run d = 1 and the maximum run k = 7.
Has an indeterminate code (a code including *) as an element of the basic code. Further, since the conversion table in Table 4 has a variable length structure, the basic code has i = 1 to 3. Further, since the conversion table in Table 4 has a replacement code for limiting the continuation of the minimum run d, the data string is (11).
0111), refer to the following code word sequence,
When it is "010", this data string is a code word "
001 000 000 ". This data string is converted into a code word in 2-bit units ((11), (01), (11)) if the immediately succeeding code word string is not as described above. This is converted to the word "* 0 * 010 * 0 *". With this, in the codeword string obtained by converting the data, the continuation of the minimum run is limited, and the minimum run is repeated up to six times at the maximum.

Then, in the conversion table of Table 4,
The maximum constraint length r = 4. The code with the constraint length i = 4 is configured with a replacement code (maximum run compensation code) for realizing the maximum run k = 7. That is, when it is data (00001000), the subsequent data string is referred to, and when it is (01) or (001), this data string is represented by the code word "00010010".
0100 ". The data (00000000)
0) is a code word "01010010001" when the succeeding data string is (01) or (001).
00 ”. In this case as well, the minimum run d
= 1 is protected.

In other words, in the code having the constraint length i = 4, the replacement code (maximum run compensation code) for realizing the maximum run k = 7 has 6 bits of data (000010). Further, when the following code word string is “000”, this data string is converted into a code word “000100100100”. Also,
6 bits of data are (000000), and
If the succeeding code word string is “000”, it is converted to a code word “010100100100”.

The replacement code that realizes the maximum run k = 7 in Table 4 is determined by referring to the total data string of 11 bits by looking at the maximum of 3 bits in addition to the data string of 8 bits. At the time of conversion, the maximum run k = 7 can be realized by merely referring to the data string up to 8 bits. However, by performing the conversion as shown in Table 4, the number of occurrences of the replacement code can be reduced.

Similarly to Table 3, the conversion code in Table 4 is a remainder obtained by dividing the number of "1" in the element of the data string by two, and the remainder in the element of the code word string to be converted. There is a conversion rule such that the remainder when the number of 1 "is divided by 2 is equal to 1 or 0.

<Table 5> 1,7PP-32 (plus * 0 *) Data string Code string 11 * 0 * 10 001 01 010 0011 010 100 0010 010 000 0001 000 100 000011 000 100 100 000010 000 100 000 000001 010 100 100 000000 010 100 000 _________________________ # 110111 001 000 000 (next010 / * 0 *) # 00001000 000 100 100 100 # 00000000 010 100 100 100 # 110111 + 01/001/00000-> 001 000 000 # 110111 + "010"-> 001 000 000 # "* 0 * -010-101" + "010"-> 001 000 000 (110111-01 / 00/11) → 001 000 000 # 110111 + "* 0 *" → 001 000 000 # "* 0 * -010-101" + "* 0 *" → 001 000 000

The conversion table shown in Table 5 is a 1,7PP code. Further, as compared with Table 2, the two codewords immediately after the two types are used so as to suppress the number of occurrences of six consecutive occurrences of the minimum run which is the most repeated. The replacement is restricted by referring to the column.

Table 5 shows that the minimum run d = 1 and the maximum run k = 7.
Since the element of the basic code has an uncertain code (code including *) and has a variable length structure, the basic code is i = 1
Up to 3. The conversion table in Table 5 is as shown in Table 3
As shown in Table 4 and Table 4, the data string has (110111)
, Refer to the following code word string, and it is “0”.
When it is 10 "or" * 0 * ", this data string is replaced with a code word" 001 000000 ".
This data string is converted into a code word in units of 2 bits ((11), (01), (11)) under conditions other than the above two conditions, so that the code word "* 0 * 010 * 0 *" Is converted to ". As a result, in the code word sequence obtained by converting the data, the continuation of the minimum run is limited, and the minimum run is repeated up to six times.

The replacement code for limiting the continuation of the minimum run d in Table 5 is determined with reference to the two types of code word strings immediately after. One of the two immediately following codeword strings to be referenced is limited to six consecutive minimum runs d without being referred to at the time of conversion, but the conversion table shown in Table 5 should be used. Thus, the number of consecutive occurrences of the minimum run six times can be reduced.

The change codes in Table 5 are shown in Tables 3 and 4
Similarly, the maximum constraint length r = 4. The code having the constraint length i = 4 is constituted by a replacement code (maximum run compensation code) for realizing the maximum run k = 7. Further, the conversion code in Table 5 is the same as Tables 3 and 4, except that the remainder obtained by dividing the number of “1” in the element of the data string by 2 and “1” in the element of the code word string to be converted. "Has a conversion rule such that the remainder when dividing the number of""by 2 is the same at 1 or 0.

In general, as the maximum constraint length r increases, the bit shifts (the position of the edge bit shifts by one bit at the time of reproduction, forward or backward from the normal position).
The propagation characteristic of the demodulation error at the time deteriorates. As a result, it is conceivable that the data conversion portion having a large constraint length causes long demodulation error propagation. In other words, reducing the number of occurrences of the conversion having a large constraint length improves the error propagation characteristics. Therefore, in Table 2,
The 7PP code has a structure as shown in Tables 3 and 4, so that error propagation characteristics can be improved. In addition, as shown in Table 5, by reducing the number of occurrences of six times, which is the largest number of consecutive minimum runs, long error propagation can be reduced, thereby improving the error propagation characteristics.

Since Tables 3 to 5 are independent of each other,
A table in which these are combined can be configured. For example, Table 6 shown below is a combination of Tables 3 and 4, and has two conversion codes that can further reduce the number of occurrences of replacement codes that are conversions with a large constraint length. It is.

[0065]

When a synchronization signal is inserted at an arbitrary position in the code word string (channel bit string) generated by the conversion tables of Tables 3 to 6, this conversion table has a variable length structure. Therefore, a termination table is defined to terminate a code at an arbitrary position, and is used as needed.

Table 7 below shows an example of the synchronization signal and termination table in Tables 3 to 6 of the present invention. <Table 7> Sync & Termination for Tables 3 to 6 # 01 000 000 001 (12 channtl bits) # = 0 not terminate case # = 1 terminate case __________________ Termination table 00 000 0000 0000 010 100

For example, when inserting a synchronization signal at an arbitrary position, first, connection bits are set so as to keep the minimum run d and the maximum run k in connection with the immediately preceding and succeeding code word strings. A unique pattern for the synchronization signal is set in between. If a pattern that breaks the maximum run k = 7 is given as a synchronization signal pattern, for example, "#
01 000 000 001. The leading "#" of the synchronization signal pattern is a connection bit, "0" or "0".
The second channel bit following “#” is set to “0” to keep the minimum run.From the third channel bit, k is set as a synchronization signal pattern. A unique pattern of 9T where = 8 is provided, that is, eight “0” s are continuously arranged between “1” and “1”.

The termination table applicable to Tables 3 to 6 can be realized in the same manner as in Table 2, and the termination table is 00 000 0000 010 100 as shown in Table 7. The termination table is required for a basic code having a constraint length i in which the number of pairs of data strings and codeword strings is less than four (2 ^ m = 2 ^ 2 = 4).

The data (0
0) is converted to a code “000” and the data (0000)
Is converted to the code “010100”. This makes it possible to prevent the data immediately before the synchronization signal from being converted into a code when inserting the synchronization signal (the code immediately before the synchronization signal cannot be terminated).

Connection bit “#” of the synchronization signal pattern
Is for distinguishing between a case where a terminal table is used and a case where it is not used. That is, “#” of the first channel bit at the head provided as a synchronization signal
Is set to “1” when the termination code is used, and is set to “0” otherwise. By doing this,
The difference between the tables (whether or not a termination code is used) can be definitely identified.

If the terminal table is given as described above,
When the synchronization signal is inserted at an arbitrary position in combination with the synchronization signal pattern, it can be terminated.

FIG. 1 is a block diagram showing a configuration of a modulation device that performs a modulation process using the above-described conversion table.
Here, the data string is a variable length code (d,
k, m, n; r) = (1, 7; 2, 3; 4).

The data sequence input to the modulation device 1 is a DSV
The control bits “1” or “0” are determined and input to the DSV control bit determination / insertion unit 11 which inserts the control bits at an arbitrary interval. The data output from the DSV bit determination / insertion unit 11 is input to the modulation unit 12, subjected to modulation processing, and output to the NRZI conversion unit 13. The NRZI conversion unit 13 converts the input data into a recording code string. The timing management unit 14 generates a timing signal and supplies it to each unit to manage the timing.

FIG. 2 is a block diagram showing another example of the configuration of the modulation device 1. The data sequence input to the modulation device 1 is
The DSV control bit “1” or “0” is input to a control bit insertion unit 21 that inserts the DSV control bit at a predetermined position. The data output from the control bit insertion unit 21 is input to the modulation unit 12 and subjected to modulation processing.
The NRZI is output to the NRZI conversion unit 13 which performs NRZI conversion and level coding. The data output from the NRZI conversion unit 13 is input to a DSV bit determination unit 22 that selects the DSV-controlled one from the two input level code strings and uses this as a recording code string. Further, the timing management unit 14 generates a timing signal and supplies it to each unit to manage the timing.

FIG. 3 is a block diagram showing a configuration example of the modulation section 12. The shift register 31 shifts the data by two bits at a time, and outputs a constraint length determination unit 32, a minimum run continuation restriction code detection unit 33 including a substitution restriction, a run length restriction compensation code detection unit 34 including a substitution restriction, and a conversion unit 35. -1 to 35-4. At this time, the shift register 31 supplies the number of bits necessary for each unit to perform the processing to each unit.

The constraint length judging section 32 judges the constraint length i of the data and outputs it to the multiplexer 36. When detecting a code exclusively for restricting the continuation of the minimum run, the minimum run continuation restriction code detection unit 33 including the restriction on the replacement outputs a detection signal indicating the restriction length to the restriction length determination unit 32. When the run-length-restriction-compensation-code detecting section 34 including the replacement restriction detects a code dedicated to compensating for the maximum run shown in Table 6, it outputs a detection signal indicating the constraint length to the constraint-length determining section 32. .

When a dedicated code is detected by the minimum run continuation restriction code detecting unit 33 including the replacement restriction, or when a dedicated code is detected by the run length restriction compensation code detecting unit 34 including the replacement restriction, the constraint length is set. The determination unit 32 outputs the corresponding constraint length to the multiplexer 36. At this time, the constraint length determination unit 32 may determine another constraint length, but the minimum run continuous restriction code detection unit 33 including the replacement restriction or the run length restriction compensation code detection unit 34 including the replacement restriction. If there is a detection output based on the dedicated code from, the constraint length determination unit 32 determines the constraint length by giving priority to that output. In other words, the constraint length determination unit 32 selects a larger constraint length.

The conversion units 35-1 to 35-4 refer to the built-in conversion table and determine whether or not a conversion code corresponding to the supplied data is registered. After the data is converted into the corresponding code word, the converted code word is output to the multiplexer 36. If the corresponding data is not registered as a conversion code in the conversion table, the conversion units 35-1 to 35-4 discard the input data.

The multiplexer 36 includes a constraint length determining unit 32
The conversion unit 35-i (i
= 1 to 4), the converted code is selected, and the converted code is output as serial data via the buffer 37.

The operation timing of each unit is managed in synchronization with a timing signal supplied from the timing management unit 14.

Next, the operation of the modulation section 12 will be described. From the shift register 31, the constraint length determination unit 32, the minimum run continuous restriction code detection unit 33 including the replacement restriction, the run length restriction compensation code detection unit 34 including the replacement restriction, and the conversion units 35-1 to 35-4 include: The data input to the modulation unit 12 is supplied in units of 3 bits, and each unit is supplied with the number of bits necessary for determination and the like.

The constraint length judging section 32 incorporates, for example, a basic code portion of the conversion table shown in Table 6, judges the constraint length i of the data with reference to this conversion table, and determines the judgment result (constraint length i ) Is output to the multiplexer 36.

The minimum run continuation restriction code detection unit 33 including the substitution restriction includes a replacement code (in the case of Table 6,
A part to be converted with reference to the data (110111), the immediately preceding codeword “0” and the succeeding codeword “010”)
With reference to this conversion table, when a code that restricts the continuation of the minimum run is detected, the constraint length i =
3 is output to the constraint length determination unit 32.

Further, the run length restriction compensation code detecting unit 34 including the substitution restriction is the conversion code for protecting the maximum run in the conversion table shown in Table 6 (in the case of Table 6, the data (0
0001000-x) and (00000000-
x), x: (01) or (001))
Referring to this conversion table, when a replacement code that protects the maximum run is detected, a detection signal of the constraint length i = 4 is output to the constraint length determination unit 32.

When the detection signal of the constraint length i = 3 is input from the minimum run continuation restriction code detecting unit 33 including the replacement restriction, the constraint length determining unit 32 determines whether another constraint length is determined at that time. , The constraint length i (i = 3 in the example of Table 6) corresponding to the detection of the minimum run continuation restriction code detecting unit 33 including the replacement restriction is selected, and is output to the multiplexer 36. Similarly, the constraint length determination unit 32
Is a run length limit compensation code detection unit 3 including a replacement limit.
When the detection signal of the constraint length i = 4 is input from No.4, even if another constraint length is determined at that time, the constraint length is not selected and the run length limit compensation code detecting unit 34 including the replacement limit is detected. Length i (in the example of Table 6, i
= 4) and outputs it to the multiplexer 36.

In this way, the result of the determination of the constraint length in the minimum run continuation restriction code detecting unit 33 including the replacement restriction or the run length restriction compensation code detecting unit 34 including the replacement restriction, and the restriction length determining unit If the determination results of the constraint lengths at 32 differ, this means that the larger constraint length may be selected as the final constraint length.

FIG. 4 is a block diagram showing another example of the configuration of the modulating unit 12. As shown in FIG. The shift register 31 shifts the data by two bits at a time, and outputs a constraint length determination unit 32, a minimum run / maximum run compensation code detection unit 41, a minimum run continuation restriction code detection unit 42, a previous / next bit reference unit 43, and The data is output to the conversion units 35-1 to 35-4. At this time, the shift register 31 supplies the number of bits necessary for each unit to perform the processing.

The minimum run continuation restriction code detection section 42 and the minimum run / maximum run compensation code detection section 41 detect first and second replacement codes to which no replacement restriction is added. Then, the immediately preceding / immediate bit reference section 43 has given a rule for adding the replacement restriction shown in Table 6, and is output from the immediately preceding / immediate bit reference section 43 and is output from the constraint length determining section 3.
2 is input to the constraint length determination unit 32 shown in FIG.
And a similar signal. Other parts are the same as those in FIG. 3, and the description thereof will be omitted.

Next, referring to FIG. 5, the constraint length judging section 32, the minimum run continuation restriction code detecting section 33 including the replacement restriction, and the run length restriction compensating code detecting section 34 including the substitution restriction shown in FIG. The operation will be described with a specific example.

The run length restriction compensation code detection unit 34 including the substitution restriction performs the conversion of (0000) in the conversion table shown in Table 6.
If the input 8-bit data has a conversion part of (1000-x) and (00000000-x) and matches this, the next data is further referred to, and the next data is (01) or (001). ), The constraint length i =
4 is output to the constraint length determination unit 32. In other words, if the input 6-bit data matches (000010) and (000000) and the code word string immediately following it is “000”, the detection signal with the constraint length i = 4 is restricted. This is output to the length determination unit 32.

The minimum run continuation restriction code detecting section 33 including the substitution restriction is configured to output the data (110111), the code “0” immediately before the code “0” and the code “0” immediately after the data in the conversion table shown in Table 6.
The input 6-bit data having a conversion part of 10 ″ is (110111), and the code word immediately before it is “110111”.
If it is “0” and the immediately following three codewords are “010”, a detection signal with the constraint length i = 3 is output to the constraint length determination unit 32. Then, the part of the three codewords “010” is removed. , (001), (001),
Or (00000). Therefore, the minimum run continuation restriction code detecting unit 33 including the restriction on the substitution
0 "+ (110111) + (01/001/0000)
0), in addition to the input 6-bit data, in addition to the immediately preceding 1 code, up to the immediately succeeding 5-bit data, and if they match any of these , And outputs a detection signal with the constraint length i = 3 to the constraint length determination unit 32.

The constraint length judging section 32 has a built-in basic code portion of the table shown in Table 6, and the inputted 6-bit data is (0000011), (00001).
0), (000001), or (000000), it is determined that the constraint length i = 3. Also, the input 4-bit data is (0011), (0
010) or (0001), the constraint length determination unit 32 determines that the constraint length i = 2. further,
The input 2-bit data is (11), (10),
If any one of (01) is matched, the constraint length determination unit 32
Determines that the constraint length i = 1.

When the input data is, for example, (000010), the constraint length determination unit 32
It is determined that the constraint length i = 3. However, in addition to the above 6 bits, further data is (0001) or (0)
0001), the run length restriction compensation code detection unit 34 including the substitution restriction determines that the constraint length i = 4. In such a case, the priority is given to the output signal from the run length limitation compensation code detection unit 34 including the replacement limitation, and the constraint length i is determined to be i = 4.

In this manner, according to the table of Table 6, the maximum constraint length of 8 bits and, if necessary, the immediately preceding or succeeding code word sequence are referred to, and all (1) and (0) are referred to. The constraint length is determined from the following data string.

The constraint length judging section 32 outputs the constraint length i thus determined to the multiplexer 36.

It is to be noted that the constraint length judging section 32 reverses the order shown in FIG. 5 so that i = 1, i = 2,
The constraint length may be determined in the order of i = 3, i = 4.

Each of the conversion units 35-1 to 35-4 stores a table (the conversion unit 35-1) corresponding to each constraint length i.
Has a table of i = 1, the conversion unit 35-2 has a table of i = 2, the conversion unit 35-3 has a table of i = 3, and the conversion unit 35-4 has a table of i = 4). If the conversion rule corresponding to the supplied data is registered in the table, the supplied 2 ×
The i-bit data is converted into a 3 × i-bit code, and the code is output to the multiplexer 36.

The multiplexer 36 includes a constraint length determining unit 33
A code is selected from the conversion unit 35-i corresponding to the supplied constraint length i, and the code is output as serial data via the buffer 37.

Here, for example, in Table 6, the constraint length i =
Replacement code (1
Suppose that 1 01 11) does not exist. At this time, as data, (01 11 01 11 01 11 01 1 1
When (101) is input, the conversion process is performed in the order of data (01) (11) (01) (11) (01)... And "010 101 010 101 010 101".
010 101 010 "is generated.

The code generated in this way is, for example,
When converted to NRZI and converted to a level code, the "
1 ", the logic is inverted.
01 100 110 011 001 100... ", And the 2T minimum inversion interval is continuous.
Such a recording code string is a pattern in which an error easily occurs during recording and reproduction at a high linear density.

Therefore, as shown in Table 6, the replacement code for limiting the repetition of the minimum run is represented by (11 01 11)
Stipulates that (01 11 01 11 01 11 01 01
11 01), the first data (0
1) + (11 01 11) + (01) becomes “0” +
(11 01 11) + “010” ”, which is replaced and converted, and (11 01 11) is“ 001 000 0
00 ". The next data (11 01 1
1) From “+ (01)” and the immediately preceding codeword string “0”, “0”
+ (11 01 11) + “010” ”, and is replaced and converted, and (11 01 11) becomes“ 001 000 ”.
000 ". After all, the code word string is" 010 001 ".
000 000 010 001 000 000 010
... "to prevent the repetition of the minimum run from continuing. Therefore, during recording and reproduction at a high linear density, a pattern in which an error easily occurs is removed, and the above-described replacement conversion is performed. In this case, the minimum run and the maximum run will be maintained.

In the above description, the case where Table 6 is used in the modulation section 12 has been described, but it is also possible to use Table 3 to Table 5. In such a case, details of the minimum run continuation restriction code detection unit 33 including the replacement restriction and the run length restriction compensation code detection unit 34 including the replacement restriction in the modulation unit 12 shown in FIG. What is necessary is just to correspond to any of Table 5.

By the way, the arrangement order may be different within each constraint length of the data string and the code word string in Tables 3 to 6. For example, for the constraint length i = 1 in Table 6, May be arranged as follows. Also in this case, the number of “1” in the element of the data string and the number of “1” in the element of the code word string are set such that the remainders when divided by 2 are both 1 or 0. .

In addition, (1) and (0) of each element of the data string in Tables 3 to 6 may be inverted. That is, the data sequence code sequence 11 * 0 * 10 001 01 010 0011 010 100 0010 010 000 0001 000 100 may be as follows, and even in this case, the number of “1” in the data sequence is Regarding the number of “1” of the elements of the code word string, the remainders when divided by 2 are both equal to 1 or 0. Data string Code string 00 * 0 * 01 001 10 010 1100 010 100 1101 010 000 1110 000 100

FIG. 6 is a block diagram showing a configuration of a demodulation device 51 for demodulating data modulated by the above processing. The demodulation device 51 includes a variable length code (d, k; m, n;
r) = (1, 7; 2, 3; 4) is demodulated into a data string using the inverse conversion table of Table 6.

The demodulation device 51 compares the signal transmitted from the transmission line or the signal reproduced from the recording medium, converts the signal into an inverse NRZI, and converts the recording code sequence into a code word sequence. It is input to the inverse NRZI conversion section 52. The signal output from the comparator / inverse NRZI conversion section 52 is input to a demodulation section 53 that performs demodulation based on a demodulation table (inverse conversion table). The data sequence demodulated by the demodulation unit 53 is input to a DSV control bit removal unit 54 that removes the DSV control bits in the data sequence inserted at an arbitrary interval and restores the original data sequence. The data string output from the DSV control bit removing unit 54 is
The serial data is temporarily stored, read out at a predetermined transfer rate, and output. Timing management unit 5
6 generates a timing signal and supplies it to each unit to manage the timing.

FIG. 7 is a block diagram showing a configuration example of the demodulation unit 53. The constraint length determining unit 61 calculates the comparison / reverse N
The RZI unit 52 receives the input of the digitized signal and determines the constraint length i. Further, the minimum run continuation restriction code detecting unit 62 detects a dedicated code given for restricting the continuation of the minimum run from the digitized signal, and sends a corresponding detection signal to the constraint length determination unit 61. . Further, the run length restriction compensation code detection unit 63 detects a dedicated code given for compensating the maximum run from the input signal, and sends a corresponding detection signal to the constraint length determination unit 61.

The inverse transform units 64-1 to 64-4 are provided with n × i
It has a table for inversely converting a variable length code of bits into data of m × i bits. The multiplexer 65 outputs one of the outputs from the inverse conversion units 64-1 to 64-4,
A selection is made according to the determination result of the constraint length determination unit 61, and output as serial data.

Next, the operation of the demodulation unit 53 shown in FIG. 7 will be described. The signal transmitted from the transmission path or the signal reproduced from the recording medium is compared with the signal of the inverse NR
The data is input to the ZI conversion unit 52 and compared. Further, the digital signal is converted into a digital signal of an inverse NRZI code (code in which “1” indicates an edge) and is input to the constraint length determination unit 61, and the constraint length is determined according to the basic code portion of the conversion table (inverse conversion table) shown in Table 6. Is determined. The judgment result (constraint length) of the constraint length judging section 61 is output to the multiplexer 65.

The digital signal input to the demodulation unit 53 is
It is also input to the minimum run continuation restriction code detection unit 62. The minimum run continuation restriction code detecting unit 62 replaces the minimum run continuation code (in the case of Table 6, the code word “001 000 000”) in the conversion table shown in Table 6.
Is converted, and the code "001" for limiting the continuation of the minimum run is referred to by referring to the reverse conversion table.
When “00000 000 not100” is detected, a detection signal of the constraint length i = 3 is output to the constraint length determination unit 61. Here, “not100” means a code word other than “100”.

Further, the input digital signal is also input to the run length restriction compensation code detection section 63. The run length restriction compensation code detection unit 63 replaces the replacement code (in the case of Table 6, the code word strings “000 100 100 100” and “010”) in the conversion table shown in Table 6 with the maximum run.
100 100 100 "). When a replacement code that protects the maximum run is detected with reference to the inverse conversion table, a detection signal of the constraint length i = 4 is output to the constraint length determination unit 61.

FIG. 8 is a diagram for explaining the determination processing of the constraint length determination unit 61, the minimum run continuation restriction code detection unit 62, and the run length restriction compensation code detection unit 63. That is, the run length restriction compensation code detection unit 63 determines whether “000 100 100 100” or “0” in the table shown in Table 6.
When the input 12-bit code word string has the inverse transform portion of 10 100 100 100 ", it outputs a detection signal of the constraint length i = 4 to the constraint length determination unit 61.

The minimum run continuation restriction code detecting section 62 has an inverse conversion part of “001 000 000” in the table shown in Table 6, and converts the input 12-bit code word string to “0”.
01 000 000 not100 "
The detection signal of the constraint length i = 3 is output to the constraint length determination unit 61.

The constraint length judging section 61 has a built-in inverse conversion table shown in Table 6, and stores the input 9 bits or 1 bit.
A 2-bit code word string is “000 100 100”, “
000 100 000 not100 "," 010 100
100 ”or“ 010 100 000 not10
0, it is determined that the constraint length i is 3. If this is not the case, the input 6-bit or 9-bit codeword string is "010 100", "01".
If it matches either 000 not100 "or" 000100 ", it is determined that the constraint length i is 2. If this is not the case, the input 3-bit codeword string is" 000 "," 101 "," 001 ",
Alternatively, when it matches any one of “010”, the constraint length determination unit 61 determines that the constraint length i = 1.

The constraint length determination process of the constraint length determination unit 61, the minimum run continuation restriction code detection unit 62, and the run length restriction compensation code detection unit 63 is performed in order from the smaller constraint length to i.
= 1, i = 2, i = 3, i = 4 in this order.

The constraint lengths are set in the order of i = 1, i
= 2, i = 3, i = 4, the input codeword string is, for example, “000 100 100 10
When the constraint length is “0”, the constraint length judging section 61 judges whether the constraint length matches or mismatches in order from the smallest constraint length. If the constraint length i = 1, the constraint length i = 2, the constraint length i = 3, or This applies to the constraint length i = 4 and all constraint lengths i. In such a case, the largest one from the determined constraint lengths i may be selected and determined.

Of the inverse conversion units 64-1 to 64-4, for example, in the inverse conversion unit 64-1, data (11) is stored at addresses “101” and “000”, and an address “001” is stored.
And data (01) are written in the address “010”, respectively. Hereinafter, similarly, in each of the inverse conversion tables of the inverse conversion units 64-2 to 64-4, corresponding data is written, and the supplied 3 × i-bit code word string is converted into a 2 × i-bit code word string. The data word is converted to a data string, and the data word is output to the multiplexer 65.

The multiplexer 65 includes an inverse conversion unit 64-1.
−４64-4 are selected in accordance with the constraint length determination result of the constraint length determination unit 61 and output as serial data.

The following table 8 shows the inverse conversion table of Table 6.
become that way. <Table 8> Inverse conversion table (1, 7; 2, 3; 4) Codeword string Demodulated data string i = 4: limits k to 7 000 100 100 100 00001000 010 100 100 100 00000000 i = 3: Prohibit Repeated Minimum Transition Runlength 001 000 000 (not 100) 110 111 000 100 0001 i = 1 101 11 000 11 001 10 010 01

Next, referring to the flowchart of FIG.
The operation of the DSV control bit remover 54 will be described. DSV
The control bit removing unit 54 has a counter inside, and when the bits of the data string are input from the demodulation unit 53 in step S1, counts the number. In step S2, it is determined whether or not the count value has reached a predetermined data interval for inserting the DSV control bit. If it is determined that the count value is not an arbitrary data interval, the process proceeds to step S3, where the count value is input from the demodulation unit 53. The output data is output to the buffer 55 as it is. In contrast, step S2
In, when it is determined that it is a predetermined data interval,
Since that bit is a DSV control bit, step S3
Is skipped, and the process proceeds to step S4. That is, in such a case, the bit is not output to the buffer 55 and is discarded.

Next, in step S4, processing for inputting the next data is executed. Then, in step S5, it is determined whether or not processing for all data has been completed. If there is data that has not been processed yet, the process returns to step S1, and the subsequent processing is repeatedly executed. If it is determined in step S5 that all data has been processed, the processing of this flowchart ends.

As described above, the data output from the DSV control bit removing section 54 is data from which the DSV control bits have been removed. This data is output via the buffer 55.

Incidentally, at the time of data modulation, the synchronization signal (Sy
10 and 11 show examples of the configuration of the modulation apparatus when nc) is inserted, and FIG. 11 shows an example of the configuration of the demodulation apparatus.
Also in these embodiments, the data sequence is based on the variable length code (d, k; m, n; r) = (1, 7;
2, 3; 4) and demodulated.

As shown in FIG. 10, in the modulator 71 that inserts synchronization signals at predetermined intervals, the output of the DSV control bit determination / insertion unit 72 is output from the modulation unit 73 and the SYNC determination unit 7.
4 is supplied. The output from the modulator 73 is also supplied to the SYNC determiner 74. The SYNC determining unit 74 determines a synchronization signal from these input signals, and outputs its output to the SYNC insertion unit 75. The SYNC insertion unit 75 includes a modulation unit 73
The synchronization signal input from the SYNC determination unit 74 is inserted into the input modulation signal, and is output to the NRZI conversion unit 76.
The other configuration is the same as that of the modulation device 1 shown in FIG.

The SYNC determining unit 74 sets the synchronization signal pattern to 1
When two codewords are used, the synchronization signal is “# 01 0000 0”.
“001” depends on the immediately preceding data string (DSV control bits may be included) separated by the insertion of the synchronization signal, and the divided data string is modulated according to the conversion table. In this case, when termination is performed using the termination table, “#” is set to “1”. When termination is performed using the table in Table 2 without using the termination table, “#” is set to “0”. You.

The modulator 73 uses “#” = “1” when the termination table is used, and “#” = “0” when not used.
Is output to the SYNC determination unit 74. When receiving the value of “#” from the modulator 73, the SYNC determiner 74 inserts the value into the first bit of the synchronization signal. Then, the synchronization signal is output to the SYNC insertion unit 75.

The SYNC insertion section 75 inserts the synchronization signal output from the SYNC determination section 74 into the output from the modulation section 73,
Output to the NRZI conversion unit 76. Other operations are the same as those of the modulation device 1 shown in FIG.

The first data after the insertion of the synchronization signal is converted from its head (without considering the data immediately before the synchronization signal). Modulator 73 and SYNC determiner 7
Reference numeral 4 includes a counter for counting a predetermined interval at which the synchronization signal is inserted, and determines the position of the synchronization signal according to the count value.

FIG. 11 is a block diagram showing a configuration of another modulation device 71. The signal input to the modulator 71 is
A control bit insertion unit 81 that inserts “1” or “0” which is a DSV control bit at a predetermined position in a data string.
, And further input to a modulator 73 that modulates two types of data strings. The output from the modulation unit 73 is input to a synchronization signal insertion unit 75 that inserts a synchronization signal at predetermined intervals, and is further NRZI-encoded and level-encoded.
6 is input. Then, the signal output from the NRZI conversion section 76 is a DSV bit / SYNC
It is input to the decision unit 82. In addition, the modulation device 71 includes a timing management unit 77 that generates a timing signal and supplies the timing signal to each unit to manage the timing.

The modulator 73 of the modulator 71 shown in FIG. 10 or 11 is, for example, the modulator 12 shown in FIG. 3 or FIG.
It is possible to realize with the same configuration as described above.

FIG. 12 is a block diagram showing an example of the configuration of a demodulation device for demodulating a code modulated and output by the modulation device 71 of FIG. 10 or FIG. The code input to the demodulation device 91 via a predetermined transmission path is input to the comparator / inverse NRZI conversion unit 92 and is converted into a codeword string. The codeword string output from the comparator / inverse NRZI conversion section 92 is input to a demodulation section 93 and a SYNC identification section 94. SY
The NC identification unit 94 identifies a synchronization signal using the input code, and outputs the identification signal to the demodulation unit 93 and the SYNC removal unit 95. The SYNC removing unit 95 removes a synchronization signal from the demodulated signal input from the demodulation unit 93 in accordance with the output of the SYNC identification unit 94, and outputs a signal from which the synchronization signal has been removed to the DSV control bit removal unit 96.

The SYNC identification section 94 counts the codewords by a built-in counter, and determines the position of the synchronization signal inserted at a predetermined interval from the count value. When the position of the synchronization signal pattern is determined, the SYNC identification section 94 reads the "#" portion determined at the time of the next modulation. That is, the first bit of the synchronization signal bit portion is read and is
Output to 3. If the first bit is “1”, the demodulation unit 93 uses the end table in Table 6 to demodulate the code immediately before it. If the first bit is “0”, the demodulation unit 9
3 uses the conversion code table in Table 6 for demodulating the code immediately before. Other synchronization signal bits are unnecessary because they are bits having no information.

The SYNC identification section 94 outputs an identification signal for identifying the bits constituting the synchronization signal to the SYNC removal section 95.
The SYNC remover 95 removes only the synchronization signal bits specified by the identification signal output from the SYNC identifier 94 from the data output from the demodulator 93, and outputs the data to the DSV control bit remover 96.

The demodulation section 93 of the demodulation device 91 in FIG. 12 can be realized by the same configuration as the demodulation section 53 shown in FIG. It is.

Here, the result of verifying the modulation result using the conversion table described in the embodiment is shown. Table 6 which restricts the continuation of Tmin and modulates a data string in which a DSV control bit is inserted in the data string, further provides a conversion code for adding a conversion condition of a replacement code and reducing demodulation error propagation. I have. In the simulation, the conventional 1,7PP code according to Table 2 was compared with the 1,7PP code according to Table 6 using the present embodiment.

Arbitrarily created random data 13,107,200
After performing DSV control by inserting a 1-bit DSV control bit for every 56 data-bits and then converting it to a codeword string (channel bit string) using the modulation code table in Table 2 or Table 6, the result is It is as follows.

The numerical value of each result was calculated as follows. Ren_cnt [1 to 10]: Number of occurrences of 1 to 10 repetitions of the minimum run. T_size [2 to 10]: Number of occurrences of each run from 2T to 10T. Sum: Number of bits. Total number of bits. Total: Number of runlengths. Total number of occurrences of each run (2T, 3T, ...) Average Run: (Sum / Total) Numeric value of run distribution: (T_size [i] * (i)) / (Sum), i = 2, 3,4 ,,, 10

The numerical values shown in the columns 2T to 10T in Table 9 below show the numerical values of this run distribution.

Numerical value of continuous distribution of Tmin: (Ren_cnt [i]
* (i)) / T_size [2T], i = 1,2,3,4 ... 10

The values shown in the columns of RMTR (1) to RMTR (7) in Table 9 represent the numerical values of the continuous distribution of the minimum runs. max-RMTR: The maximum number of repetitions of the minimum run. peak DSV: In the process of performing DSV control of the codeword string, DS
The peak on the plus side and the peak on the minus side of the DSV value when the V value is calculated. The redundancy rate when DSV control bits are inserted every 56 data columns as DSV control bits is as follows:
Since the DSV control bit is 1 bit for 56 data strings,
The redundancy is 1.75% (1 / (1 + 56)).

[0142]

From the results described above, it was found that
The 7PP code and the 1,7PP code according to Table 6 of the present embodiment are:
It is confirmed that the minimum run d = 1, the maximum run k = 7, and the minimum run are each limited to a maximum of six times, and that the DSV control can be performed in the data sequence from the peak DSV results. (The peak DSV value is within a predetermined range). Also, from Table 9, Table 2
It was found that there was no difference in the characteristics between the run distribution and the minimum run continuous number distribution due to the difference between the table of FIG.

Next, a simulation result of demodulation will be described. Demodulation was performed by the same demodulation method in both Table 2 and Table 6 so that comparisons were possible. In addition to confirming that demodulation was performed normally, a bit shift error was arbitrarily generated in the codeword string, and the demodulation error propagation characteristics at this time were examined. Demodulation error propagation refers to the number of bits propagated at the time of demodulation with respect to one bit shift error in a code word string, and this is regarded as a byte error by setting it in units of 8 bits.

[0145]

From the results shown in Table 10, both Tables 2 and 6 have 1,7P
It was confirmed that the worst error propagation of P was 3 bytes, but the actual occurrence frequency was almost nil. Also, by adding the conversion condition of the replacement code according to Table 6 and providing the conversion code for reducing the demodulation error propagation, the occurrence rate of long error propagation is reduced from 15.0% to 14.4%, and the average byte error propagation length is also reduced. Could also be reduced.

As another effect of the present embodiment,
Consider the case of Table 5. When this table is used, the RMTR characteristic can be changed at the same time as the average error propagation length is reduced.

<Table 11> *** 1,7PP comparison *** <Table 2> <Table 6> <Table 5> Conventional 1,7PP New 1,7PP New 1,7PP RMTR (1) 0.3837 0.3803 0.3886 RMTR ( 2) 0.3107 0.3032 0.3099 RMTR (3) 0.1738 0.1799 0.1839 RMTR (4) 0.0938 0.0968 0.0866 RMTR (5) 0.0299 0.0319 0.0261 RMTR (6) 0.0081 0.0079 0.0049 RMTR (7) ------ ------- ----- max-RMTR 6 6 6

Table 5 shows that the number of occurrences of a long RMTR can be reduced. Therefore, when a simulation similar to that in Table 9 is performed, the RMTR is the same up to six times, and
The frequency of occurrence of a large number of times such as RMTR (4), RMTR (5), and RMTR (6) is reduced. In particular, Table 11 shows that the occurrence probability of the maximum RMTR (6) is reduced from about 0.008 to about 0.005, which is reduced to about 2/3.

As described above, by further reducing the large RMTR, it is possible to prevent a long error propagation when an error occurs, and it can be expected that the error propagation value is improved.

For the 1,7PP code, in the conversion table having the minimum run d = 1, the maximum run k = 7, and the conversion rate m / n = 2/3, a replacement code for limiting the number of repetitions of the minimum run length is provided. Therefore, (1) the recording / reproducing at a high linear density and the tolerance for tangential tilt can be improved. (2) The portion where the signal level is low decreases, and AGC and P
Accuracy of waveform processing such as LL can be improved, and overall characteristics can be improved. (3) The path memory length for Viterbi decoding or the like can be designed to be shorter than before, and the circuit scale can be reduced.

Also, the number of “1” in the element of the conversion table and the number of “1” in the element of the code word string to be converted are
Since the remainder when divided by 2 is made to match with either 1 or 0, (4) redundant bits for DSV control can be reduced. (5) For the minimum run d = 1 and (m, n) = (2,3),
DSV control can be performed with 1.5 codewords. (6) The minimum run and the maximum run can be protected while the redundancy is small.

Further, since the present table is provided with a replacement code for keeping the run length restriction, (7) the table can be made compact.

In the present embodiment, the fact that the error propagation length at the time of demodulation becomes longer is determined by using a table structure that reduces the number of occurrences of conversion codes that increase error propagation. Demodulation error propagation can be made smaller than the conventional 1,7 PP shown in Table 2.

[0155] In the present specification, a providing medium for providing a user with a computer program for executing the above processing includes an information recording medium such as a magnetic disk and a CD-ROM, and a network such as the Internet and a digital satellite. Transmission media is also included.

[0156]

As described above, the modulating device according to claim 1, the modulating method according to claim 6, the providing medium according to claim 7, the demodulating device according to claim 8, and the modulating device according to claim 9. According to the demodulation method of the present invention, and the providing medium according to claim 10,
The input data is converted into a code according to the conversion table, and the conversion code of the conversion table is obtained by dividing the number of “1” in the elements of the data string by 2 and the code word string to be converted. A conversion rule in which the remainder when dividing the number of "1" in the element of "2" by 2 is equal to 1 or 0, and a first replacement for limiting the continuation of the minimum run d to a predetermined number or less. A first replacement code, a second replacement code, and a base code different from the first replacement code and the second replacement code. Is restricted, the code word string with high linear density and few errors can be recorded and reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a modulation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing another configuration of the modulation device.

FIG. 3 is a block diagram illustrating a configuration of a modulation unit.

FIG. 4 is a block diagram illustrating another configuration of the modulation unit.

FIG. 5 is a diagram illustrating modulation.

FIG. 6 is a block diagram illustrating a configuration of a demodulation device.

FIG. 7 is a block diagram illustrating a configuration of a demodulation unit.

FIG. 8 is a diagram illustrating demodulation.

FIG. 9 is a flowchart illustrating a DSV control bit removal process.

FIG. 10 is a block diagram showing another configuration of the modulation device.

FIG. 11 is a block diagram showing still another configuration of the modulation device.

FIG. 12 is a block diagram illustrating another configuration of the demodulation device.

[Explanation of symbols]

11 DSV bit determination / insertion unit, 12 modulation unit, 1
3 NRZI conversion section, 14 timing management section, 21 control bit insertion section, 22 DSV bit determination section,
32 Constraint length judgment unit, 33 Minimum run continuous restriction code detection unit including replacement restriction, 34 Run length restriction compensation code detection unit including replacement restriction, 41 Minimum run / maximum run compensation code detection unit, 42 Minimum run continuous restriction code detection Section, 43 immediately preceding / immediate bit reference section, 52
Comparator / inverse NRZI generator, 53 demodulator, 54
DSV control bit removal unit, 61 constraint length judgment unit, 62
Minimum run continuous limit code detector, 63 run length limit compensation code detector

Claims (10)

[Claims] A data having a basic data length of m bits and a variable length code having a basic code length of n bits (d, k; m, n;
r) a conversion device for converting the input data into a code according to a conversion table, wherein the conversion code in the conversion table is such that the number of “1” in the element of the data string is two. A conversion rule in which the remainder when dividing and the remainder when dividing the number of “1” in the element of the codeword string to be converted by 2 are both equal to 1 or 0; A first replacement code for limiting the continuation to a predetermined number of times or less, a second replacement code for keeping the run length limit, and a basic code different from the first replacement code and the second replacement code. The modulation device according to claim 1, wherein the first replacement code or the second replacement code is subject to replacement restriction. 2. The replacement restriction added to the first replacement code or the second replacement code is performed by referring to at least one of a code word string immediately before and after the replacement code. 3. The modulation device according to claim 1. 3. The replacement restriction added to the first replacement code or the second replacement code is performed by referring to at least one of a preceding code word sequence and a succeeding data sequence. The modulation device according to claim 1. 4. The modulation apparatus according to claim 1, further comprising an insertion unit that inserts a synchronization signal of a codeword string obtained from the modulation code of the input data at an arbitrary position. 5. The apparatus according to claim 1, wherein the insertion unit further includes a first detection unit that detects the first replacement code, and a second detection unit that detects the second replacement code. Item 5. The modulation device according to Item 4. 6. A data having a basic data length of m bits and a variable length code (d, k; m, n;
r) a modulation method of the modulation device for converting the input data into a code according to a conversion table, wherein the conversion code of the conversion table is the number of “1” in the elements of the data string. The conversion rule that the remainder when dividing by 2 and the remainder when dividing the number of “1” in the element of the code word string to be converted by 2 is equal to 1 or 0; A first replacement code for limiting the continuation of the run d to a predetermined number or less, a second replacement code for maintaining the run length limitation, and a different basis from the first replacement code and the second replacement code A modulation method, wherein the first replacement code or the second replacement code is subject to a replacement restriction. 7. A data having a basic data length of m bits and a variable length code (d, k; m, n;
r) a medium for providing a program for causing a modulation device to execute a process including a conversion step of converting input data into a code in accordance with a conversion table in the modulation device for converting the input data into a code. Is the remainder when dividing the number of “1” in the element of the data string by 2 and the remainder when dividing the number of “1” in the element of the codeword string to be converted by 2 A conversion rule that matches with 1 or 0, a first replacement code for limiting the continuation of the minimum run d to a predetermined number or less, a second replacement code for keeping the run length limitation, A replacement code and a base code different from the second replacement code, wherein the first replacement code or the second replacement code is subject to replacement restrictions. Medium. 8. A demodulator for converting a variable length code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits. A conversion means for converting the data into data according to the table; a conversion code of the conversion table includes a remainder obtained by dividing the number of “1” in the data string element by two, and a conversion code in the code word string element to be converted; A conversion rule such that the remainder when dividing the number of "1" of "2" by 2 is equal to 1 or 0; a first replacement code for limiting the continuation of the minimum run d to a predetermined number or less; A second replacement code for keeping a run length restriction, and a first replacement code and a basic code different from the second replacement code, wherein the first replacement code or the second replacement Code is a replacement system Demodulating apparatus characterized by is added. 9. A demodulation method of a demodulator for converting a variable length code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits. Is converted into data in accordance with a conversion table. The conversion code of the conversion table includes a remainder obtained by dividing the number of “1” in an element of the data string by 2, and a code word string to be converted. A conversion rule such that the remainder when dividing the number of "1" in the element of 2 by 2 is either 1 or 0, and a first replacement for limiting the continuation of the minimum run d to a predetermined number of times or less. A first replacement code, a second replacement code for maintaining a run length restriction, and a basic code different from the first replacement code and the second replacement code. 2 replacement code Demodulation method characterized by replacement limit is added. 10. A demodulator which converts a variable length code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits, converts the input code into a demodulator. A conversion medium for providing a program for causing a demodulation device to execute a process including a conversion step of converting data into data according to a table, wherein a conversion code of the conversion table is obtained by setting the number of “1” in an element of a data string to two. A conversion rule in which the remainder when dividing and the remainder when dividing the number of “1” in the element of the codeword string to be converted by 2 are both equal to 1 or 0; A first replacement code for limiting the continuation to a predetermined number of times or less, a second replacement code for keeping the run length limit, and a basic code different from the first replacement code and the second replacement code. Having the first Replacement code or the second replacement code is provided medium characterized by replacement limit is added.