JP2000068849A - Modulation device and method, demodulation device and method and providing medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To limit the number of times of the succession of minimum runs by limiting the succession of the minimum runs to be equal to or less than the prescribed number of times and performing modulation. SOLUTION: A Digital Sum Value(DSV) bit decision/insertion part 11 DSV controls an inputted data stream at an optional interval first, decides the '1' or '0' of a DSV control bit, inserts it at the optional interval and supplies the DSV-controlled data stream to a modulation part 12. The modulation part modulates the data string into which the DSV control bit is inserted and supplies the obtained code stream to a Non-Return-to-Zero Inversion(NRZI) part 13. The NRZI part 13 NRZI-modulates the code stream and converts it to a recording waveform string. A timing management part 14 generates timing signals, supplies them to the DSV bit decision/insertion part 11, the modulation part 12 and the NRZI part 13 and manages the timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation apparatus and method, a demodulation apparatus and method, and a providing medium, and more particularly to a modulation apparatus and method, a demodulation apparatus and method suitable for data transmission and recording and reproduction on a recording medium. In addition, it relates to a providing medium.

[0002]

2. Description of the Related Art When data is transmitted to a predetermined transmission line or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated so as to be suitable for transmission and recording. A block code is known as one of such modulation methods. In this block code, a data sequence is divided into units of m × i bits (hereinafter referred to as data words), and the data words are converted into code words of n × i bits according to an appropriate coding rule. This code is a fixed-length code when i = 1, and when a plurality of i can be selected, ie, 1
When a predetermined i in the range of i to imax (maximum i) is selected and converted, a variable length code is obtained. This block-coded code is represented as a variable-length code (d, k; m, n; r).

Here, i is called a constraint length, and imax is r
(Maximum constraint length). In addition, d indicates the minimum number of consecutive “0” s, for example, the minimum run of “0”, between consecutive “1” s, and k indicates the maximum number of consecutive “0s” between consecutive “1s”. The number indicates a maximum run of, for example, “0”.

When the variable length code obtained as described above is recorded on an optical disk, a magneto-optical disk, or the like, for example, in a compact disk (CD) or a mini disk (MD: trademark), the variable length code is set to "1". "Non-Return to Zero"
Inverted) modulated and NRZI modulated variable length code (hereinafter, referred to as
Recording is performed based on a recording waveform sequence. In addition, the initial IS, which was not so large in recording density,
In a magneto-optical disk of the O standard, a bit string subjected to recording modulation was recorded without being subjected to NRZI modulation.

The minimum inversion interval of the recording waveform sequence is Tmin,
When the maximum inversion interval is Tmax, in order to perform high-density recording in the linear velocity direction, the longer the minimum inversion interval Tmin is,
That is, it is preferable that the minimum run d is large, and from the viewpoint of clock reproduction, it is desirable that the maximum inversion interval Tmax is short, that is, the maximum run k is small. To satisfy this condition, various modulation methods are used. Proposed.

More specifically, as a modulation method proposed or actually used in, for example, an optical disk, a magnetic disk, or a magneto-optical disk, a variable length code such as RLL (1-7) or RLL (2-7) is used. ), And ISO standard M
There is a fixed length RLL (1-7) used for O.

The conversion table of the variable length RLL (2-7) code is, for example, the following table. Maximum constraint length r
Is 4.

[0008]

The parameter of the variable length RLL (2-7) is (2,7; 1,2; 4). If the bit interval of the recording waveform sequence is T, the minimum inversion interval represented by (d + 1) T Tmin is 3 (= d + 1 = 2 + 1 = 3) T. If the bit interval of the data string is Tdata, this (m / n) × 2
Is 1.50 (= (1 /
2) × 3) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is 8 (= 7 + 1) T (= ((m /
n) × Tmax) Tdata = (１ ／) × 8Tdata = 4.
0Tdata). Further, the detection window width Tw is (m / n) ×
Tdata, whose value is 0.50 (= １ ／) Tdata
Becomes

In general, as the linear recording density increases, it becomes difficult to record and reproduce at the shortest wavelength. Comparing the shortest wavelengths of the RLL (1-7) code and the RLL (2-7) code, each shortest wavelength is determined by Tmin and the conversion efficiency, so that RLL (1-7): Tmin × (2/3) = 1.33 Tdata RLL (2-7): Tmin x (1/2) = 1.50 Tdata, and the shortest wavelength of RLL (2-7) is large.

A channel bit string modulated by RLL (2-7) in Table 1 has a frequency of occurrence of Tmin
3T, which is the largest, followed by 4T and 5T. Tmin
When 3T is repeated, that is, when edge information frequently occurs in an early cycle, clock regeneration is advantageous.

However, when the recording linear density is further increased, the repetition of the minimum run easily causes distortion in the recording waveform. This is because the waveform output of Tmin is smaller than the others, and is easily affected by, for example, defocus or tangential tilt. Further, when recording at a high linear density, continuous recording of the minimum mark is susceptible to disturbance such as noise, and thus an error is likely to occur during data reproduction. As a pattern of the data reproduction error in this case, there are many cases where the leading edge and the trailing edge of the continuous minimum mark are respectively shifted and erroneous, and as a result, the error propagates from the beginning to the end of the repetition of the minimum run, This means that the length of the generated bit error becomes longer.

As described above, it is effective to limit the continuation of the minimum run as one method of stabilizing data recording and reproduction at a high linear density.

The conversion table of the variable length RML (2-7) code is as follows, for example. The maximum constraint length r is 5, and the maximum constraint length increases as compared with the variable length RLL (2-7) code.

[0015]

The parameter of the variable length RML (2-7) is (2,7; 1,2; 5). If the bit interval of the recording waveform sequence is T, the minimum inversion interval Tmin is 3 (= 2 + 1).
It becomes T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin expressed by (m / n) × 2 is 1.
50 (= (1/2) × 3) Tdata. Also (k +
1) The maximum inversion interval Tmax represented by T is 8T (4.00
Tdata). Further, the detection window width Tw is (m / n) × Td
It is represented by ata, and its value is 0.50 (= １ ／) Tdata. These are the same as the RLL (2-7) codes in Table 1. In Table 2, the repetition of 3T, which is the minimum run, is limited to four times by the continuous replacement code of the minimum run at the constraint length i = 5.

By the way, at the time of recording on a recording medium and transmission of data, coded modulation suitable for each medium (transmission) is performed. DC components included in these modulation codes are, for example, servo signals of a disk drive. Causing fluctuations in various error signals, such as tracking errors in control,
Alternatively, jitter is generated. Therefore, the DC component is
It is better not to include it in the modulation code.

In DSV (Digital Sum Value), a channel bit string is converted to NRZI (that is, level-coded), and a code is added by setting "1" of the bit string (data symbol) to +1 and "0" to -1. Means the sum. DSV is a measure of the DC component of the code string. Decreasing the absolute value of DSV, that is, performing DSV control, suppresses the DC component of the code string.

Here, the variable length RLL (2
-7) Modulation code by table and shown in Table 2,
The modulation code according to the variable length RML (2-7) table is DS
V control is not performed. DSV control in such a case is
This is realized by performing DSV calculation at predetermined intervals in a coded sequence (channel bit sequence) after modulation, and inserting predetermined DSV control bits into the coded sequence (channel bit sequence).

The DSV control bits to be inserted into the channel bit string are determined by the minimum run, and in the case of Tables 1 and 2, d = 2 in both cases. When inserting DSV control bits at arbitrary positions in a codeword so as to keep the minimum run, the required number of bits is 3 channel bits. The number of bits required to insert the DSV control bit at an arbitrary position in the codeword so as to keep the maximum run is 6 channel bits.

Incidentally, the DSV control bits are basically redundant bits. Therefore, considering the efficiency of code conversion,
The smaller the number of DSV control bits, the better.

Further, it is preferable that the minimum run d and the maximum run k do not change depending on the inserted DSV control bit. This is because the change in (d, k) affects the recording / reproducing characteristics.

However, in the actual RLL code, the minimum run is always protected because the minimum run greatly affects the recording / reproducing characteristics.
Maximum runs are not always followed. In some cases, there is a format that uses a pattern that breaks the maximum run as a synchronization signal. For example, DVD (Digital Versatil
The maximum run is 1
It is 1T, but 14T is allowed due to the format. By breaking the maximum run in this way, the ability to detect, for example, a synchronization signal can be significantly increased.

Therefore, in the RLL code with the minimum run d = 2, which is more suitable for higher linear density, the continuity of the minimum run is controlled so as to be more suitable for high linear density, and the DSV control is performed as efficiently as possible. Is important.

In practice, for example, a conventional RLL
(2-7) Basic code parameters (d, k; m, n) =
It is effective to protect (2,7; 1,2) from the viewpoint of utilizing the conventional technology.

Furthermore, the structure should be as simple as possible in consideration of the demodulation error propagation, the synchronization signal should be easy to make,
It is also important to be able to terminate before and after the synchronization signal.

[0027]

As described above, in a disk device having a high linear density, there is a problem that a long error is apt to occur in a continuous pattern of the minimum run when recording and reproducing the RLL code. When DSV control is performed on an RLL code such as an RLL (2-7) code,
DSV at arbitrary intervals in a codeword string (channel bit string)
Control bits must be inserted. Since the DSV control bits are redundant, it is desirable that the DSV control bits be as small as possible. However, if DSV control is performed using a codeword string, at least 3 bits or more are required to keep the minimum run or the maximum run.

The present invention has been made in view of such a situation, and the RLL code (d, k;
m, n) = (2, 7; 1, 2), it is necessary to limit the number of consecutive minimum runs, and to perform complete DSV control with efficient control bits while maintaining the minimum and maximum runs. Aim.

[0029]

According to a first aspect of the present invention, there is provided a modulation apparatus comprising modulation means for limiting the number of consecutive minimum runs to a predetermined number or less and modulating the minimum run.

According to a sixth aspect of the present invention, there is provided a modulation method including a modulation step of performing modulation by limiting the continuation of the minimum run to a predetermined number or less.

According to a seventh aspect of the present invention, there is provided a medium for providing a computer readable program for causing a modulation device to execute a process including a modulation step of performing modulation by limiting the minimum run sequence to a predetermined number or less. It is characterized by.

The demodulating device according to the present invention is characterized in that the demodulating device further comprises a detecting means for detecting a code for limiting the continuation of the minimum run to a predetermined number or less.

A demodulation method according to a ninth aspect of the present invention is characterized in that the demodulation method includes a detection step of detecting a code for limiting the continuation of the minimum run to a predetermined number or less.

According to a tenth aspect of the present invention, there is provided a computer-readable program for causing a demodulation device to execute a process including a detection step of detecting a code for limiting the minimum run continuation to a predetermined number or less. It is characterized by the following.

In the modulation device according to the first aspect, the modulation method according to the sixth aspect, and the providing medium according to the seventh aspect, the modulation is performed with the minimum run continuation limited to a predetermined number or less.

In the demodulation device according to the eighth aspect, the demodulation method according to the ninth aspect, and the providing medium according to the tenth aspect, a code for limiting the continuation of the minimum run to a predetermined number of times or less is detected.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

That is, the modulator according to claim 1 is
A modulation unit (for example, the modulation unit 12 in FIG. 1) for modulating the minimum run continuation to a predetermined number or less is provided.

The demodulating device according to the present invention is characterized in that it comprises a detecting means (for example, the demodulating unit 32 in FIG. 5) for detecting a code for limiting the continuation of the minimum run to a predetermined number or less.

Hereinafter, embodiments of the present invention in a conversion table, a modulation device, a demodulation device, and a synchronization signal according to the present invention will be described with reference to the drawings. In the following, for convenience of explanation, the sequence of “0” and “1” before conversion (data string before conversion) is represented by being separated by (), as in (0000011), and after conversion. Sign "0"
And the sequence of "1" (the last column of the code) is "000100100"
Will be separated by "". Table 3 shown below is a conversion table including a termination table and a synchronization signal pattern for converting data of the present invention into codes.

[0041]

The code according to Table 3 has a minimum run d = 2, a maximum run k = 7, a conversion rate m / n = 1/2, and a variable length structure.

The conversion code with the minimum constraint length i = 2 in the conversion table is composed of two less than the required number of four (2 ^ 2 = 4). That is, when converting a data string, there is a data string (for example, (11) (00)) which cannot be converted only by the constraint length i = 2, which is the minimum unit. After all, in order to convert all data strings using the table of Table 3, that is, in order to be realized as a conversion table, a constraint length i = 4 is required. Codes required for data conversion are called basic codes.

The conversion table in Table 3 has a replacement code for limiting the continuation of the minimum run. That is,
When the data string continues with (00000), sign these
0000 100100 ". In this way, in the code word string after the data conversion, the continuation of the minimum run is limited, and the minimum run repetition is four at the maximum.

Further, the table shown in Table 3 shows that the number of “1” in the element of the data string and the number of “1” in the element of the code word string to be converted are divided by two. However, both have conversion rules such that 1 or 0 is the same. That is, the element (000) of the data string is “1001”
00 ", each of which is" 1 "
Is 0 in the data sequence and 2 in the corresponding codeword sequence.
In each case, the remainder after dividing by 2 is equal to 0. Similarly, the element (1101) of the data string is “000”
0 1000 ", the number of which is" 1 "is that the number of data strings is three and the number of corresponding code words is one. I do.

The code generated by the conversion table in Table 3 has a maximum constraint length r = 5. The conversion code with the constraint length i = 5 is a replacement code for limiting the repetition of the minimum run.

When no replacement code with the constraint length i = 5 is provided, Table 3 shows the maximum constraint length r = 4, and d =
2, code of k = 7 can be created. However, by the conversion into the code having the constraint length i = 5, the continuation of the minimum run is limited to four times, and a code corresponding to the high linear density recording can be obtained.

As described above, in the conversion using the table of Table 3, when the table is constituted only by the basic code, the maximum constraint length r = 4, the minimum run d = 2, the maximum run k = 8, and the data The remainder when dividing the number of "1" in the elements of the sequence by 2 and the "
A code is generated so that the remainder when the number of 1 "is divided by 2 is the same for both 1 and 0. Table 3
In the conversion using the table of (1), when a replacement code for limiting the continuation of the minimum run d is configured in addition to the basic code, the maximum constraint length r = 5 and the minimum run d = 2
, The continuation of the maximum run k = 7 and the minimum run d is limited to a finite number of times, and the remainder when the number of “1” in the elements of the data string is divided by 2 and the code word string to be converted A code is generated such that the remainder obtained by dividing the number of "1" in the element by 2 is the same as either 1 or 0.

In general, as the maximum constraint length r increases, the propagation of demodulation errors during bit shifting (errors caused by shifting the edge bit position by one bit forward or backward from the normal position). The characteristics deteriorate.

When Table 1 and Table 2 are compared, the maximum constraint length r in Table 1 is 4, whereas the maximum constraint length r in Table 2 is 5. However, comparing Table 2 with Table 3 of the present invention, the maximum constraint length r is 5, which is the same. In addition, since there is only one element of the constraint length r = 5 in Tables 2 and 3, the effect is small considering that the number of occurrences is small.

The data sequence is modulated using the conversion table as shown in Table 3, and the modulated channel bit sequence can be subjected to DSV control at predetermined intervals in the same manner as before. However, the processing using the conversion table of Table 3 can perform DSV control more efficiently by making use of the relationship between the data string and the codeword string to be converted.

That is, in the conversion table, the remainder when the number of “1” in the element of the data string and the number of “1” in the element of the code word string to be converted are divided by 2 is both 1
Alternatively, when there is a conversion rule that is the same as 0, it is not possible to insert a DSV control bit of “1” representing “inversion” or “0” representing “non-inversion” in the channel bit. , "1" if "inverted" in the data bit string
However, "non-inversion" is equivalent to sandwiching the DSV control bit of "0".

For example, in Table 3, data conversion 2
When the bit continues with (00), the DSV
With the control bit interposed, the data conversion is (00-y) (y
Is 1 bit and is 0 or 1). Here, if “0” is given to y, the conversion table of Table 3 becomes data code 000 1001 00, and if “1” is given, it becomes data code 001 0010 00.

When the code word string is NRZI-coded and level-encoded, these become the data code level code (previous level L (0)) 000 1001 00 111000 001 0010 00 001111, and the last 3 in the level code string. Bits are inverted. That is, by selecting "1" and "0" of the DSV control bit y, DSV control can be performed in the data string.

Considering the redundancy by the DSV control, performing the DSV control with one bit in the data string is represented by the conversion rate m = 1 and n = 2 in Table 3 in terms of the channel bit string.
This is equivalent to performing DSV control with two channel bits. Here, for example, in order to perform DSV control in the (2-7) tables such as Table 1 and Table 2, DSV control must be performed in a channel bit string, and in order to keep the minimum run, at least three channel bits must be used. Required and the redundancy is greater. By performing DSV control within the data string as in this method, efficient DSV
Control can be realized.

One embodiment of the modulation device according to the present invention will be described with reference to the drawings. In this embodiment, the data sequence is represented by the variable length code (d, k; m, n; r) = (2, 7;
1, 2; 5).

FIG. 1 is a block diagram showing the configuration of an embodiment of the modulation device according to the present invention. DSV bit determination
The insertion unit 11 first performs DSV control on the input data sequence at an arbitrary interval, determines “1” or “0” of the DSV control bit, inserts it at an arbitrary interval, and outputs the DSV-controlled data. The column is supplied to the modulator 12. Modulating section 12 modulates the data string into which the DSV control bits have been inserted, and supplies the obtained code string to NRZI generating section 13. The NRZI conversion unit 13 performs NRZI modulation on the code sequence and converts the code sequence into a recording waveform sequence. The timing management unit 14 generates a timing signal, and determines a DSV bit.
The information is supplied to the insertion unit 11, the modulation unit 12, and the NRZI conversion unit 13, and the timing is managed.

FIG. 2 shows the DSV of the DSV bit determination / insertion unit 11.
FIG. 9 is a diagram for explaining control bit determination / insertion processing. DSV
The determination and insertion of control bits are performed at arbitrary intervals in the data string. As shown in FIG. 2, first, DATA1 and DATA2
In order to insert the DSV control bit during the period, the DSV bit determination / insertion unit 11 calculates the integrated DSV up to DATA1. Further, the DSV bit determination / insertion unit 11 calculates the section DSV in the next section DATA2. The DSV value is obtained by converting each of DATA1 and DATA2 into a channel bit string, and further level-encoding (NRZI-converting) and integrating the level H as +1 and the level L as -1. Inserted
The DSV control bit indicates that the integrated DSV value up to DATA1
Are determined so that the absolute value approaches "zero".

When "1" is given as a DSV control bit to "x1" in FIG. 2, the section DATA2 after DATA1 is inverted, and when "0" is given, the section after DATA1 is inverted. Indicates that DATA2 is not inverted. Because the number of elements in each table of Table 3 is “1” in the elements of the data string and the number of “1” in the elements of the codeword string to be converted is:
Since the remainder when divided by 2 matches both 1 and 0, "1"
This means that "1" meaning "inversion" is also inserted into the code word string to be converted thereafter.

After “x1” in FIG. 2 has been determined in this way, the DSV bit is determined at a predetermined data interval.
The insertion unit 11 similarly performs DSV control at “x2”. The integrated DSV value at that time is DATA1, x1, and DA1.
All DSV values up to TA2.

Then, as shown in FIG. 2, a DSV control bit is inserted in the data sequence in advance, and thereafter,
The modulator 12 performs modulation and generates a channel bit sequence.

FIG. 3 is a block diagram showing a configuration example of the modulation section 12. The shift register 21 shifts the data one bit at a time, while the constraint length determination unit 22, the minimum run continuation restriction code detection unit 23, and the conversion units 24-1 to 24-2.
4-4. The shift register 21 also allows the constraint length determination unit 22, the minimum run continuation restriction code detection unit 23, and the conversion units 24-1 to 24-4 to refer to data of the number of bits necessary for converting the data. Store the data.

The constraint length judging unit 22 judges the constraint length i of the data and outputs it to the multiplexer 25. When detecting a code for limiting the number of consecutive minimum runs,
The signal is output to the constraint length determination unit 22.

When the dedicated code is detected by the minimum run continuation restriction code detecting unit 23, the constraint length determining unit 22
The predetermined constraint length is output to the multiplexer 25. At this time, the constraint length determination unit 22 may determine another constraint length, but if there is an output by a dedicated code from the minimum run continuation restriction code detection unit 23, the constraint length is given priority and the constraint length is determined. decide. In other words, the constraint length determination unit 22
The longer constraint length is selected and determined.

The conversion units 24-1 to 24-4 refer to the built-in conversion table, determine whether a conversion rule corresponding to the supplied data is registered, and determine that the conversion rule is registered. In this case, after the data is converted, the converted code is output to the multiplexer 25. If it is determined that the data is not registered in the conversion table, the conversion units 24-1 to 24-4
-4 discards the supplied data.

FIG. 3 is an example corresponding to Table 3, so that
Although the conversion unit is assumed to be a 5-10 conversion, when the maximum constraint length is r, the modulation unit has a conversion unit up to 24−r.

The multiplexer 25 includes a constraint length determining unit 22
The conversion unit 24-i corresponding to the supplied constraint length i receives the converted code, and outputs the code via the buffer 26 as serial data.

Next, the operation of the modulation section 12 will be described.

First, the data is sent from the shift register 21 to each of the conversion units 24-1 to 24-4 and the constraint length determination unit 2
2, the minimum continuous limit code detection unit 23,
It is supplied to the maximum run compensation code detector 24. The data is supplied by the number of bits required for each determination.

The constraint length judging section 22 incorporates, for example, a conversion table shown in Table 3 and judges the constraint length i of the data with reference to this conversion table, and outputs the judgment result (constraint length i) to the multiplexer 25. I do.

Then, the minimum run continuation restriction code detecting section 2
Reference numeral 3 denotes a replacement code (in the case of Table 3, data (00
000) is converted, a code for restricting the continuation of the minimum run is detected with reference to the conversion table, and a predetermined detection signal is output to the constraint length determination unit 22.

When there is a detection signal from the minimum run continuation restriction code detecting unit 23, the constraint length judging unit 22 determines whether or not the constraint length judging unit 22 itself judges another constraint length. Is not selected, and the minimum run continuous restriction code detection unit 2 is selected.
3 is output to the multiplexer 25. That is, the output from the minimum run continuation restriction code detection unit 23,
If the result of the constraint length determination unit 22 is different, the one with the larger constraint length is selected.

FIG. 4 is a diagram for explaining the processing of the constraint length determination unit 22 and the minimum run continuation restriction code detection unit 23. The minimum run continuation restriction code detecting unit 23 has a conversion part of (00000) in the table shown in Table 3, and when the input 5-bit data matches this, the constraint length =
The detection signal shown in FIG. The constraint length determination unit 22 has a built-in table shown in Table 3, and the four bits of the input data are (1101) or (1100).
Is determined, it is determined that the constraint length = 4. The constraint length determination unit 22 determines that three bits of the input data are (0
01), (000) or (111), it is determined that the constraint length = 3. Further, when two bits of the input data match either (10) or (01), the constraint length determination unit 22 determines that the constraint length = 2.
Is determined.

When the input data string is, for example, (000000), the constraint length determination unit 22
Determines that the constraint length = 3. However, in the first 5 bits, the minimum run continuation restriction code detecting unit 23 sets (00
000) is detected, and it is determined that the constraint length = 5. In such a case, the output signal from the minimum run continuation restriction code detection unit 23 is selected, and the constraint length determination unit 22 determines that the constraint length = 5.

As described above, the constraint length determining unit 22 refers to the maximum constraint length of 5 bits according to the table of Table 3 and
The constraint length of all data strings consisting of "1" and "0" is determined.

The constraint length judging section 22 outputs the constraint length i thus determined to the multiplexer 25.

The constraint length determination process of the constraint length determining unit 22 is performed in the order of smaller constraint lengths in addition to the process shown in FIG.
= 1, i = 2, i = 3, i = 4. At this time, the determination of the constraint length is performed in the same manner.

Referring back to FIG. 3, the conversion units 24-1 to 24-4
Has a table corresponding to each constraint length i,
When a conversion rule corresponding to the supplied data is registered in the table, the supplied i-bit data is converted into a 2 × i-bit code using the conversion rule.
The code is output to the multiplexer 25.

The multiplexer 25 includes a constraint length determining unit 22
The code is received from the conversion unit 24-i corresponding to the supplied constraint length i, and the code is output as serial data via the buffer 26.

Here, for example, it is assumed that there is no conversion code in the conversion table of Table 3 that restricts the repetition of the minimum run with the constraint length r = 5. At this time, if (000000000000000) is input as data,
The data string is (000) (000) (000) (0
00) (000) ... is converted in units of "100100-
100 100-100 100-100 100-100
A code word string (channel bit string) of 100 ″ is generated.
When the signal is converted into a level code by performing the conversion, the signal becomes a signal whose logic is inverted at the timing of “1”. Therefore, this code word string is “111000 111 000 111
000 111 000 11 000 ", and the minimum inversion interval of 3T is long and continuous. Such a recording code string is liable to cause an error during recording and reproduction at a high linear density.

Thus, in the conversion table of Table 3,
Given a conversion code that limits the repetition of the minimum run,
The data string of (00000000000000) is converted in data string units of (00000), (0000) and (0000), and the code string is “000010”.
0100-0000100100-0000001010
0 ", thereby preventing the occurrence of a continuous minimum run of minimum runs. This means that a pattern that is likely to cause an error is removed during recording and reproduction at a high linear density. Even when the replacement conversion is performed, the minimum run and the maximum run are maintained.

By the way, the order of arrangement may be different within each constraint length of the data string and the code word string in Table 3.
For example, in Table 3 where the constraint length i = 2, Is an array like It may be.

Also in this case, the number of "1" in the element of the data string and the number of "1" in the element of the code word string are both equal to 1 or 0 when the remainder is divided by 2.

Table 4 below shows another conversion table obtained by rearranging Table 3. Corresponding parameters and modulators can be made as in Table 3. In any case, as for the constraint length, i = 5 is used to limit the repetition of the minimum run, so that the maximum constraint length is at least r = 5.

<Table 4> 27PP-part.II (d, k; m, n; r) = (2,7; 1,2; 5) 10 1000 01 0100 111 000 100 110 100 100 001 001000 0001 00001000 0000 00100100 11011 0000100100

Next, an embodiment of the demodulation device according to the present invention will be described with reference to the drawings. In this embodiment, a modulation codeword string obtained by converting a data string into a variable length code (d, k; m, n; r) = (2, 7, 1, 2, 5) using the conversion table of Table 3 This is applied to a demodulation device for demodulating the signal. FIG. 5 is a block diagram illustrating a configuration of an embodiment of a demodulation device using an inverse conversion table corresponding to the conversion table in Table 3. FIG. 6 is a block diagram illustrating a specific configuration example of the comparison / inverse NRZI conversion unit 31 and the demodulation unit 32. FIG. 7 is a diagram illustrating the processing of the constraint length determination unit 41 and the minimum run continuation restriction code detection unit 42. FIG. 8 is a flowchart illustrating the process of the DSV bit extracting unit 33.

The comparing / inverse NRZI conversion section 31 compares the signal transmitted from the transmission line or the signal reproduced from the recording medium, further converts the signal into an inverse NRZI (converts the signal into an edge code), and outputs the signal to the demodulation section 32. It is made to supply. The demodulation unit 32 demodulates the signal supplied from the comparison / inverse NRZI conversion unit 31 based on a demodulation table (inverse conversion table), and supplies the demodulated signal to the DSV bit extraction unit 33. The DSV bit extracting unit 33 further removes the DSV control bits included in the data sequence inserted at an arbitrary interval from the demodulated data sequence, gives the original data sequence, and outputs the same to the buffer 34. The buffer 34 temporarily stores the input serial data, reads out the serial data at a predetermined transfer rate, and outputs the read serial data. The timing management unit 35 generates a timing signal, and divides the timing signal into a comparison / inverse NRZI conversion unit 31, a demodulation unit 32, and a DSV bit extraction unit 3.
3 and the buffer 34 to manage the timing.

The constraint length judging section 41 calculates the comparison / inverse NR
The signal digitized by the ZI conversion unit 31 is input, and the constraint length i is determined. Minimum run continuation restriction code detection unit 42
Detects a dedicated code given to limit the continuation of the minimum run from the input of the signal digitized by the comparator / inverse NRZI conversion unit 31 and supplies the information to the constraint length determination unit 41 .

The inverse transform units 43-1 to 43-4 are provided as n × i
It has a table for converting bit variable-length codes into m × i-bit data in reverse (parts corresponding to i = 2 to 5 in the conversion table in Table 3). The multiplexer 44 switches and selects the data from the inverse converter 43-i, and outputs the data as serial data.

Next, the processing of the comparator / inverse NRZI generator 31 and the demodulator 32 shown in FIG. 6 will be described.

The signal transmitted from the transmission line or the signal reproduced from the recording medium is a signal obtained by comparing / inverting the NRZI signal.
Is input to the conversion unit 31 and compared,
A digital signal of an NRZI code (“1” indicates an edge) is input to the constraint length determination unit 41. The constraint length determination unit 41 performs a constraint length determination process, and outputs a determination result (constraint length) to the multiplexer 44. The constraint length determination unit 41 has a conversion table (inverse conversion table) shown in Table 3.

The digital signal output from the comparator / inverse NRZI conversion section 31 is output to the minimum run continuous restriction code detection section 4.
2 is detected by the minimum run continuation restriction code detecting section 42 and a dedicated pattern provided for restricting the continuation of the minimum run is detected.
Is output to The minimum run continuation restriction code detection unit 42
A replacement code for limiting the continuation of the minimum run in the conversion table shown in Table 3 (in the case of Table 3, the codeword “0000”
100100 "is converted, a code for limiting the continuation of the minimum run is detected with reference to the inverse conversion table, and a predetermined detection signal is output to the constraint length determination unit 41.

That is, the constraint length determination unit 41 and the minimum run continuation restriction code detection unit 42 have the table of Table 3 divided.

FIG. 7 is a diagram for explaining a specific example of the operation of the constraint length determination unit 41 and the minimum run continuation restriction code detection unit 42. The minimum run continuation restriction code detection unit 42 is as shown in Table 3
When the input 10-bit code word string matches the inverse conversion part of "0000-1001-00" in the table shown in FIG. 41. The constraint length determination unit 41 has a built-in inverse conversion table shown in Table 3, in which 8 bits of the input code word string are set to “0000 1000” or “001”.
0 0100 ", the constraint length i =
4 is determined. If this is not the case, the 6 bits of the input codeword string are “0010 00”, “100
If it matches either “100” or “0001 00”, the constraint length determination unit 41 determines that the constraint length i = 3.If this is not the case, the 4 bits of the input codeword string are If it matches either “1000” or “0100”, the constraint length determination unit 41 determines that the constraint length i = 2.

The constraint length determination process of the constraint length determination unit 41 and the minimum run continuation restriction code detection unit 42 is performed in the order shown in FIG. 7 in addition to i = 1, i = 2, i =
3, and i = 4. At this time, the determination of the constraint length is similarly performed.

On the other hand, in the inverse conversion section 43-1, the address "
The data (10) is stored in the address “0100” in “1000”.
Is written with data (01). Hereinafter, similarly, the corresponding data is written in the inverse conversion units 43-2 to 43-4 in the same manner, and the supplied 2 × i
The bit codeword string is converted into an i-bit data string, and the data string is output to the multiplexer 44.

The multiplexer 44 includes an inverse converter 43-i.
The supplied data is selected according to the result of the constraint length determination by the constraint length determination unit 41, and is output as serial data.

The inverse conversion table is, for example, as shown in Table 5 below.

[0099]

In the data string obtained from the demodulation unit 32, DSV control bits are interposed at arbitrary data bit intervals. The DSV bit extracting section 33 has an internal counter,
To extract the SV control bit, for example, turn the counter,
The output is not performed at an arbitrary data interval, and is output at other times.

FIG. 8 is a flowchart for explaining the processing of the DSV bit extracting section 33. In step S11, the DSV bit extracting section 33 counts the data sequence obtained from the demodulation section 32. In step S12, DS
The V bit extracting unit 33 determines whether or not the data interval is an arbitrary data interval (the count value is a value corresponding to the interval).
If it is determined that the data interval is not an arbitrary data interval, step S
At 13, a data string is output. In step S14, the DSV bit extracting unit 33 performs a process of sequentially transmitting data.

In step S15, the DSV bit extracting section 33 determines whether or not the code has been completed. If it is determined that the code has not been completed, the procedure proceeds to step S11.
And the processing is continued.

If it is determined in step S12 that the data interval is an arbitrary data interval (the count value is a value corresponding to the interval), the DSV bit extracting unit 33 proceeds to step S1.
Skip to step S3 and proceed to step S14.

If it is determined in step S15 that all codes have been demodulated, the process ends.

The result of simulating the modulation using the above conversion table is shown. That is, the result of modulating a data string in which the continuation of Tmin is limited and a DSV control bit is inserted in the data string will be described below. The simulation is performed using a conversion table as a conventional table 1
And Table 2 and Table 3 which is this method were used.

A codeword string (channel bit string) was generated by using the conversion table shown in Table 1, Table 2, or Table 3 based on arbitrarily created 13107200-bit random data. In Table 3, in particular, DSV control was performed every 51 data bits, and conversion was performed after inserting DSV control bits. At this time, the redundancy is 1 / (1 + 51) =
1.92% 2cbit / (2cbit + 102cbit) = 1.92%.

Since the DSV control cannot be performed according to Tables 1 and 2 as shown in Table 3, after generating a code word string, a DSV control bit is inserted at a predetermined interval in the code rear row. There must be. If the conventional DSV control is performed on the channel bits when the redundancy is set to 1.92%, which is the same as the above, at least three channel bits must be interposed in order to keep the minimum run. 3cbit + Acbit) = 1.92%, that is, A = 153cbit.

With the same redundancy, when DSV control is performed using channel bits, three DSV bits are interposed every 153 channel bits, and low-frequency components are not suppressed more than when control is performed for every 102 channel bits according to the present method.

The numerical values shown in the results were calculated as follows. Ren_cnt [1 to 10]: Number of occurrences of 1 to 10 repetitions of the minimum run. T_size [2 to 9]: Number of occurrences of each run from 2T to 9T. Sum: Number of bits. Total number of bits. Total: Number of runlengths. Each run (3T, 4T,
...) Total number of occurrences Average Run: (Sum / Total) Numerical value of run distribution: (T_size [i] * (i)
) / (Sum), i = 2,3,4 ,,,
10 Numerical value of continuous distribution of minimum run: (Ren_cnt [i] * (i)) / T_s
size [3T], i = 1,2,3,4,, 1,1
0 max-RMTR: the maximum number of repetitions of the minimum run. peak DSV: The DSV control of the channel bit string refers to a difference between when “1” is high and “0” is low after NRZI conversion, and a peak on the plus side and a peak on the minus side of the DSV value. The distance from High to Low of the peak DSV is DSV
The control performance is shown, and the lower the distance, the more the low-frequency component is suppressed.

<Table 6> *** PP27 *** <Table.3> <Table.2> <Table.1> PP27 RML27 RLL27 Average Run 4.5341 4.5335 4.4215 Sum 26214400 26214376 26214376 Total 5781636 5782412 5928875 2T 0 (- ----) 0 (------) 0 (------) 3T 1820683 (20.84%) 1822690 (20.86%) 1988204 (22.75%) 4T 1462138 (22.31%) 1461449 (22.30%) 1520669 (23.20%) 5T 1011173 (19.29%) 1011117 (19.29%) 1073988 (20.48%) 6T 764815 (17.51%) 765108 (17.51%) 761370 (17.43%) 7T 523572 (13.98%) 522107 (13.94%) 448224 11.97%) 8T 199 255 (6.08%) 199941 (6.10%) 136 420 (4.16%) 9T 0 (------) 0 (------) 0 (------) 10T 0 ( ------) 0 (------) 0 (------) RMTR (1) 902333 (49.56%) 905469 (49.68%) 833485 (41.92%) RMTR (2) 298756 ( 32.82%) 298 611 (32.77%) 292795 (29.45%) RMTR (3) 87590 (14.43%) 87549 (14.41%) 103838 (15.67%) RMTR (4) 14517 (3.19%) 14338 (3.15%) 36510 (7.35% ) RMTR (5) 0 (------) 0 (------) 13112 (3.30%) RMTR (6) 0 (------) 0 (------) 4536 (1.37%) RMTR (7) 1614 (0.57%) RMTR (8) 555 (0.22%) RMTR (9) 203 (0.09%) RMTR (10) 79 (0.04%) max-RMTR 4 4 17 === =========================== =============================== peak DSV High-peak +38 +5900 +5688 Low-peak -38 -1164- 1128 ("#": 51data-bit + 1dc-bit, 1.92%) ================================== =============================

The results in Table 6 show that the codes using the conversion table in Table 3 according to the present invention are protected from the minimum run and the maximum run.
In addition, it is shown that the continuation of the minimum run is limited to a maximum of four times. Also, the results of peak DSV indicated that DSV control within the data sequence of the present invention was performed. Further, although not shown in the above results, since the efficiency of DSV control is high, when performing DSV control with the same redundancy of 1.92%, the code using the conversion table in Table 3 is placed every 102 codewords. While the DSV control can be performed, the code using the conversion table of Table 1 or Table 2 is placed every 153 code words.
This is equivalent to performing DSV control. As a result, with the code using the conversion table of Table 3, the width of the peak DSV value can be reduced, and lower frequency components can be suppressed.

As described above, in comparison with the conventional RLL (2-7) system, the 27PP system can limit the repetition of the minimum run to at most four times, so that the error characteristic at high linear density can be improved. Can be expected. In addition, since the 27PP system has high DSV control efficiency, when DSV control is performed with the same redundancy, low-frequency components can be suppressed even more than in the past, and stable data recording and reproduction can be performed.

In summary, in the conversion table having the minimum run d = 2, the maximum run k = 7, and the conversion rate m / n = 1/2, there is a replacement code for limiting the number of repetitions of the minimum run length. 2.) The recording / reproducing at a high linear density and the tolerance for tangential tilt are improved. (2) The portion where the signal level is low decreases, and AGC and PL
Accuracy of waveform processing such as L can be improved, and overall characteristics can be improved.

Also, the number of “1” in the element of the conversion table and the number of “0” in the element of the code word string to be converted are:
Since the remainder when divided by 2 is set to match either 1 or 0, (3) redundant bits for DSV control can be reduced. (4) For the minimum run d = 2 and (m, n) = (1,2), 2
This can be done with codewords. (5) The minimum run and the maximum run can be kept with little redundancy.

In this specification, a system is defined as
It is assumed that the device as a whole is constituted by a plurality of devices.

[0116] Examples of a providing medium for providing a user with a computer program for performing the above-described processing include:
In addition to recording media such as magnetic disks, CD-ROMs, and solid-state memories, communication media such as networks and satellites can be used.

[0117]

According to the modulation device of the first aspect, the modulation method of the sixth aspect, and the providing medium of the seventh aspect, the modulation is performed by limiting the continuation of the minimum run to a predetermined number or less. As a result, the number of consecutive minimum runs can be limited.

According to the demodulation device of the eighth aspect, the demodulation method of the ninth aspect, and the providing medium of the tenth aspect, a code that limits the continuation of the minimum run to a predetermined number or less is detected. As a result, the number of consecutive minimum runs can be limited.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a modulation device.

FIG. 2 is a diagram for explaining processing of DSV control bit determination / insertion by a DSV bit determination / insertion unit 11;

FIG. 3 is a block diagram illustrating a configuration example of a modulation unit 12.

FIG. 4 is a diagram for explaining processing of a constraint length determination unit 22 and a minimum run continuation restriction code detection unit 23;

FIG. 5 is a block diagram illustrating a configuration of an embodiment of a demodulation device.

FIG. 6 shows a comparator / inverse NRZI generator 31 and a demodulator 3
FIG. 9 is a diagram for explaining the process 2;

FIG. 7 is a diagram illustrating a specific example of an operation of a constraint length determination unit 41 and a minimum run continuation restriction code detection unit 42.

FIG. 8 is a flowchart illustrating a process of a DSV bit extracting unit 33;

[Description of Code] 11 DSV bit determination / insertion unit, 12 modulation unit, 1
3 NRZI generator, 31 comparator / inverse NRZI generator, 3
2 Demodulation unit, 33 DSV bit extraction unit

Claims (10)

[Claims] 1. A variable length code (d, d) having a basic data length of 1 bit and a minimum run of 2 and a basic code length of 2 bits.
A modulating device for modulating (k; m, n; r), comprising: a modulating means for modulating by limiting the continuation of the minimum run to a predetermined number or less. 2. The variable-length code has a remainder obtained by dividing the number of “1” in the data string by 2 and a remainder obtained by dividing the number of “1” in the codeword string to be converted by 2. The modulation device according to claim 1, wherein the modulation codes are the same. 3. The modulation device according to claim 1, wherein the continuation of the minimum run is limited to four times. 4. The modulation device according to claim 1, wherein DSV control is performed before performing the modulation. 5. The modulator according to claim 1, wherein the maximum constraint length is at least 5. 6. A variable length code (d, d) having a basic data length of 1 bit and a minimum run of 2 and a basic code length of 2 bits.
k; m, n; r), wherein the modulation method includes a modulation step of limiting the continuation of the minimum run to a predetermined number or less and performing modulation. 7. A variable length code (d, d) having a basic data length of 1 bit and a minimum run of 2 and a basic code length of 2 bits.
k; m, n; r), to provide a computer readable program for executing a process including a modulation step of limiting and modulating the continuation of the minimum run to a predetermined number or less of the minimum run. Providing medium characterized. 8. A demodulator for demodulating a variable length code (d, k; m, n; r) having a minimum run of 2 and a basic code length of 2 bits into data having a basic data length of 1 bit. A demodulation apparatus comprising: a detection unit that detects a code that limits the continuation of the minimum run to a predetermined number of times or less. 9. A demodulation method for demodulating a variable length code (d, k; m, n; r) having a minimum run of 2 and a basic code length of 2 bits into data having a basic data length of 1 bit. A demodulation method, comprising: a detection step of detecting a code for limiting the continuation of the minimum run to a predetermined number or less. 10. A demodulator for demodulating a variable length code (d, k; m, n; r) having a minimum run of 2 and a basic code length of 2 bits into data having a basic data length of 1 bit, A providing medium for providing a computer-readable program for executing a process including a detecting step of detecting a code for limiting a continuous minimum run to a predetermined number or less.