JP2001144621A - Code conversion method and code converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a code conversion method and a code converter that can encode data so as to record the data with high density to a recording medium such as an optical disk. SOLUTION: The code converter converts data by using a conversion table that is used to convert input data whose one word is M (M is a natural number) bits into an NRZ code word whose one word is N (N is a natural number) bits and whose run length is limited. K-kinds of conversion tables are prepared, where the run length of a front end and a tail end of a code word is a half of a minimum value of the run length limit or over, and whose own code words are (L/K)×2M sets (L is a number being 1 or over and K is a natural number) or over. One of the conversion tables is selected and used in a way that a different conversion table is used in a different state before the transition to the same state in response to a state depending on a characteristics value of each code word from P words-preceding word (P is an integer being 2 or over) to one word-preceding word.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a modulation / demodulation technique for a run-length limited code (hereinafter referred to as an RLL code) in digital information recording.

[0002]

2. Description of the Related Art A reproduction signal from an optical disk or the like generally has a characteristic that the higher the frequency of the signal, the smaller the amplitude and the relative C / N ratio deteriorates. This becomes more remarkable as the recording density increases. come. Also, for example, PWM (pulse)
When performing e-width modulation) recording, the mark width must be accurately recorded, but as the recording density increases, it becomes more difficult to record with the accuracy of the detection window width. Further, when the power density of the code is high, the envelope of the reproduced signal is rapidly disturbed because the reproducing circuit cuts off the low frequency band, so that it is impossible to binarize and reproduce the data accurately. These are considered to be the causes of errors during reproduction.

In order to minimize the use of high-frequency signals and to increase the width of a detection window, particularly in an optical disc, a run length limit (RLL) is used.
d) Signs have been used. Further, control has been performed to reduce the power of the code.

For example, in an 8/16 recording code, if the interval between binary bits is T, the minimum mark width is 1.5T,
The detection window width is 0.5T, and the minimum mark width is larger than the binary bit interval T. Also, RL
Most of the conversion tables used for L codes are DSV
(Digital sum value) is configured to have a small absolute value.

[0005]

In recent years, with the digitization of AV equipment, there has been an increasing demand for increasing the recording capacity of recording media. Accordingly, demands for high-density recording on optical disks have been increasing. However,
Since the amplitude of the reproduction signal becomes smaller in the high frequency range, the rate of errors in the reproduction data increases as the recording density of the optical disk increases. In the final stage of the reproduction process, E
Error correction using a CC (error correction code) is also performed, but if an error exceeding the correction capability is included in the reproduced data, the data cannot be correctly reproduced.

An object of the present invention is to provide a code conversion method and a code conversion device for performing coding so that data can be recorded on a recording medium such as an optical disk with higher density.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is that one word is M
(M is a natural number) input data of 1 bit is N (N
Is a natural number) bit run-length limited NRZ (no
n return to zero) a code conversion method using a conversion table for converting into a code word, wherein a run length of a front end and a rear end of the code word is equal to or more than a half of a minimum value of a run length limit. (L / K) × 2 ^M (L is a number greater than 1 and K is a natural number)
Using K types of conversion tables configured as described above, the state transits to the same state according to the state determined by the characteristic value of each code word from P (P is an integer of 2 or more) words to one word before. One of the conversion tables may be used to use different conversion tables in different previous states.
One of them is used.

According to the first aspect of the present invention, the convolutional code has a constraint length without changing parameters that affect the recording density, such as the minimum value of the run-length limit and the detection window width. A correction capability can be provided to reduce random errors.

In the invention of claim 2, one word is M-bit.
The input data of the bit is a run length of 1 bit for N words.
Using a conversion table to convert to a restricted NRZ codeword
Code conversion method, comprising: a front end and a rear end of the code word.
Run length is half of the minimum run length limit
Is one or more, and codewords that only the conversion table has
(L / K) × 2^MConversion cards configured to have more than
Table as the main table, the front end or the rear end of the codeword
Run length is half of the minimum run length limit
Is less than 1 and the codeword that only the conversion table has
(L / K) × 2 ^MConversion cards configured to have more than
Table as a sub-table, the main table and the sub-table
Use K sets of conversion tables with bulls and P words before
In the state determined by the characteristic value of each code word up to one word before
Corresponding to different states before transitioning to the same state
Uses a different set of conversion tables.
Select and use one of the sets of
Connect the codeword obtained by the previous word with the codeword one word before
Run length of the connection part is limited by the run length
In the case of not less than the minimum value of
The codeword and the codeword obtained from the sub-table
The code word in which the absolute value of the integrated value of DSV becomes smaller is
It is a converted output.

According to the second aspect of the present invention, when the run-length limit of the connection portion is satisfied, the codeword of the sub-table can be selected. Can be increased, or the integrated value of DSV can be decreased.

Further, according to a third aspect of the present invention, in the code conversion method according to the first or second aspect, the characteristic value of the codeword is obtained by converting the codeword into a non-return to zero inv.
erted) is the weight of the codeword obtained by the conversion.

According to the third aspect of the present invention, the state can be changed according to the weight of the codeword after the NRZI conversion, and the conversion table can be selected.

According to a fourth aspect of the present invention, in the code conversion method according to the third aspect, the conversion table stores the NRZ so that the value of a specific bit of the input data corresponds to the oddness or evenness of the weight. Characteristically, the codeword is mapped.

According to the present invention, it is not necessary to calculate the weight of the code word.

According to a fifth aspect of the present invention, in the code conversion method according to the first or second aspect, the characteristic value of the code word is the D value of the code word obtained by performing NRZI conversion on the code word.
It is characterized by the value of SV.

According to the fifth aspect of the present invention, the state can be changed by the DSV of the codeword after the NRZI conversion, and the conversion table can be selected.

According to a sixth aspect of the present invention, in the code conversion method according to the fifth aspect, in the conversion table, a value of a specific bit of the input data corresponds to a value of a specific bit of the DSV. Thus, the NRZ codeword is mapped.

According to the sixth aspect of the present invention, the code word DSV
Does not need to be calculated.

According to a seventh aspect of the present invention, in the code conversion device, one word is input data of M bits and one word is input data of N bits.
7 is a conversion table for converting an NRZ code word having a run length limit of bits into bits, wherein the run length at the front end and the rear end of the code word is one half of the minimum value of the run length limit.
As described above, K types of conversion tables configured to have (L / K) × 2 ^M or more code words only in the conversion table are incorporated, and the input data is converted into NRZ code words using these conversion tables. RO to convert to and output
M (read-only memory) and the NRZ codeword
An NRZI conversion circuit that converts the NRZI code word to an output, a weight calculation unit that calculates and outputs the weight of the NRZI code word, and a latch that latches the weight of the NRZI code word, and the weight of the NRZI code word one word before. And a first flip-flop that outputs the NR in synchronization with the input clock and the NR one word before.
A second flip-flop for latching the weight of the ZI code word and outputting the weight of the NRZI code word two words before in synchronization with the input clock;
And selecting one of the conversion tables based on the output of the flip-flop and the output of the second flip-flop.

According to the seventh aspect of the present invention, the convolutional code has a constraint length without changing parameters that affect the recording density, such as the minimum value of the run-length limit and the detection window width. A correction capability can be provided to reduce random errors. The state can be changed according to the weight of the codeword after the NRZI conversion, and the conversion table can be selected.

According to an eighth aspect of the present invention, in the code conversion apparatus, one word is input data of M bits and one word is input data of N bits.
7 is a conversion table for converting an NRZ code word having a run length limit of bits into bits, wherein the run length at the front end and the rear end of the code word is one half of the minimum value of the run length limit.
As described above, K types of conversion tables configured to have (L / K) × 2 ^M or more code words only in the conversion table are incorporated, and the input data is converted into NRZ code words using these conversion tables. RO to convert to and output
M, an NRZI conversion circuit that converts the NRZ code word into an NRZI code word and outputs the converted NRZ code word,
DSV calculating means for calculating and outputting V;
The DSV of the ZI code word is latched, and the NRZI one word before is latched.
First to output the codeword DSV in synchronization with the input clock
And a second flip-flop that latches the DSV of the NRZI codeword one word before and outputs the DSV of the NRZI codeword two words before in synchronization with the input clock. , One of the conversion tables is selected and used based on the output of the first flip-flop and the output of the second flip-flop.

According to the eighth aspect of the present invention, the state can be changed by the DSV of the codeword after the NRZI conversion, and the conversion table can be selected.

According to a ninth aspect of the present invention, in the code conversion apparatus, one word is M bits of input data and one word is N bits.
7 is a conversion table for converting an NRZ code word having a run length limit of bits into bits, wherein the run length at the front end and the rear end of the code word is one half of the minimum value of the run length limit.
That is, the conversion table has only (L / K) × 2 ^M or more codewords, and the value of a specific bit of input data and the weight of a codeword obtained by performing NRZI conversion on the codeword A modulation ROM that incorporates K types of conversion tables configured to correspond to the value of a particular bit of odd or even or DSV, converts input data into an NRZ code word using these conversion tables, and outputs An NRZI conversion circuit that converts the NRZ code word into an NRZI code word and outputs the same; latches a value of a specific bit of input data; and synchronizes a value of a specific bit of input data one word before, in synchronization with an input clock. A first flip-flop for outputting, and a value of a specific bit of the input data one word before, latched,
A second flip-flop for outputting a value of a specific bit of input data before a word in synchronization with an input clock, wherein the modulation ROM includes an output of the first flip-flop and a second flip-flop. And selects and uses one of the conversion tables based on the output.

According to the ninth aspect, it is not necessary to calculate the weight or the DSV of the code word.

According to a tenth aspect of the present invention, there is provided a conversion table as a code conversion apparatus for converting input data of one word of M bits into an NRZ code word of one bit of N bits with run-length limited. The run length at the front end and the rear end of the word is at least half the minimum value of the run length limit, and at least (L / K) × 2 ^M code words included in the conversion table alone are provided. , K types of conversion tables configured so as to correspond to the specific bit values of the code words and the odd / even weights of the code words obtained by performing the NRZI conversion on the code words are incorporated as main tables, and these conversion tables are used. A main table modulation ROM for converting input data into an NRZ code word and outputting the same, and a run length at the front end or the rear end of the code word is the minimum value of the run length limit of 2
Less than 1 / (L / K) × 2 ^M or more codewords possessed only by the conversion table, and a specific bit value of input data and a codeword obtained by performing NRZI conversion on the codeword A sub-table modulation ROM that incorporates K types of conversion tables configured to correspond to odd and even weights as sub-tables, converts input data into NRZ code words using these conversion tables, and outputs the converted data. A main table NRZI conversion circuit for converting an NRZ codeword output from the main table modulation ROM into an NRZI codeword and outputting the same; and a sub-table for converting the NRZ codeword output from the sub-table modulation ROM into an NRZI codeword and outputting the same. NRZI conversion circuit and NRZ output from the main table NRZI conversion circuit
Main table DSV for calculating and outputting DSV of I code word
An arithmetic circuit, a sub-table DSV arithmetic circuit for calculating and outputting the DSV of the NRZI code word output from the sub-table NRZI conversion circuit, and an NRZI code word output from the main table NRZI conversion circuit, A main table NRZI code word flip-flop that outputs in synchronism, a sub-table NRZI code word flip-flop that latches an NRZI code word output from the sub-table NRZI conversion circuit and outputs the same in synchronization with an input clock;
The DSV output from the main table DSV arithmetic circuit is latched, and the main table modulation RO is synchronized with an input clock.
M, and latches the DSV output from the sub-table DSV operation circuit and the sub-table modulation ROM in synchronization with an input clock.
A NRZI codeword selector for selecting and outputting one of an output of the main table NRZI codeword flip-flop and an output of the subtable NRZI codeword flip-flop; An NRZI code flip-flop that latches the output of the NRZI code word selector and outputs it in synchronization with an input clock, and selects one of the output of the main table DSV flip-flop and the output of the sub-table DSV flip-flop. Latching the output of the DSV selector and the output of the DSV selector,
A DSV flip-flop for outputting to the main table modulation ROM and the sub-table modulation ROM in synchronization with an input clock; a lower bit of an output of the NRZI code word flip-flop and a higher order of an output of the sub-table NRZI code word flip-flop; The run length of the connection portion between the bit and the connection portion between the lower bit of the output of the sub-table NRZI code word flip-flop and the upper bit of the input of the main table NRZI code word flip-flop are both equal to or greater than the minimum value of the run length limit. When the absolute value of the integrated value of the DSV is smaller in selecting the output of the sub-table DSV flip-flop than in selecting the output of the main table DSV flip-flop, it is determined based on the sub-table modulation ROM. Select the data requested in Expediently, the main table modulating ROM
The signal for selecting the data obtained based on
An RZI codeword selector and a decision circuit for outputting to the DSV selector;
Selects and uses one of the main tables based on the output of the main table DSV flip-flop and the output of the DSV flip-flop,
Is to select and use one of the sub-tables based on the output of the sub-table DSV flip-flop and the output of the DSV flip-flop.

According to the tenth aspect of the present invention, when the run length limit of the connection portion is satisfied, the code word of the sub-table can be selected. Can be increased, or the integrated value of DSV can be decreased.

According to an eleventh aspect of the present invention, there is provided a conversion table as a code conversion device for converting input data of one word of M bits into an NRZ code word of one word of N bits with run-length limited. The configuration is such that the run length at the front end and the rear end of the word is half or more of the minimum value of the run length limit, and that the conversion table alone has (L / K) × 2 ^M code words or more. The minimum value of the Hamming distance between the codeword of the converted conversion table and the input data divided in codeword units is obtained as a branch metric, and the branch metric and a branch metric for outputting a decoded value of the codeword corresponding thereto Calculation means and for each state,
Among the state transitions having the state as the transition destination, the maximum likelihood transition information indicating the state transition in which the sum of the branch metric and the path metric value of the state transition source is the minimum value and a decoded value corresponding to the branch metric are output, Maximum likelihood state transition selecting means for holding the minimum value as a new path metric value; storing the decoded values; and selecting the decoded values from these decoded values in accordance with the maximum likelihood transition information. And a maximum likelihood path holding unit that outputs a decoded value corresponding to the maximum likelihood path.

According to the eleventh aspect, it is possible to obtain the decoded value of the code word closest to the data read from the recording medium.

Further, according to the twelfth aspect of the present invention,
Wherein the maximum likelihood path holding means outputs a decode value corresponding to each of the paths and the number of the paths when there are a plurality of paths having continuous state transitions.

According to the twelfth aspect of the present invention, a plurality of decode value candidates are obtained, and then a correct decode value can be selected by ECC.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments, as an example,
Input data of 16 bits per word is converted into 32 bits per word, run length limited NR of minimum run length 2
The case of converting to a Z code will be described. Also, the description will be made on the assumption that the obtained NRZ code is converted into an NRZI code and then recorded on a recording medium such as an optical disk.

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory diagram showing an example of a 32-bit NRZ codeword. The codeword is recorded on the recording medium in order from the most significant bit (hereinafter, referred to as MSB) to the least significant bit (hereinafter, referred to as LSB). NRZ
A portion where bits having the same value are continuous in the NRZI code obtained by performing NRZI conversion on the code, that is, a portion where bits having a value of “0” are continuous in the NRZ code is called a run, and its length is a run length. That. The run at the front end including the MSB is referred to as an FR run connection, and the run at the rear end including the LSB is referred to as an RR run connection.

Since the FR run connection is connected to the RR run connection of the preceding code word and the RR run connection is connected to the FR run connection of the subsequent code word, if attention is paid to only one code word, The run lengths of the FR run connection and the RR run connection have not been determined. Minimum run length limit is 2
Therefore, the run length of the portion excluding the FR run connection portion and the RR run connection portion of the code word is set to 2 or more, and the code word before and after is connected to connect the RR run connection portion of the previous code word and the rear portion. When the FR run connection portion of the code word is one continuous run, the code words are combined so that the run length of the connection portion is 2 or more.

In the following, when the NRZ code word is simply referred to as “weight”, it indicates the number of bits that are “1” in the code word after the NRZ code word is subjected to NRZI conversion. An NRZ code word having an even weight is referred to as an even-weight code word, and an NRZ code word having an odd weight is referred to as an odd-weight code word. Further, the NRZ codewords are classified by the run length of the FR run connection unit, the run length of the RR run connection unit, and the oddness or evenness of the weight of the codeword after the NRZI conversion. If the run length is 2 or more, the run length is classified as 2. For example, the codeword in FIG.
It is classified under the notation R2RR1e. This is F
The run length of the R run connection unit is 2 or more, the run length of the RR run connection unit is 1, and the weight of the codeword converted into the NRZI code word is an even number. When the weight is odd, the last character is set to o.

FIG. 2 shows the minimum run length 2, one word 3
It is explanatory drawing which shows the number of codewords for every classification of 2-bit NRZ codeword. FIG. 2A shows the FR run connection portion and the RR.
The run length of each of the run connection parts indicates one-half or more of the minimum value of the run-length limit, that is, the number of codewords in which the run length of each of the connection parts is one or more.
FIG. 2B shows that at least one of the FR run connection portion and the RR run connection portion has a run length that is less than half the minimum value of the run length limit, that is, one of the run lengths of the connection portion. Indicates the number of codewords for which is 0.

As shown in FIG. 2A, there are 125491 codewords having a run length of 1 or more in both the FR run connection section and the RR run connection section. When these codewords are connected to each other, the run length of the connection portion between the two codewords is two or more, so that any combination is possible. Of the codewords in FIG. 2A, there are 62744 codewords with even weights and 62747 codewords with odd weights.

Further, as shown in FIG. 2B, there are 1,4051, code words in which at least one of the run lengths of the FR run connection portion and the RR run connection portion is 0. Of these codewords, those with even weight are:
There are 72029 codewords with an odd weight of 72022
There are pieces. From the code words shown in FIG. 2, code words “00000000h” and “FFFFFFF” having no edge in one code word
Fh ″ (h at the end indicates hexadecimal notation), the total number of codewords is 269540.

In this embodiment, as shown in FIG. 2A, a code word having a run length of 1 or more is used for both the FR run connection section and the RR run connection section.

Here, from the odd / even weights of the codewords of the immediately preceding two words obtained by the conversion, four states (stats) are obtained.
e), that is, (Even, Even), (Odd,
Odd), (Even, Odd) and (Odd, Eve)
Consider a state machine that takes n). FIG. 3 is a state transition diagram of the state machine. Even indicates that the weight of the codeword is even and Odd is odd, two words before,
The oddness of the weight of the code word is shown in the order of one word before.

FIG. 4 is an explanatory diagram showing the structure of a conversion table for converting input data into NRZ code words, which is used according to the four states shown in FIG. Here, only the number of codewords assigned for each classification is shown.

As shown by the presence or absence of oblique lines in FIGS. 3 and 4, the case where the state is (Even, Even) and the case where (Odd,
Odd), the same conversion table (hereinafter referred to as conversion table 1) is used, and the state is (Even, Od).
The same conversion table (hereinafter referred to as conversion table 2) is used in the case of d) and in the case of (Odd, Even). That is, one type is selected and used from two types of conversion tables according to the four states. In particular, when transitioning from a different state to the same state, a different conversion table is used in the transition source state. Further, in the conversion table of FIG. 4, 16-bit input data (Da
ta Symbol), from 0000h to 7FFFh, the NRZ codeword that becomes an even weight after NRZI conversion is 8
From 000h to FFFFh, NRZ codewords having odd weights after NRZI conversion are assigned.

As shown in FIG. 4, the conversion table 1 contains 0
For input data from 000h to 7FFFh, F
6802 code words of R1RR2e, 14604 code words of FR2RR2e, and 31 code words of FR1RR1e
67, and 6,798 code words of FR2RR1e are used. Also, the conversion table 1 is 8000h to FFFF
For input data up to h, 6798 code words of FR1RR2o and 14608 code words of FR2RR2o are used.
, FR1RR1o codewords 3165, FR2RR
6802 code words of 1o are used. Conversion table 2
And these are all different codewords.

The conversion table 1 is the FR of the conversion table 1.
Although it is different from 6802 codewords of 1RR2e, 1397 additional codewords identical to a part of 6802 codewords of FR1RR2e in conversion table 2 are used. The conversion table 1 is different from the 6798 code words of FR1RR2o in the conversion table 1, but is different from the FR1R in the conversion table 2.
An additional 1,395 codewords identical to a portion of the 6,798 codewords of R2o are used. Similarly, conversion table 2 is
Although 1397 codewords which are different from 6802 codewords of FR1RR2e of conversion table 2 and which are the same as part of 6802 codewords of FR1RR2e of conversion table 2 are used, codeword 6 of FR1RR2o of conversion table 2 is used.
798 but different from FR1RR2 in conversion table 1.
The same codeword as a part of the 6798 codewords of o
395 are used.

The conversion table 1 and the conversion table 2
FR1RR2e and FR1RR2o used in both
Are assigned to different input data in each conversion table.

The run length of the connection part between codewords obtained by such a conversion table is such that the run length of the FR run connection part and the RR run connection part of each codeword is one.
As described above, the minimum value 2 of the run-length limit is always satisfied.

In these two types of conversion tables, FR1
Except for 1397 code words of RR2e and 1395 code words of FR1RR2o, all code words are different code words. Therefore, between these two types of conversion tables, the distance 2 is maintained between most of the even-weight codewords and between the odd-weight codewords. It should be noted that 1397 FR1RR2e and FR1RR of which the distance 2 is not taken between the even weight codewords and the odd weight codewords
For 1395 2o, a code word in which an error is unlikely to occur, such as a code word including a long run, may be used.

If there are two types of conversion tables, and if each conversion table allocates 75% or more of the required number of codewords whose codewords are kept at a distance of 2 from each other, the insufficient number of codewords is required. 25% or less of the number of code words. If a part of the codewords of the other conversion tables that are kept at a distance of 2 from each other is used as this missing codeword,
More than 50% of the required number of codewords in all the conversion tables have a distance of 2 from each other. Therefore, even if an error occurs, the probability of correction can be reduced to 1/2 or more.

The error propagates up to the maximum constraint length, but the average error propagation is less than half the constraint length. If the constraint length is 4, the average error propagation is 2, the number of errors before decoding is E, and the probability that the error cannot be corrected is 1/2.
The number of errors after decoding is E × (１ ／) × 2 = E, which is the same as before decoding. Therefore, among the code words required in all the conversion tables, the higher the percentage of code words that are kept at a distance of 2 from each other, the higher the correction capability is, but the ratio is 7
If it is 5% or more, even if there is error propagation due to erroneous correction, the number of corrections exceeds and the total number of errors after decoding decreases. At this time, the number of code words only one conversion table has the total conversion table necessary number of codeword of more than 50%, i.e., (L / K) × 2 16 pieces (L is a number of 1 or more, K is a conversion table Number). In the present embodiment, the value of L is about 1.8 and the value of K is 2. Note that the longer the constraint length, the higher the correction capability.

FIG. 5 is an explanatory diagram showing a specific example of a part of the conversion table of FIG. The NRZ code words for the input data from 0 to 65535 are obtained according to the state on the state transition diagram of FIG. 3 at that time, that is, the oddness or evenness of the weight of the code word of the immediately preceding two words. . The input data is represented by a decimal number, and the code word is represented by a hexadecimal number. The state E indicates Even and O indicates Odd. For example, the state EO indicates the same meaning as the state (Even, Odd).

Next, a specific conversion example using the conversion table of FIG. 4 will be described. Now, the initial state is (Even, Ev
en). If the input data to be converted is 800
It is assumed that 0h, F000h, 1000h, and 8000h are input in this order.

The first input data is a state (Eve)
n, Even) in the conversion table 1 corresponding to 8000h
Is converted to an odd-weight code word corresponding to the following equation. Since this code word has an odd-weight, the state is (Even, Odd)
Transitions to. The second input data is the state (Eve)
In the conversion table 2 corresponding to (n, Odd), the code word is converted into an odd-weight code word corresponding to F000h, and the state is (Od).
d, Odd). The third input data is 10 in the conversion table 1 corresponding to the state (Odd, Odd).
It is converted into an even-weight codeword corresponding to 00h, and the state transits to (Odd, Even). The fourth input data is converted into an odd-weight codeword corresponding to 8000h in the conversion table 2 corresponding to the state (Odd, Even), and the state transits to (Even, Odd).

Here, the fourth input data is the same as the first input data, both are converted into codewords of odd weight, and the same state (Even, Od
It has transited to d). However, in the conversion table 1 used for the first input data and the conversion table 2 used for the fourth input data, the same input data is mapped to a unique codeword, so that the first The input data and the fourth input data are converted into different code words. Therefore, a distance of 2 or more is obtained between the obtained codewords. Therefore, even if one of these codewords has a 1-bit error during reproduction, an error can be detected by performing Viterbi decoding. Further, when a 1-bit error occurs, the path of the state transition is different, so that error correction can be performed.

FIG. 6 is a block diagram of a code conversion apparatus using the conversion tables of FIGS. 6 includes a modulation ROM 11, an NRZI conversion circuit 12,
Bit output flip-flop 13, exclusive OR (EXOR) circuit 14, and first flip-flop 15
And a second flip-flop 16.

The modulation ROM 11 has a built-in conversion table for converting 16-bit input data into a 32-bit NRZ code word as described with reference to FIGS. The input data to be converted is input to the modulation ROM 11 as 16-bit parallel data in synchronization with the input clock signal. The modulation ROM 11 has a flip-flop 15
And 16 are also input. Flip-flop 1
The outputs of Nos. 5 and 16 indicate the oddness and evenness of the NRZI-converted weights of the NRZ codeword converted two words before and one word before, respectively. These outputs indicate that the weight is even when “0” and odd when “1”. The modulation ROM 11 converts the input data into NRZ codeword data based on a built-in conversion table, and outputs the converted data to the NRZI conversion circuit 12 as 32-bit width parallel data.

The NRZI conversion circuit 12 receives the input NR
The Z codeword data is converted into NRZI codeword data and output to the output flip-flop 13 and the exclusive OR circuit 14. Output flip-flop 13 outputs the NRZI codeword data in synchronization with the input clock. The exclusive OR circuit 14 calculates an exclusive OR between all bits of the input NRZI codeword data, and outputs the first flip-flop 1
5 is output. Since the exclusive OR represents the oddness or evenness of the weight of the NRZI code word data, the exclusive OR circuit 14 operates as a weight calculating means.

The first flip-flop 15 outputs the inputted exclusive OR to the second flip-flop 16 and the modulation ROM 11 in synchronization with the input clock. The second flip-flop 16 outputs the input exclusive OR to the modulation ROM 11 in synchronization with the input clock.

FIG. 7 is a block diagram of the NRZI conversion circuit 12. The NRZI conversion circuit 12 includes a flip-flop 121 and 32 two-input exclusive OR gates 122 corresponding to each bit of the input NRZ codeword data.
And

The output of the exclusive OR gate 122 corresponding to the LSB of the NRZ code word, that is, the LSB of the NRZI code word one word before is input to the flip-flop 121. The flip-flop 121 outputs this to the exclusive OR gate 122 corresponding to the MSB in synchronization with the clock signal.

Exclusive OR gate 12 corresponding to MSB
2 is the MS of the current NRZ codeword to be converted
B is also input. If the value of the MSB is 1, the output of the flip-flop 121 is inverted, and if the value of the MSB is 0, the output of the flip-flop 121 is output as it is as the MSB of the NRZI code word. The exclusive OR gate 122 corresponding to the MSB also outputs this output to the exclusive OR gate 122 corresponding to the next lower bit. The exclusive OR gate 122 also receives as an input the lower bit of the MSB of the NRZ code word, and similarly outputs the exclusive OR as the lower bit of the MSB of the NRZI code word.

As described above, the NRZ code word is converted into the NRZI code word by sequentially obtaining the exclusive OR of the output of the adjacent exclusive OR gate on the MSB side and the bit of the input NRZ code word data. can do.

In the code conversion device of FIG. 6, a reset signal is input to the NRZI conversion circuit 12, the first flip-flop 15, and the second 16. In the NRZI conversion circuit 12 in FIG. 7, a reset signal is input to the flip-flop 121. When the reset signal is asserted, the transcoder enters an initial state. At this time, the values of the first flip-flop 15, the second flip-flop 16, and the flip-flop 121 are set to “0”.
That is, the weight of the NRZI code word of the NRZ code word one word before and two words before the NRZI conversion is an even number, and the LSB of the NRZI code word one word before and the LSB is 0.

FIG. 8 is a block diagram showing a modification of the code conversion apparatus shown in FIG. In this transcoder, the exclusive OR circuit 14 is omitted, and instead, the input NR
The MSB of the Z codeword data is the first flip-flop 15
Has been entered.

The conversion tables of FIGS. 4 and 5 are mapped so that the MSB of the input data can determine whether the weight of the NRZ codeword after the NRZI conversion is odd or even.
That is, this conversion table indicates that the codeword having an even-numbered weight after the NRZI conversion is used when the MSB of the input data is “0”, and the NRZI is used when the MSB of the input data is “1”.
The input data is converted into a code word having an odd weight after the conversion.

Therefore, when using the conversion table mapped as described above, there is no need to calculate the weight. In addition, the meaning of the input signal to the first flip-flop 15 is “0”, which indicates an even weight, so that the MSB of the input data can be directly input to the first flip-flop 15.

As described above, by devising the mapping of the code words in the conversion table, the code conversion device can be simplified. Note that the values of bits other than the MSB of the input data may correspond to the oddness or evenness of the weight of the NRZI-converted codeword of the NRZ codeword.

In each bit of the code word, +1 is given to a bit that is “1”, and −1 is given to a bit that is “0”.
The sum of all bits of one word is called DSV. For example, in a 32-bit code word, DSV
Is always a multiple of two. The DSV is a multiple of 4 when the weight of the codeword is even, and is not a multiple of 4 when the weight of the codeword is odd. Therefore, DSV
It can be understood that when the value of the second bit is “0” from the LSB of “1”, the code word has an even weight, and when the value is “1”, the code word has an odd weight.

For this reason, in this embodiment, the value of a specific bit of the DSV after the NRZI conversion of the NRZ codeword can be used instead of the NRZI conversion weight of the NRZ codeword. That is, in FIG. 3, the state is changed according to the value of a specific bit of the DSV. Although not shown, a DSV operation unit is provided instead of the exclusive OR circuit 14 in FIG. Eye value first
May be output to the flip-flop 15.

The conversion tables in FIGS. 4 and 5 are mapped so that the value of a specific bit of the DSV after NRZI conversion of the NRZ codeword can be determined from the value of a specific bit such as the MSB of the input data. Is also good.

(Second Embodiment) FIG. 9 is an explanatory diagram showing the configuration of a conversion table having the conversion table of FIG. 4 as a main table and further having a sub table. Here, only the number of codewords assigned for each classification is shown. Also in the present embodiment, the minimum value of the run-length limit is 2. Further, the point that one type is selected from two types of conversion tables according to the four states on the state transition diagram of FIG. 3 and used is the same as in the first embodiment.

The sub-table indicates that the run length of the FR run connection portion or the RR run connection portion is less than half the minimum value of the run length limit, as described with reference to FIG. Are formed of 0 code words. The oddness and evenness of the codeword weights for the same input data are the same in the main table and the sub-table. For example, if the code word of the main table is odd weight, the code word of the sub table is also odd weight.

In this embodiment, under the condition that the run length of the connection between the codeword obtained by converting the input data and the codewords connected before and after it is equal to or more than the minimum value of the runlength limit, An integrated value of DSV is calculated when a codeword obtained from the main table is used and when a codeword obtained from the sub-table is used, and a codeword having a smaller absolute value is selected. The integrated value of DSV is obtained by integrating the DSV obtained for each codeword. Therefore, it is desirable that the DSV code is not the same between the code word of the sub-table corresponding to the same input data and the code word of the main table. For example, when the integrated value of the DSVs of the codewords up to one word before is 0, if the DSV of the codeword of the main table is a positive number, the DSV of the codeword of the sub-table is 0 or Desirably a negative number.

In the main table, codewords whose distances are not sufficient (1397 FR1RR2e and F1RR2e in FIG. 9)
(1395 R1RR2o), it is preferable that at least the run length of one of the front and rear connection portions is equal to or greater than the minimum value of the run length limit so that the code word of the sub table corresponding to 1395 R1RR2o can be connected to the preceding and succeeding code words. . By using the code word of the sub-table,
The probability of using a codeword whose distance is not sufficiently large can be reduced as much as possible, and the correction probability can be increased.

FIG. 10 is an explanatory diagram showing a part of a specific example of the conversion table of FIG. The code words for the input data from 0 to 65535 correspond to the states in the state transition diagram of FIG. 3, that is, the odds and evens of the weights of the code words of the immediately preceding two words, and the main table (Main) and the Table (Su
One word can be obtained from b). The input data is represented by a decimal number, and the code word is represented by a hexadecimal number.

FIG. 11 is a block diagram of a code conversion apparatus using a conversion table having the sub-tables of FIGS. The code conversion device shown in FIG.
21, a main table NRZI conversion circuit 22, a main table DSV operation circuit 23, a main table NRZI code word flip-flop 24, a main table DSV flip-flop 25, a judgment circuit 26, an NRZI code word selector 27, and an NRZI Code word flip-flop 28, sub-table modulation ROM 31, sub-table NRZI conversion circuit 32, sub-table DSV operation circuit 33, sub-table NRZI code word flip-flop 34, sub-table DSV flip-flop 35, DSV selector 37
And a DSV flip-flop 38.

The main table modulation ROM 21 and the sub-table modulation ROM 31 have the same structure as that of FIG.
A conversion table for converting bit input data into a 32-bit NRZ code word is provided. Main table modulation RO
M21 includes a main table, and the sub-table modulation ROM 31 includes a sub-table. The input data to be converted is 16
The main table modulation ROM 21 and the sub table modulation ROM 3 are synchronized with the clock signal as parallel data of bit width.
1 is input. The main table modulation ROM 21 has a main table DSV flip-flop 25 and a DSV
The output of the flip-flop 38 is a sub-table modulation ROM.
The output of the sub-table DSV flip-flop 35 and the DSV flip-flop 38 is input to 31.

The outputs of main table DSV flip-flop 25 and sub-table DSV flip-flop 35 are 1
This is the DSV of the NRZI-converted codeword of the NRZ codeword converted before the word by the main table and the sub-table, respectively. The output of the DSV flip-flop 38 is the DSV of one of the NRZI-converted codewords of the NRZ codewords converted by the main table and the sub-table two words before.

The main table modulation ROM 21 converts the input data into an NRZ code word based on the main table, and outputs the converted data to the main table NRZI conversion circuit 22 as 32-bit width parallel data. Similarly, the sub-table modulation ROM 31
Converts the input data into NRZ codewords based on the sub-table and outputs it to the sub-table NRZI conversion circuit 32.

The main table NRZI conversion circuit 22 synchronizes the input NRZ code word with the input clock to
It is converted into a code word and output to the main table DSV operation circuit 23 and the main table NRZI code word flip-flop 24. Similarly, the sub-table NRZI conversion circuit 32 synchronizes the input NRZ code word with the input clock to
It is converted into a code word and output to the sub-table DSV operation circuit 33 and the sub-table NRZI code word flip-flop 34.

The main table DSV calculation circuit 23 calculates the DSV in word units only for the input NRZI codeword and outputs it to the main table DSV flip-flop 25. Similarly, the sub-table DSV calculation circuit 33 calculates the DSV in word units for only the input NRZI codeword.
And outputs it to the sub-table DSV flip-flop 35.

The main table NRZI code word flip-flop 24 and the sub table NRZI code word flip-flop 34 output the input NRZI code word to the NRZI code word selector 27 in synchronization with the input clock.

The NRZI code word selector 27 selects an NRZI code word in accordance with the output of the
Output to the I code word flip-flop 28. The NRZI code word flip-flop 28 outputs the input NRZI code word in synchronization with the input clock.

The main table DSV flip-flop 25 and the sub-table DSV flip-flop 35 output the input DSV to the judgment circuit 26 in synchronization with the input clock. The main table DSV flip-flop 25
Outputs the data of the second bit counted from the LSB of the DSV to the main table modulation ROM 21 and the DSV selector 37. Secondary table DSV flip-flop 3
5 outputs the data of the second bit counted from the LSB of the DSV to the sub-table modulation ROM 31 and the DSV selector 37. As described in the first embodiment,
The second bit data counted from the LSB of the DSV corresponds to the evenness of the codeword weight.

The DSV selector 37 selects the DSV data corresponding to the code word selected by the NRZI code word selector 27 according to the output of the decision circuit 26, and
Output to the flip-flop 38. The DSV flip-flop 38 synchronizes the input DSV data with the clock to make the main table modulation ROM 21 and the sub table modulation R
This is fed back to the OM31.

The decision circuit 26 determines the upper 3 bits of the input data of the main table NRZI code word flip-flop 24,
Upper 3 bits and lower 3 bits of output data of sub-table NRZI code word flip-flop 34, lower 3 bits of output data of NRZI code word flip-flop 28, output of main table DSV flip-flop 25 and sub table DSV flip-flop 35 Take output as input.
Based on these inputs, the determination circuit 26 obtains N from the main table modulation ROM 21 and the sub table modulation ROM 31
Of the codewords converted to the RZI code, “1” is selected to select a codeword obtained based on the sub table, “0” is selected to select a codeword obtained based on the main table,
NRZI codeword selector 27 and DSV
Output to selector 37.

FIG. 12 is a block diagram of the main table DSV operation circuit 23. The DSV operation circuit 23 has 16 1
A bit 2 input adder 231, a 2 bit 16 input adder 232, and a 6 bit 2 input signed subtractor 233
And

Sixteen 1-bit 2-input adders 231
Inputs a 32-bit NRZI codeword two bits at a time and outputs the addition result to a 2-bit 16-input adder 232. The adder 232 outputs each bit of the addition result to the subtractor 233 as 1-bit data on the MSB side. The subtractor 233 is set to subtract 32 from the input addition result, and outputs the subtraction result as DSV data. The sub-table DSV operation circuit 33 has the same configuration.

FIG. 13 is a block diagram of the judgment circuit 26. The judgment circuit 26 of FIG.
1, the second run determination circuit 262, and the first adder 26
3, a second adder 264, an absolute magnitude comparator 265, a decision logic circuit 266, a DSV
An integrated value selector 267 and a DSV integrated value flip-flop 268 are provided.

The first run determination circuit 261 sets the run length of the connection between the lower three bits of the output of the NRZI code word flip-flop 28 and the upper three bits of the output of the sub-table NRZI code word flip-flop 34 as It is determined whether or not it is equal to or more than the minimum value of the run length limit. The second run determination circuit 262 calculates the lower 3 bits of the output of the sub-table NRZI codeword flip-flop 34 and the main table NRZ
It is determined whether or not the run length of the connection between the upper three bits of the input to the I code word flip-flop 24 is equal to or greater than the minimum run length limit.

In a portion having a run length of 2 or more in an NRZ code word, three or more "0" s or "1" s are continuous when the code word is subjected to NRZI conversion. For this reason, the first and second
The run determination circuits 261 and 262 of the
"000001", "00001"
1 "," 000111 "," 001111 "," 011 "
111 "," 100000 "," 110000 "," 1 "
11000 "," 111100 "or" 111110 "
, It is determined that the run length of the connection portion satisfies the minimum run length limit, and "1" is determined by the determination logic circuit 266.
Output to

The first adder 263 has a main table DS
The output of the V flip-flop 25 and the output of the DSV integrated value flip-flop 268 which is the integrated value of the DSV up to that point are input. The first adder 263 calculates these 2
The sum of the two inputs is obtained as a temporary DSV integrated value, and is output to the absolute value magnitude comparator 265 and the DSV integrated value selector 267.

The second adder 264 has a sub-table DS
The output of V flip-flop 35 and the output of DSV integrated value flip-flop 268 are input. The second adder 264 calculates the sum of these two inputs as a provisional DSV integrated value, and calculates the absolute value magnitude comparator 265
And the DSV integrated value selector 267.

Absolute value magnitude comparator 26
5 is the absolute value of the provisional DSV integrated value output from the first adder 263 and the provisional DSV output from the second adder 264.
When the absolute value of the value output from the second adder 264 is smaller, that is, when the absolute value of the value output from the second adder 264 is smaller, that is, from the point of the DSV integrated value, the codeword obtained based on the sub-table is selected. "1" when it is better to do it, "0" otherwise
Is output to the decision logic circuit 266.

The decision logic circuit 266 makes a decision according to the input signals from the first and second run decision circuits 261 and 262 and the absolute value magnitude comparator 265, and converts the decision signal into a DSV integrated value selector 267 and an NRZI codeword selector. 27 and the DSV selector 37.

FIG. 14 is an explanatory diagram of the logic used by the decision logic circuit 266 for the decision. In FIG. 14, "x" indicates that the value may be either "1" or "0". The decision logic circuit 266 includes first and second run decision circuits 261,
262 and absolute magnitude comparator 2
When all the three input signals from 65 are "1", that is, when the run lengths of the connection portions with the code words before and after the code word obtained based on the sub-table are both equal to or more than the minimum value of the run length limit Only when the absolute value of the DSV integrated value of the code word obtained based on the sub-table is smaller than that of the code word obtained based on the main table, based on the sub-table, "1" is output as the selected code word should be selected.

The DSV integrated value selector 267 outputs the output of the second adder 264 when the judgment signal from the judgment logic circuit 266 is “1”, and otherwise outputs the first adder 26.
3 is selected as the DSV integrated value and output to the DSV integrated value flip-flop 268. The DSV integrated value flip-flop 268 converts the input DSV integrated value into the first and second adders 263 and 264 in synchronization with the input clock.
Feedback to

The conversion tables provided with the sub-tables of FIGS. 9 and 10 are mapped so that the weight of the NRZI-converted codeword after the NRZI conversion can be determined by, for example, the MSB of the input data. That is, when the MSB of the input data is “0”, this conversion table indicates that the NRZI
The MSB of the input data is added to the code word that becomes an even weight after conversion.
Is "1", the input data is converted into a codeword having an odd weight after NRZI conversion.

The conversion tables in FIGS. 9 and 10 are mapped so that the value of a specific bit of the DSV after NRZI conversion of the NRZ codeword can be determined from the value of a specific bit such as the MSB of the input data. Is also good.

In this embodiment, the NRZ codeword NR
Instead of a specific bit value of the DSV after ZI conversion, NR
The weight after the NRZI conversion of the Z codeword can be used. That is, in FIG. 3, the state is changed according to the weight of the NRZI code word, and although not particularly shown in FIG.
1 further includes a weight calculation means and a two-stage flip-flop, and a main table DSV flip-flop 25,
Instead of the DSVs of the sub-table DSV flip-flop 35 and the DSV flip-flop 38, the weights, which are the outputs of the weight calculation means, are passed through the two-stage flip-flops to the main table modulation ROM 21 and the sub-table modulation ROM 31.
May be fed back.

(Third Embodiment) FIG. 15 is a block diagram of a code conversion apparatus for reproducing data on a recording medium on which a codeword output by the code conversion apparatus according to the first or second embodiment is recorded. is there. The code conversion device shown in FIG.
1, a binarization circuit 52, a PLL circuit 53, a serial / parallel data conversion circuit 54, a branch metric calculation circuit 55, a maximum likelihood state transition selection circuit 56, and a maximum likelihood path holding circuit 57. I have.

The reproduction head 51 converts data recorded on a recording medium such as an optical disk into an analog reproduction signal,
Output to the value conversion circuit 52. The binarization circuit 52 converts the analog reproduction signal into serial binarized data and outputs it to the PLL circuit 53. The PLL circuit 53 samples the serial binary data, converts it into serial digital data, and outputs it to the serial / parallel data conversion circuit 54.

Generally, serial digital data includes
Even when data is recorded on a recording medium without error, a random error such as an edge shift error is included. If the recording code is directly decoded with respect to the serial digital data, the decoded data will include errors equal to or greater than the number of edge shifts. Therefore, here, Viterbi decoding is performed using the Hamming distance between the serial digital data and the code word as a branch metric.

Serial / parallel data conversion circuit 54
Converts the input serial digital data into parallel digital data that is parallelized in codeword units, and outputs the parallel digital data to the branch metric calculation circuit 55. Branch metric calculation circuit 5
5 selects codewords each having the smallest Hamming distance with the parallel digital data for each of the eight state transitions shown in FIG. 3, and uses these Hamming distances as branch metrics. The branch metric calculation circuit 55 outputs these branch metrics and the decoded value of the corresponding code word to the maximum likelihood state transition selection circuit 56.

When attention is paid to one of the four states shown in FIG. 3, one of a plurality of state transitions that transition to the state, a branch metric corresponding to the state transition, A sequence of state transitions that continue to the state of the transition source of the state transition, that is, the state transition that has the smallest sum with the integrated value of branch metric of path surviving state transition (referred to as path metric value) is assigned to that state. It is called the maximum likelihood transition.

The maximum likelihood state transition selection circuit 56 calculates the maximum likelihood transition for each state, and outputs the maximum likelihood transition of each state and the decoded value of the code word corresponding to the maximum likelihood transition to the maximum likelihood path holding circuit 57. . The maximum likelihood path holding circuit 57 holds the maximum likelihood transition of each state as the maximum likelihood path, sequentially selects the path with the highest likelihood, and eliminates the other paths to obtain a path with the highest likelihood surviving. Output the decoded value of the corresponding codeword.

FIG. 16 is a block diagram of the branch metric calculation circuit 55 and the maximum likelihood state transition selection circuit 56 of FIG. In the following, for example, a state in which the code word two words before is odd weight and the code word one word before is even weight is expressed as OE, and a code word of even weight is obtained using the conversion table for the state OE. , The state transition to the state EE is represented as OE → EE.

The branch metric calculation circuit 55 performs eight state transitions shown in FIG. 3, namely, EE → EE, OE → EE,
EE → EO, OE → EO, EO → OO, OO → OO, O
Branch metric calculation ROMs 551a to 551h corresponding to the respective state transitions of O → OE and EO → OE are provided. The maximum likelihood state transition selection circuit 56 includes adders 561a to 561a.
561h and a two-input magnitude comparator 56
2a to 562d and selectors 563a to 563d, 5
64a to 564d and path metric flip-flops 565a to 565d.

The parallel digital data is input to branch metric calculation ROMs 551a to 551h. In the branch metric calculation ROMs 551a to 551h, for input data, a branch metric having the smallest value among the Hamming distances between the data and all codewords of the conversion table corresponding to each ROM, And a decode value for a codeword corresponding to the branch metric is written in advance.

However, the state transitions EE → EE and OO → O
E, EO → OE and OE → EE, EE → EO and OO → O
O, EO → OO and OE → EO have the same corresponding conversion tables. Therefore, the same data is written in the branch metric calculation ROMs 551a and 551g. Similarly, branch metric calculation ROMs 551b and 5
The same data is written in 51h, 551c and 551f, and 551d and 551e, respectively.

The circuit for calculating the state transition to the state EE among the branch metric calculation circuit 55 and the maximum likelihood state transition selection circuit 56 in FIG. 16 will be described.

The branch metric calculation ROM 551a stores the first
Of the conversion tables of FIGS. 4 and 5 described in the embodiment,
It is applied in the state EE, and corresponds to a portion that outputs a code word of even weight. Branch metric calculation ROM 551b
Is applied in the state OE in the conversion tables of FIGS. 4 and 5 described in the first embodiment, and corresponds to a portion that outputs a code word having an even weight.

Branch metric calculation ROMs 551a and 55
1b outputs the branch metric for the input parallel digital data to the adders 561a and 561b, and outputs the decoded value of the codeword corresponding to each of these branch metrics to the selector 564a.

The adder 561a has a branch metric calculation RO
The branch metric output by M551a is added to the branch metric calculation ROM 551a and the path metric value output from the path metric flip-flop 565a, which is obtained for the corresponding state transition EE → EE transition source state EE, and has a two-input magnitude. Comparator 562a
And selector 563a.

The adder 561b is provided with a branch metric calculation RO
The branch metric output by M551b and the branch metric calculation ROM 551b are added to the path metric value output from the path metric flip-flop 565d, which is obtained for the corresponding state transition OE from the state transition OE → EE, and has a two-input magnitude. Comparator 562a
And selector 563a.

The magnitude comparator 562a
The selector 563 compares the outputs of the adders 561a and 561b, that is, the path metric value of the state transition with the same transition destination state, and selects the smaller value.
a and 564a as control inputs. The magnitude comparator 562a outputs "1" when the output of the adder 561b is smaller, and outputs "0" otherwise.

When the output of the magnitude comparator 562a is "0", the selector 563a operates the adder 5
When the output of 61a is "1", the output of adder 561b is selected and output to path metric flip-flop 565a.

When the output of the magnitude comparator 562a is "0", the selector 564a outputs the decoded value output from the branch metric calculation ROM 551a.
When the value is "1", the decoding value output from the branch metric calculation ROM 551b is selected and output.

The path metric flip-flop 565a
Holds the value output from the selector 563a as a new path metric value for the state EE, and outputs the value to the adders 561a and 561c in synchronization with the word clock.

The magnitude comparator 562a
Outputs the output as maximum likelihood transition information to the state EE, and the selector 564a outputs the output as the decoded value of the maximum likelihood codeword of the state EE to the maximum likelihood path holding circuit 57.

The same applies to a circuit for calculating the state transition to the state EO, the state transition to the state OO, and the state transition to the state OE.

However, the path metric flip-flop 565b adds the path metric value to the state EO to the adder 5
61e and 561h. The path metric flip-flop 565c outputs the path metric value to the state OO to the adders 561f and 561g. The path metric flip-flop 565d outputs the path metric value to the state OE to the adders 561b and 561d.

FIG. 17 shows the maximum likelihood path holding circuit 57 of FIG.
It is a block diagram of. The maximum likelihood path holding circuit 57 holds a decode value corresponding to the code word (maximum likelihood code word) of the maximum likelihood state transition to each state for an appropriate period, and a state transition path that has few errors and eliminates others during that period. And outputs the decoded value of the code word corresponding to. Only one maximum likelihood state transition from one state is not always determined, and a plurality of maximum likelihood state transitions to a plurality of states may be determined. Many maximum likelihood state transitions are derived from state transitions without errors, and state transitions with many errors are eliminated.

As shown in FIG. 17, the maximum likelihood path holding circuit 5
7 can hold the maximum likelihood path for four reproduction data words. The maximum likelihood path holding circuit 57 includes first-stage flip-flops 71a to 71d, second-stage flip-flops 72a to 72d, third-stage flip-flops 73a to 73d, and fourth-stage flip-flop. Step 74
a, 74d and first-stage selectors 75a to 75d
, Second-stage selectors 76a to 76d, third-stage selectors 77a and 77d, and fourth-stage selector 78a.

The flip-flops 71a and 72 shown in FIG.
a, 73a and 74a hold the decoded values corresponding to the maximum likelihood codeword to state EE. Flip-flop 71b,
72b and 73b are state EO, flip-flop 71
c, 72c and 73c are state OO, flip-flop 7
1d, 72d, 73d and 74d hold decode values corresponding to the maximum likelihood codeword to the state OE. Thus, the flip-flop that holds the decode value for each maximum likelihood state is determined. These flip-flops operate in synchronization with a clock.

The decoded value for the maximum likelihood codeword to each state input from the maximum likelihood state transition selection circuit 56 is input to each of the first-stage flip-flops 71a to 71d. The flip-flop 71a outputs the input value to the selectors 75a and 75b in synchronization with the clock. Similarly,
The flip-flop 71b outputs the input value to the selector 7
5c and 75d, the flip-flop 71c outputs to the selectors 75c and 75d, and the flip-flop 71d outputs to the selectors 75a and 75b. Selector 75
The maximum likelihood transition information to the state EE is input to the a, 76a, 77a and 78a from the maximum likelihood state transition selection circuit 56. The selectors 75b and 76b have states EO.
The maximum likelihood transition information to the state OO is stored in the selectors 75c and 76c.
The maximum likelihood transition information to the state OE is input to the d and 77d from the maximum likelihood state transition selection circuit 56.

The selector 75a selects the output of the flip-flop 71a when the maximum likelihood transition information to the state EE is "0", and selects the output of the flip-flop 71d when the maximum likelihood transition information is "1". Output to the output terminal 72a. Similarly, the selector 75b selects the output of the flip-flop 71a when the maximum likelihood transition information to the state EO is "0", and selects the output of the flip-flop 71d when the maximum likelihood transition information is "1". Output to the loop 72b. The selector 75c selects the output of the flip-flop 71b when the maximum likelihood transition information to the state OO is “0”, and selects the output of the flip-flop 71c when the information is “1”. Output. The selector 75d selects the output of the flip-flop 71c when the maximum likelihood transition information to the state OE is "0", and selects the output of the flip-flop 71b when the information is "1". Output.

The flip-flops and selectors in the second to fourth stages operate in a similar manner. However, the third-stage flip-flops 73a and 73d output only to the selector 77a, the flip-flops 73b and 73c output only to the selector 77d, and the fourth-stage flip-flops 74a and 74d output only to the selector 78a.

During the shift to the fourth stage, the decode value corresponding to the code word of the state transition having a small likelihood is eliminated, and the information held in the flip-flop corresponding to each state becomes the same. Selector 78a outputs a decoded value of the code word corresponding to the maximum likelihood state transition.

FIG. 18 shows the maximum likelihood path holding circuit 57 of FIG.
It is a block diagram of the modification of. This circuit includes a maximum-likelihood path holding circuit 57 shown in FIG.
77c and the fourth stage flip-flops 74b and 74c
And a fourth-stage selector 78d and a 32-bit exclusive OR circuit 79.

The fourth-stage selectors 78a and 78d
Output the output to the subsequent stage as a next candidate decode value, and also output the exclusive OR circuit 79. The exclusive OR circuit 79 obtains an exclusive OR between all the bits of the input decoded value and outputs the result as a next candidate flag. When the outputs of the two selectors 78a and 78b are different, that is, when it is not possible to determine which output is an error-free decoded value, the exclusive OR circuit 79 determines that there is a next candidate for the decoded value. Is output to a subsequent ECC decoding unit (not shown).

When the next candidate flag is "1", the subsequent stage ECC decoder calculates each of the syndromes with respect to the decode values output by the selectors 78a and 78b, thereby determining which decode value is correct. it can. When the flag is “1”, the flag can be treated as an error pointer to perform erasure correction.

Note that the number of decode values serving as the next candidate is not limited to two, but may be increased to the number of states (four in the present embodiment). Further, instead of the exclusive OR circuit 79, a circuit such as a subtractor that can detect a match between two input values may be used.

In the first to third embodiments, 1 is set.
Converts 6-bit input data into 32-bit codeword,
Although the case of decoding has been described, the number of bits of input data and codewords is not limited to this.

Although the case where the number K of conversion tables is 2 has been described, K may be 3 or more.

The case where the state on the state transition diagram is determined by the code word from two words before to one word before has been described. The same applies to the case where the state is determined by the code word from three words or more to one word before. is there.

[0136]

As described above, the code used in the present invention is a run-length limited convolutional code. Therefore, by using this code, not only the high frequency component of the signal recorded on the recording medium can be suppressed, but also the error can be corrected by performing Viterbi decoding. That is, E
Since the correction can be performed at the recording code stage regardless of the CC, the reliability and the recording density can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of a 32-bit NRZ codeword.

FIG. 2 shows a minimum run length of 2, N of 1 word and 32 bits.
It is explanatory drawing which shows the number of codewords for every classification of RZ codeword.

FIG. 3 is a state transition diagram of a state machine.

FIG. 4 is an explanatory diagram showing the configuration of a conversion table from input data to NRZ codewords.

FIG. 5 is an explanatory diagram showing a specific example of a part of the conversion table of FIG. 4;

FIG. 6 is a block diagram of a code conversion device using the conversion tables of FIGS.

FIG. 7 is a block diagram of an NRZI conversion circuit.

FIG. 8 is a block diagram of a modified example of the code conversion device of FIG.

FIG. 9 is an explanatory diagram showing a configuration of a conversion table including the conversion table of FIG. 4 as a main table and further including a sub table.

FIG. 10 is an explanatory diagram showing a part of a specific example of the conversion table of FIG. 9;

FIG. 11 is a block diagram of a code conversion apparatus using a conversion table including the sub-tables of FIGS.

FIG. 12 is a block diagram of a main table DSV operation circuit.

FIG. 13 is a block diagram of a determination circuit.

FIG. 14 is an explanatory diagram of the logic used for the determination by the determination logic circuit.

FIG. 15 is a block diagram of a transcoder that reproduces data on a recording medium on which a codeword output by the transcoder of the first or second embodiment is recorded.

FIG. 16 is a block diagram of a branch metric calculation circuit and a maximum likelihood state transition selection circuit of FIG. 15;

17 is a block diagram of the maximum likelihood path holding circuit of FIG.

18 is a block diagram of a modification of the maximum likelihood path holding circuit of FIG.

[Description of Signs] 11 Modulation ROM 12 NRZI conversion circuit 13 Output flip-flop 14 Exclusive OR circuit (weight calculation means) 15 First flip-flop 16 Second flip-flop 121 Flip-flop 122 Exclusive-OR gate 21 Main Table modulation ROM 22 Main table NRZI conversion circuit 23 Main table DSV operation circuit 24 Main table NRZI code word flip-flop 25 Main table DSV flip-flop 26 Judgment circuit 27 NRZI code word selector 28 NRZI code word flip-flop 31 Secondary table modulation ROM 32 Secondary Table NRZI conversion circuit 33 Sub-table DSV operation circuit 34 Sub-table NRZI code word flip-flop 35 Sub-table DSV flip-flop 37 DSV selector 38 DSV Rip-flop 231,232 Adder 233 Signed subtractor 261 First run decision circuit 262 Second run decision circuit 263 First adder 263 264 Second adder 264 265 Absolute value magnitude comparator 266 Decision logic circuit 267 DSV integrated value selector 268 DSV integrated value flip-flop 51 reproduction head 52 binarization circuit 53 PLL circuit 54 serial / parallel data conversion circuit 55 branch metric calculation circuit 56 maximum likelihood state transition selection circuit 57 maximum likelihood path holding circuit 551a to 551h Branch metric calculation ROMs 561a to 561h Adders 562a to 562d Magnitude comparators 563a to 563d, 564a to 564d Selectors 565a to 565d Path metric flip-flops 71a to 71d, 2a~72d, 73a~73d, 7
4a to 74d Flip-flops 75a to 75d, 76a to 76d, 77a to 77d, 7
8a, 78d selector 79 exclusive OR circuit

Claims (12)

[Claims] 1. A conversion table for converting input data of which one word is M (M is a natural number) bits into a run-length-limited NRZ (non return to zero) code word of which one word is N (N is a natural number) bits. The code conversion method used, wherein a run length at a front end and a rear end of the code word is equal to or more than half of a minimum value of a run length limit, and a code word included only in the conversion table is (L / K) × 2 ^M (L is a number of 1 or more, K is a natural number) or more K conversion tables are used, and each of the conversion tables from P (P is an integer of 2 or more) words to 1 word before A code conversion method for selecting and using one of the conversion tables so that different conversion tables are used in different states before transitioning to the same state according to a state determined by a characteristic value of a codeword. 2. A code conversion method using a conversion table for converting input data of M bits in one word into an NRZ code word of one bit in N bits with run length limited, comprising: a front end of the code word; A conversion table configured so that the run length at the rear end is equal to or more than one-half of the minimum value of the run-length limit, and is provided with (L / K) × 2 ^M or more codewords included only in the conversion table. The run length at the front end or the rear end of the code word is less than half the minimum value of the run length limit, and the code word only in the conversion table is (L / K) × 2 ^M A conversion table configured to have more than one conversion table is used as a sub-table, and K sets of conversion tables of the main table and the sub-table are used, and are determined by characteristic values of each codeword from P words to one word before. Depending on the whole state, one of the sets of the conversion tables is selected and used so that different sets of the conversion tables are used in different states before transitioning to the same state. If the run length of the connection portion when the code word and the code word one word before are connected is equal to or more than the minimum value of the run length limit, the code word obtained by the main table and the code word obtained by the sub table are obtained. DSV (digital sum)
A code conversion method in which the code word having the smaller absolute value of the integrated value of (value) is used as the conversion output. 3. The code conversion method according to claim 1, wherein the characteristic value of the codeword is obtained by converting the codeword into an NRZI (non-rewrite) code.
(turn to zero inverted) A code conversion method characterized by the weight of a codeword obtained by conversion. 4. The code conversion method according to claim 3, wherein in the conversion table, the NRZ code word is mapped such that a value of a specific bit of the input data corresponds to the oddness or evenness of the weight. A code conversion method characterized in that: 5. The code conversion method according to claim 1, wherein the characteristic value of the code word is a DSV value of the code word obtained by performing NRZI conversion on the code word. Code conversion method. 6. The code conversion method according to claim 5, wherein the conversion table has an NRZ codeword such that a value of a specific bit of the input data corresponds to a value of a specific bit of the DSV. A transcoding method characterized by being mapped. 7. A conversion table for converting input data of M bits in one word into an NRZ code word of one bit in N bits with run length limitation, wherein run lengths of a front end portion and a rear end portion of the code word are equal. K types of conversion tables which are at least half the minimum value of the run-length limit and are configured to have (L / K) × 2 ^M or more codewords included only in the conversion table are provided. A modulation ROM (read-only memory) that converts input data into an NRZ code word using a conversion table and outputs the read data, an NRZI conversion circuit that converts the NRZ code word into an NRZI code word and outputs the same, Weight calculation means for calculating and outputting the weight of the NRZI code word;
A first flip-flop for outputting the weight of the RZI code word in synchronization with the input clock;
A second flip-flop that outputs the weight of the NRZI codeword before the word in synchronization with the input clock; wherein the modulation ROM outputs an output of the first flip-flop and an output of the second flip-flop. The conversion table is set to 1 based on
A transcoder for selecting and using one. 8. A conversion table for converting one-word M-bit input data into a one-word N-bit run-length-limited NRZ code word, wherein the run length of the front end and the rear end of the code word is K types of conversion tables which are at least half the minimum value of the run-length limit and are configured to have (L / K) × 2 ^M or more codewords included only in the conversion table are provided. A modulation ROM that converts the input data into an NRZ codeword using a conversion table and outputs the NRZ codeword; an NRZI conversion circuit that converts the NRZ codeword into an NRZI codeword and outputs the data; and calculates a DSV of the NRZI codeword. DSV to output
A first flip-flop, which comprises a calculating means, latches the DSV of the NRZI code word, and outputs the DSV of the NRZI code word one word before in synchronization with an input clock; Latch
A second flip-flop that outputs the DSV of the NRZI code word two words before in synchronization with the input clock, wherein the modulation ROM has an output of the first flip-flop and an output of the second flip-flop. The conversion table is set to 1 based on
A transcoder for selecting and using one. 9. A conversion table for converting one-word M-bit input data into a run-length-limited NRZ code word having one-bit N bits, wherein a run length of a front end and a rear end of the code word is It is at least half the minimum value of the run-length limit, and is provided with at least (L / K) × 2 ^M codewords that only the conversion table has. The value of a specific bit of input data and the codeword K types of conversion tables are configured so that the odd / even of the weight of the codeword obtained by the NRZI conversion or the value of a specific bit of the DSV correspond to the input data, and the input data is converted into NRZ using these conversion tables.
A modulation ROM for converting the NRZ code word into an NRZI code word and outputting the NRZI code word; a NRZI conversion circuit for converting the NRZ code word into an NRZI code word; A first flip-flop that outputs a value of a specific bit in synchronization with an input clock; a value of a specific bit of the input data one word before, and a value of a specific bit of the input data two words before And a second flip-flop that outputs the conversion table in synchronization with an input clock. The modulation ROM stores the conversion table in the conversion table based on the output of the first flip-flop and the output of the second flip-flop.
A transcoder for selecting and using one. 10. One word is M bits of input data.
A conversion table for converting a word into an N-bit run-length limited NRZ code word, wherein the run length at the front end and the rear end of the code word is at least half the minimum value of the run length limit, (L / K) × 2 ^M or more codewords included only in the conversion table, and the value of a specific bit of input data corresponds to the oddness or evenness of the weight of the codeword obtained by performing NRZI conversion on the codeword. A main table modulation ROM for converting the input data into NRZ codewords using these conversion tables and for outputting the NRZ codewords; run length of the end portion is less than one-half of the minimum value of the run length limited, provided with a code word only the conversion table has (L / K) × 2 ^M or more, of the specific bit of the input data values The code word NR
K types of conversion tables are configured as sub-tables configured to correspond to odd and even weights of codewords obtained by ZI conversion, and input data is converted into NRZ codewords using these conversion tables. Output sub-table modulation ROM
NRZ codeword output from the main table modulation ROM is represented by N
A main table NRZI conversion circuit that converts the NRZ code word into an RZI code word and outputs the NRZ code word;
A sub-table NRZI conversion circuit that converts the output into an RZI code word and outputs the same; a main table DSV operation circuit that calculates and outputs a DSV of the NRZI code word output from the main table NRZI conversion circuit; A sub-table DSV arithmetic circuit for calculating and outputting a DSV of an NRZI code word to be output; a main table NRZI code word flip-flop for latching an NRZI code word output from the main table NRZI conversion circuit and outputting the NRZI code word in synchronization with an input clock A sub-table NRZI code word output from the sub-table NRZI conversion circuit, and a sub-table NRZI code word flip-flop output in synchronization with an input clock; and a DSV output from the main table DSV operation circuit, The main table modulation RO is synchronized with an input clock.
M, a main table DSV flip-flop that outputs to the sub-table M, and a DSV that is output from the sub-table DSV operation circuit.
A sub-table DSV flip-flop to output to M; an NRZI code-word selector to select and output one of an output of the main table NRZI code-word flip-flop and an output of the sub-table NRZI code-word flip-flop; An NRZI code flip-flop that latches an output of the NRZI code word selector and outputs it in synchronization with an input clock, and selects one of an output of the main table DSV flip-flop and an output of the sub-table DSV flip-flop A DSV selector that latches the output of the DSV selector and outputs the DSV flip-flop to the main table modulation ROM and the sub-table modulation ROM in synchronization with an input clock; and a NRZI code word flip-flop. Output lower bits And the connecting portion between the upper bits of the output of the sub-table NRZI code word flip-flop, and the sub table N
The run length of the connection between the lower bit of the output of the RZI code word flip-flop and the upper bit of the input of the main table NRZI code word flip-flop is both equal to or greater than the minimum value of the run length limit, and the sub table DSV
Selecting the output of the flip-flop is more effective than selecting the output of the main table DSV flip-flop.
When the absolute value of the integrated value becomes smaller, the data obtained based on the sub-table modulation ROM is selected, and in other cases, the data obtained based on the main table modulation ROM is selected. A determination circuit for outputting a signal to the NRZI codeword selector and the DSV selector; the main table modulation ROM includes an output of the main table DSV flip-flop;
One of the main tables is selected and used based on the output of the SV flip-flop, and the sub-table modulation ROM stores the output of the sub-table DSV flip-flop and the D
A code conversion device that selects and uses one of the sub-tables based on an output of an SV flip-flop. 11. One word is M bits of input data.
A conversion table for converting a word into an N-bit run-length limited NRZ code word, wherein the run length at the front end and the rear end of the code word is at least half the minimum value of the run length limit, The minimum value of the Hamming distance between the code word of the conversion table configured to have at least (L / K) × 2 ^M code words included in the conversion table alone and the input data divided in code word units is A branch metric calculating means for obtaining a branch metric and outputting a decoded value of the branch metric and a code word corresponding to the branch metric; for each state, a branch metric and a path of a state transition source among state transitions having the state as a transition destination The maximum likelihood transition information indicating the state transition in which the sum with the metric value becomes the minimum value and the decoded value corresponding to the branch metric are output, and the minimum value is set as a new path metric value. A maximum likelihood state transition selecting means for storing the decoded values, and selecting the decoded values from the decoded values in accordance with the maximum likelihood transition information, thereby outputting a decoded value corresponding to a path having a continuous state transition. A code conversion device comprising a likelihood path holding unit. 12. The code conversion apparatus according to claim 11, wherein the maximum likelihood path holding unit, when there are a plurality of paths having continuous state transitions, stores a decode value corresponding to each of the paths and the number of the paths. A code conversion device for outputting.