JP2007299466A - Modulation device and method, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely perform DSV control even when a parity preservation contravention conversion pattern is adopted. <P>SOLUTION: A RLL conversion pattern processing part 51 converts the first data pattern of input data to a corresponding a first code pattern according to a first table constituted of a parity preservation pattern, a specific rule conversion pattern detecting part 54 detects a parity preservation violation individual conversion code pattern from the converted first code pattern. A specific rule conversion pattern processing control part 55 detects whether a channel bit corresponding to a DSV control bit is included in the parity preservation violation individual conversion code pattern or not, and controls conversion processing to the second code pattern from the parity preservation violation individual conversion code pattern so as to surely perform DSV control. A channel bit string conversion part 56 selects which of conversion processing to the second code pattern or processing to the first code pattern from the parity preservation violation individual conversion code pattern is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a modulation device and method, a program, and a recording medium, and more particularly, to a modulation device and method, a program, and a recording medium that can surely perform DSV control even when an even-oddity preservation violation conversion pattern is adopted. .

  When data is transmitted to a predetermined transmission path or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated so as to be suitable for the transmission path or the recording medium. A block code is known as one of such modulation methods. The block code is to block a data string into units of m × i bits (hereinafter referred to as data words) and convert the data words into code words of n × i bits according to an appropriate coding rule. This code becomes a fixed length code when i = 1, and when a plurality of i can be selected, that is, when a predetermined i in the range of 1 to imax (maximum i) is selected and converted, Become. This block-coded code is represented as a variable length code (d, k; m, n; r).

  Here, i is referred to as a constraint length, and imax is r (maximum constraint length). Further, d represents, for example, the minimum continuous number of “0” that falls between consecutive “1” s, that is, the minimum run of “0”, and k represents the maximum continuous of “0” that falls between consecutive “1”. The number, that is, the maximum run of “0” is shown.

  By the way, when the code word obtained as described above is recorded on an optical disk, a magneto-optical disk, or the like, for example, in a compact disk (CD) or mini disk (MD) (registered trademark), “1” is obtained from a variable length code string. NRZI (Non Return to Zero Inverted) modulation in which “0” is non-inverted, and recording is performed based on the NRZI-modulated variable length code (hereinafter referred to as a recording waveform sequence). This is called mark edge recording. On the other hand, on an ISO standard 3.5-inch / 230 MB capacity magneto-optical disk or the like, the recording-modulated code string is recorded as it is without NRZI modulation. This is called mark position recording. Mark edge recording is often used in recording media with high recording density as at present.

  When the minimum inversion interval of the recording waveform train is Tmin and the maximum inversion interval is Tmax, in order to perform high density recording in the linear velocity direction, the longer the minimum inversion interval Tmin, that is, the larger the minimum run d is. From the viewpoint of clock reproduction, it is desirable that the maximum inversion interval Tmax is shorter, that is, the maximum run k is smaller. In consideration of overwrite characteristics, it is desirable that Tmax / Tmin is small. Furthermore, various modulation methods have been proposed and put into practical use in light of the media conditions, for example, it is important that the detection window width Tw = m / n is large from the point of Jitter and S / N.

  Here, specifically, modulation schemes proposed or actually used in optical disks, magnetic disks, magneto-optical disks, and the like will be listed. EFM code used in CD and MD (also expressed as (2,10; 8,17; 1)) and 8-16 code ((2,10; 1,2; 1) used in DVD (Digital Versatile Disc) ) And RLL (2,7) (also referred to as (2,7; m, n; r)) used in PD (120mm 650MB capacity) is an RLL code with minimum run d = 2 is there. RLL (1,7) (also expressed as (1,7; 2,3; r)) used in MD-DATA2 or ISO standard 3.5inchMO (640MB capacity) is the RLL with the minimum run d = 1 Sign. In addition, in a recording / reproducing disk device such as an optical disk or a magneto-optical disk having a high recording density that is currently being developed and researched, an RLL code with a minimum run d = 1 in which the size of the minimum mark and the conversion efficiency are balanced. (Run Length Limited code) is often used.

The modulation table of the variable length RLL (1,7) code is, for example, the following table.
<Table 1>
RLL (1,7): (d, k; m, n; r) = (1,7; 2,3; 2)
Data pattern Code pattern i = 1 11 00x
10 010
01 10x
i = 2 0011 000 00x
0010 000 010
0001 100 00x
0000 100 010

  Here, the symbol x in the modulation table is “1” when the next channel bit is “0”, and is “0” when the next channel bit is “1”. The maximum constraint length r is 2.

  The parameter of the variable length RLL (1,7) is (1,7; 2,3,2), and the minimum inversion interval Tmin represented by (d + 1) T is 2 when the bit interval of the recording waveform sequence is T. (= 1 + 1) T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin represented by (m / n) × 2 is 1.33 (= (2/3) × 2) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is Tmax = 8 (= 7 + 1) T (= (m / n) × 8Tdata = (2/3) × 8Tdata = 5.33Tdata). Further, the detection window width Tw is expressed by (m / n) × Tdata, and its value is Tw = 0.67 (= 2/3) Tdata.

  By the way, in the channel bit string modulated by RLL (1, 7) in Table 1, the frequency of occurrence is 2T, which is Tmin, and the following is the order of 3T, 4T, 5T, 6T,. When 2T, which is the minimum run (Tmin), is repeated, that is, when a large amount of edge information is generated in an early cycle, it is often advantageous for clock recovery.

  However, for example, when the recording linear density is further increased in recording / reproducing of an optical disc, the minimum run is a portion where an error is likely to occur. This is because the waveform output of the minimum run is smaller than that of other runs during disk reproduction, and is easily affected by, for example, defocusing or tangential tilt. Furthermore, continuous recording / reproduction of the minimum mark at a high recording linear density is easily affected by disturbances such as noise, and therefore, data reproduction errors are likely to occur. As a data reproduction error pattern at this time, there is a case in which an error is caused by a simultaneous shift from the first edge to the last edge of consecutive minimum marks. That is, the generated bit error length propagates from the beginning to the end of the continuous section of the minimum run. Therefore, the problem that the error propagation becomes long appears.

  For stabilization when data is recorded / reproduced at a high linear density, it is effective to limit the continuation of the minimum run.

  On the other hand, when recording data on a recording medium or transmitting data, encoding modulation suitable for the recording medium or the transmission path is performed. If these modulation codes include a low-frequency component, for example, In addition, various error signals such as tracking errors in servo control of the disk device are likely to fluctuate or jitter is likely to occur. Therefore, it is desirable for the modulation code to suppress the low frequency component as much as possible.

  There is a DSV (Digital Sum Value) control as a method for suppressing the low frequency component. The DSV is a recording code string obtained by converting a channel bit string into NRZI (that is, level coding), and the bit string (data symbol) is set to “+1” and “0” to “−1”. It means the sum when adding up. DSV is a measure of the low frequency component of the recording code string. Decreasing the absolute value of the positive / negative fluctuation of the DSV, that is, performing the DSV control, suppresses the low-frequency component except for the DC component of the recording code string.

  The modulation codes according to the variable length RLL (1,7) table shown in Table 1 are not subjected to DSV control. In such a case, DSV control is performed by performing DSV calculation at a predetermined interval in the encoded sequence (channel bit sequence) after modulation, and inserting the predetermined DSV control bits into the encoded sequence (channel bit sequence). This is realized (for example, Patent Document 1).

  The number of DSV control bits to be inserted into the channel bit string is determined by the minimum run d. When d = 1, DSV control bits are inserted at arbitrary positions in the codeword so as to keep the minimum run, the required number of bits is 2 (= d + 1) channel bits. Further, the number of bits required to insert a DSV control bit at an arbitrary position in the codeword so as to keep the maximum run is 4 (= 2 × (d + 1)) channel bits. If DSV control is performed with fewer channel bits, DSV control may not be possible depending on the pattern before and after being sandwiched.

In the RLL (1,7) code in which (d, k; m, n) = (1,7; 2,3), when the DSV control bit is converted into data together with the conversion rate,
4 channel bits x 2/3 = 8/3 = 2.67 data equivalent (2.67 Tdata)
become.

  By the way, the DSV control bit is basically a redundant bit. Therefore, from the viewpoint of code conversion efficiency, it is better to have as few DSV control bits as possible.

  Furthermore, it is preferable that the minimum run d and the maximum run k do not change depending on the inserted DSV control bit. This is because if (d, k) changes, the recording / reproducing characteristics are affected.

  However, in an actual RLL code, since the minimum run has a great influence on the recording / reproducing characteristics, it must be protected, but the maximum run is not always protected. In some cases, there are formats that use a pattern that breaks the maximum run as a synchronization pattern. For example, the maximum run in the 8-16 code of DVD (Digital Versatile Disk) is 11T, but 14T exceeding the maximum run is given in the sync pattern portion to increase the detection capability of the sync pattern.

Based on the above, the present inventors previously proposed the 1,7PP code in Table 2 as a modulation scheme corresponding to a higher recording density with (d, k) = (1,7) (for example, patents). Reference 2).
<Table 2>
1,7PP: (d, k; m, n; r) = (1,7; 2,3; 4)
Data pattern Code pattern
11 * 0 *
10 001
01 010

0011 010 100
0010 010 000
0001 000 100

000011 000 100 100
000010 000 100 000

000001 010 100 100
000000 010 100 000

110111 001 000 000 (next010)
00001000 000 100 100 100
00000000 010 100 100 100

if xx1 then * 0 * = 000
xx0 then * 0 * = 101
=============================
Sync & Termination
# 01 001 000 000 001 000 000 001 (24 channel bits)
# = 0 not terminate case
# = 1 terminate case

Termination table
00 000
0000 010 100

110111 001 000 000 (next010):
When next channel bits are '010',
convert '11 01 11 'to' 001 000 000 '.

  The modulation table in Table 2 is a basic pattern (a conversion pattern consisting of data patterns from (11) to (000000)) that cannot be converted without it as a conversion pattern, and conversion processing is possible without it. However, by doing so, a replacement pattern (a conversion pattern consisting of data patterns (110111), (00001000), and (00000000)) that realizes more effective conversion processing, and the data string is terminated at an arbitrary position. Terminal patterns (conversion patterns composed of data patterns (00) and (0000)).

  In Table 2, the minimum run d = 1 and the maximum run k = 7, and an indeterminate code (a code represented by *) is included in the elements of the basic pattern. The indeterminate code is determined to be “0” or “1” so as to protect the minimum run d and the maximum run k regardless of the codeword string immediately before and immediately after. That is, in Table 2, when the two data patterns to be converted are (11), the code pattern of “000” or “101” is selected according to the code word string (channel bit string) immediately before that, and converted to one of them. Is done. For example, when one channel bit of the immediately preceding code word string is “1”, the data pattern (11) is converted to the code pattern “000” in order to protect the minimum run d, and 1 of the immediately preceding code word string. When the channel bit is “0”, the data pattern (11) is converted into the code pattern “101” so that the maximum run k is protected.

  The basic pattern of the modulation table in Table 2 has a variable length structure. In other words, the basic pattern in the constraint length i = 1 is composed of three (* 0 *, 001, and 010), which is smaller than the required number (2 ^ m = 2 ^ 2 = 4). . As a result, there is a data string that cannot be converted only with the constraint length i = 1 when the data string is converted. After all, in Table 2, in order to convert all the data strings (in order to hold as a modulation table), it is necessary to refer to the basic pattern up to the constraint length i = 3.

  Further, since the modulation table of Table 2 has a replacement pattern that restricts the continuation of the minimum run d, when the data pattern is (110111), the codeword string that follows is referred to, which is “010”. ", The six data patterns (110111) are replaced with the code pattern" 001 000 000 ". Also, this data pattern is converted into a code pattern in units of two data ((11), (01), (11)) when the code word string that follows is other than “010”. * 0 * 010 * 0 * ”is converted. As a result, the code word string obtained by converting the data is limited to the minimum run continuation, and the maximum run repeats up to 6 times at the maximum.

  The modulation table of Table 2 has a maximum constraint length r = 4. The conversion pattern with the constraint length i = 4 is composed of a replacement pattern (maximum run guarantee pattern) for realizing the maximum run k = 7. That is, the data pattern (00001000) is converted to the code pattern “000 100 100 100”, and the data pattern (00000000) is converted to the code pattern “010 100 100 100”. Also in this case, the minimum run d = 1 is maintained.

  Further, in Table 2, when a data string is terminated at an arbitrary position in order to sandwich a synchronization pattern, the termination pattern is used when the data string is terminated at (00) or (0000). In the synchronization pattern to be inserted, the first code word is the termination pattern use identification bit, and when the termination pattern is used, the first code word of the immediately following synchronization pattern string is “1”. When no termination pattern is used, “0” is set. The synchronization pattern in Table 2 consists of the above-mentioned termination pattern use identification bit and the code pattern of k = 8 exceeding the maximum run k = 7 twice for detection of the synchronization pattern, and is composed of a total of 24 code words. It is.

  By the way, the conversion pattern of Table 2 is obtained by dividing the number of “1” as an element of the data pattern by 2 and the number of “1” as the element of the code pattern to be converted by 2. The remainder has a conversion rule in which either 1 or 0 is the same (the number of “1” in each corresponding element is an odd number or an even number). For example, the data pattern (000001) in the conversion pattern corresponds to the code pattern “010 100 100”, but the number of “1” as each element is one in the data pattern and the corresponding code. In the pattern, the number is 3, and the remainder when divided by 2 is equal to 1 (odd number). Similarly, the data pattern (000000) of the conversion patterns corresponds to the code pattern “010 100 000”, but the number of “1” s is 0 for the data pattern and 0 for the corresponding code pattern, respectively. There are two, and when both are divided by 2, the remainder is equal to 0 (even number).

  Thus, the table in Table 2 is composed only of conversion patterns in which the remainder when the number of “1” s divided by 2 matches, that is, conversion patterns in which even-oddity is stored (even-oddity-preserving conversion patterns). Therefore, there is no conversion pattern in which the remainder when the number of “1” s divided by 2 does not match, that is, a conversion pattern in which even-oddity is not stored (even-oddity storage violation conversion pattern).

  Next, a method for performing DSV control will be described. Conventional DSV control in the case where DSV control is not performed in the modulation table, such as the RLL (1,7) code in Table 1, is performed by, for example, modulating a data string and then adding a predetermined value to a channel bit string after modulation. This was done by adding at least (d + 1) bits of DSV control bits at intervals. Even in the modulation table as shown in Table 2, DSV control can be performed in the same manner as in the prior art. However, DSV control can be performed more efficiently by utilizing the relationship between the data pattern and the code pattern in Table 2. That is, in the modulation table, the remainder when the number of “1” as the element of the data pattern and the number of “1” as the element of the code pattern are divided by 2 is equal to 1 or 0. When having a conversion rule, inserting a DSV control bit of “1” indicating “inverted” or “0” indicating “non-inverted” into the channel bit string as described above is included in the data bit string. If “inverted”, it is equivalent to inserting a DSV control bit of (1), and if “non-inverted”, (0).

For example, in Table 2, when 3 bits to be converted are followed by (001) and a DSV control bit is included after that, the data is (001−x) (x is 1 bit, “0” or “1”). Here, if “0” is given to x, in the modulation table of Table 2,
Data pattern Code pattern
0010 010 000
Is converted, and if "1" is given,
Data pattern Code pattern
0011 010 100
Conversion is performed. When the codeword string is converted to NRZI and the level code string is generated, these are the data pattern code pattern level code string
0010 010 000 011111
0011 010 100 011000
Thus, the last 3 bits of the level code string are mutually inverted. This means that the DSV control can be performed in the data string by selecting (1) and (0) of the DSV control bit x.

  Considering the redundancy by DSV control, DSV control with 1 bit in the data string is 1.5 channel bits from the conversion rate (m: n = 2: 3) in Table 2 when expressed in channel bit string. This is equivalent to performing DSV control. On the other hand, in order to perform DSV control in the RLL (1,7) table as shown in Table 1, it is necessary to perform DSV control in the channel bit string. At this time, in order to keep the minimum run, at least 2 channel bits are required. This is necessary, and the degree of redundancy is greater when compared with the DSV control in Table 2. In other words, when the table structure of Table 2 is used, DSV control can be performed efficiently by performing DSV control within the data string.

  The modulation table of Table 2 corresponding to a high recording density having the minimum run and the maximum run of (d, k) = (1, 7) described above is, for example, a Blu-ray Disc which is a high-density optical disc system. It is adopted as a format in ReWritable ver1.0 (registered trademark).

  Further, in the future, there is a demand for a more stable system even in the modulation system for a higher recording density, specifically, for example, a higher density standard for a high density optical disk.

  At that time, compared to the already commercialized Blu-ray Disc ReWritable ver1.0, a more stable system with the same parameters as the conventional (1,7) PP code and the same modulation table configuration. If the modulation scheme to be realized is realized, the conventional design technique can be used, and the design risk at the time of hardware design can be reduced.

JP-A-6-197024 JP-A-11-346154

  By the way, it is conceivable to limit the continuation of the minimum run of the conversion table by adopting not only the even-oddity preservation conversion pattern but also the even-oddity preservation violation conversion pattern. However, since the even-oddity preservation violation conversion pattern cannot perform DSV control, when the even-oddity preservation violation conversion pattern is converted (replaced) at the DSV control bit insertion position portion in the input data string, DSV control becomes difficult in the DSV control section of the part. At this time, the conversion processing result may output a conversion pattern for which DSV control is not performed.

  The present invention has been made in view of such a situation, and makes it possible to reliably perform DSV control even when the even-oddity preservation violation conversion pattern is adopted.

  An aspect of the present invention corresponds to a portion that matches the first data pattern of input data according to a first table that associates a first data pattern composed of an even / oddity preservation pattern with a first code pattern. A second code in a second table comprising an even-oddity preservation violation pattern from a first conversion means for converting to the first code pattern and the first code pattern converted by the first conversion means; Detection means for detecting an even-oddity preservation violation individual conversion code pattern generated by individually converting the second data pattern associated with the pattern into a code pattern, and the even-oddity preservation violation individual conversion code pattern And a second conversion means for selecting whether to perform conversion processing to the second code pattern or to use the first code pattern. It is.

  Based on the position information indicating the position where the DSV control bit is inserted and the detection result of the even-oddity preservation violation individual conversion code pattern, the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern is performed. First processing control means for generating control information to be controlled is further provided, and the second conversion means can make a selection based on the control information.

  The first processing control means prohibits the conversion processing to the second code pattern when the DSV control bit position is included in the even-oddity preservation violation individual conversion code pattern. Can be generated.

  The first process control means can further generate the control information for controlling the conversion process to the second code pattern based on information from the outside.

  The frequency of the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern is detected, and based on the detection result, the second code of the even-oddity preservation violation individual conversion code pattern A second process control unit configured to generate control information for controlling the conversion process to the pattern, and the second conversion unit is further selected using the control information generated by the second process control unit; It can be performed.

  The second processing control means further includes an individual conversion code pattern generated by individually converting the data pattern which is the first data pattern and is not included in another table having reproduction compatibility into a code pattern. The frequency of the conversion process to the corresponding first code pattern is detected, and based on the detection result, the individual conversion code pattern of the first data pattern is converted to the corresponding first code pattern. Control information for controlling conversion processing is generated, and the second conversion means further uses the control information generated by the second processing control means to use the first code pattern of the individual conversion code pattern. The conversion process can be selected.

  The second processing control means, when the usage frequency does not exceed a predetermined reference number, permits the conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern, When the reference number is exceeded, the control information can be generated so as to be prohibited.

  The second processing control means can set the reference number of times within a range where error correction is possible.

  The second process control means detects the frequency with which the even-oddity preservation violation individual conversion code pattern is converted into the second code pattern within a predetermined ECC block, and the usage frequency is The control information can be generated so as not to be larger than the reference number corresponding to a value within a range in which error correction is possible within the predetermined ECC block.

  The first table may be a table corresponding to another table having reproduction compatibility.

  The conversion process to the second code pattern may be a conversion process for limiting the continuation of the minimum run.

  The signal modulated by the modulation device can be recorded on a recording medium.

  The aspect of the present invention also provides a correspondence between the first data pattern of the even-odd storage pattern and the first data pattern corresponding to the first code pattern in accordance with the first table that associates the first code pattern with the first code pattern. The first conversion step for converting to the first code pattern and the first code pattern converted by the processing of the first conversion step, the second table comprising the even-oddity preservation violation pattern A detection step of detecting an even-oddity preservation violation individual conversion code pattern generated by individually converting a second data pattern associated with two code patterns into a code pattern; and the even-oddity preservation violation individual conversion code A second variable for selecting whether to convert the pattern into the second code pattern or to use the first code pattern. An information processing method or a program including a step.

  The program can be recorded on a recording medium.

  In the aspect of the present invention, according to the first table associating the first data pattern composed of the even-oddity preservation pattern and the first code pattern, a portion corresponding to the first data pattern of the input data corresponds. The second data pattern associated with the second code pattern in the second table consisting of the even-oddity preservation violation pattern is individually converted from the converted first code pattern. An even-oddity preservation violation individual conversion code pattern generated by conversion into a code pattern is detected. It is selected whether to perform the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern or to use the first code pattern.

  According to the aspect of the present invention, DSV control can be reliably performed even when the even-oddity preservation violation conversion pattern is adopted.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  An aspect of the present invention corresponds to a portion that matches the first data pattern of input data according to a first table that associates a first data pattern composed of an even / oddity preservation pattern with a first code pattern. First conversion means for converting to the first code pattern (for example, the RLL conversion pattern processing unit 51 in FIG. 1, FIG. 2, FIG. 3 for executing the processing in step S3 in FIG. 4, step S403 in FIG. 16 or FIG. The RLL conversion pattern processing unit 51 in FIG. 15 that executes the process of step S603 in FIG. 15 and the second table including the even-oddity preservation violation pattern from the first code pattern converted by the first conversion unit. In FIG. 2, the second data pattern (for example, the data pattern (01110111) in Table 3) associated with the second code pattern (for example, the code pattern “010 000 000 101” in Table 3) is individually encoded. Detection means (for example, FIG. 12) detects an even-oddity preservation violation individual conversion code pattern (for example, step S242 in FIG. 12 or code pattern “010 101 010 101” in step S702 in FIG. 23) generated by conversion into a pattern. 1, 2 and 3 for executing the process of step S7 in FIG. 4, and the specific rule conversion pattern detection of FIG. 15 for executing the process of step S407 in FIG. 16 or step S607 in FIG. Unit 54) and second conversion means (for example, selecting whether to perform conversion processing of the even-odd preservation violation individual conversion code pattern to the second code pattern or to use the first code pattern) The channel bit string converter 56 in FIG. 1, FIG. 2, and FIG. 3 that executes the process in step S9 in FIG. 4, and the channel bit string converter 56 in FIG. 15 that executes the process in step S410 in FIG. 16 or step S610 in FIG. With Regulating device (e.g., 1, 2, the modulation device 1 of FIG. 3 or FIG. 15) is.

  Position information (for example, DSV control bit insertion position information output by the combining unit 41 in FIG. 3 or FIG. 15) indicating the position where the DSV control bit is inserted and the detection result of the even-oddity preservation violation individual conversion code pattern (for example, Control for controlling the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern based on the specific rule conversion pattern detection flag determined in step S252 of FIG. 13 or step S722 of FIG. First process control means for generating information (for example, the specific rule conversion pattern control flag generated in steps S256 and 257 in FIG. 13 or steps 726 and S727 in FIG. 24) (for example, the process in step S8 in FIG. 4) 1, 2, and 3, and the specific rule conversion pattern processing control unit 55 in FIG. 15 that executes step S 408 in FIG. 16 or step S 608 in FIG. 19 is executed. The Provided to the second conversion means can perform the selection based on the control information.

  The first processing control means prohibits the conversion processing to the second code pattern when the DSV control bit position is included in the even-oddity preservation violation individual conversion code pattern. (For example, the processing of steps S255 to S257 in FIG. 13 or steps S725 to S727 in FIG. 24).

  The frequency of the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern is detected, and based on the detection result, the second code of the even-oddity preservation violation individual conversion code pattern Second process for generating control information (for example, the replacement pattern control flag in steps S455 and S456 in FIG. 17 or the replacement pattern control flag (2) in steps S762 and S761 in FIG. 25) for controlling the conversion process to patterns The control unit (for example, the replacement pattern processing control unit 121 in FIG. 15 that executes the processing in step S409 in FIG. 16 or step S609 in FIG. 19) is further provided, and the second conversion unit further includes the second processing control. Selection can be performed using the control information generated by the means (for example, processing in steps S482 to S484 in FIG. 18, processing in steps S789 to S791 in FIG. 26).

  The second processing control means further includes a data pattern (for example, the data pattern of Table 8) that is the first data pattern and is not included in another table (for example, the table of Table 2) that is compatible with reproduction. (1001110111)) individually converted into a code pattern, the first code corresponding to the individual conversion code pattern (for example, the code pattern “001 010 101 010 101” determined in step S682 in FIG. 22). The frequency of conversion to a pattern (for example, the code pattern “$ 0 $ 010 000 000 101” in Table 8) is detected, and the correspondence of the individual conversion code pattern of the first data pattern based on the detection result Control information for controlling the conversion process to the first code pattern (for example, the replacement pattern control flag (1) in steps S756 and S757 in FIG. 25) is generated, and the second conversion means further includes the first code pattern. 2 Using the control information generated by the processing control means, it is possible to select conversion processing of the individual conversion code pattern to the first code pattern (for example, processing in steps S781 to S788 in FIG. 26). .

  The second processing control means, when the usage frequency does not exceed a predetermined reference number, permits the conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern, When the reference number is exceeded, the control information can be generated so as to be prohibited (for example, steps S454 to S456 in FIG. 17).

  Further, according to the first aspect of the present invention, according to the first table associating the first data pattern composed of the even-oddity preservation pattern and the first code pattern, the portion corresponding to the first data pattern of the input data is associated. Is converted by the first conversion step (for example, step S3 in FIG. 4, step S403 in FIG. 16, or step S603 in FIG. 19) and the first conversion step. From the first code pattern, the second table corresponding to the second code pattern (for example, code pattern “010 000 000 101” in Table 3) in the second table composed of the even-oddity preservation violation pattern. Even-oddity preservation violation individual conversion code pattern (for example, FIG. 12) generated by individually converting a data pattern (for example, data pattern (01110111) in Table 3) to a code pattern. A detection step (for example, step S7 in FIG. 4, step S407 in FIG. 16, or step S607 in FIG. 19) for detecting the code pattern “010 101 010 101” in step S242) and the even-oddity preservation violation individual conversion code pattern A second conversion step (for example, step S9 in FIG. 4, step S410 in FIG. 16, or FIG. 16) for selecting whether to perform the conversion process to the second code pattern or to use the first code pattern 19 step S610) and an information processing method or program (for example, the modulation method or program of FIG. 4, FIG. 16, or FIG. 19).

  Embodiments of the present invention will be described below. Hereinafter, the data string (data pattern) before conversion is delimited by () as (000011), and the channel bit string (code pattern) after conversion is delimited by “” as “000 100 100”. Further, in this specification, it is a variable length code in which the minimum run d = 1, the maximum run k = 7, and the conversion rate (m: n) = (2: 3). A code with a conversion table that performs complete DSV control with efficient DSV control bits while restricting and protecting the minimum and maximum runs, is a 1,7PP code (PP: Parity-preserve Prohibit-repeated-minimum -transition-runlength).

  Table 3 below is an example of a conversion table (modulation table) as an embodiment of the present invention, and the modulation apparatus executes a process of converting the data pattern of Table 3 into a corresponding (right) code pattern. .

<Table 3>
1,7PP-rmtr5_code.rev.30 RLL (1,7; 2,3; 4)
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

i = 3 110111 001 000 000 (next010)
i = 4 01110111 (pre1) 010 000 000 101 (not010)

If xx1 then * 0 * = 000
xx0 then * 0 * = 101
-----------------------------
Sync & Termination
# 01 010 000 000 010 000 000 010 yyy yyy (30 cbits = SY_24 cbits + ID_6 cbits)
# = 0 not terminate case
# = 1 terminate case

Termination table
Data pattern Code pattern
00 000
0000 010 100

  The modulation table in Table 3 has a replacement pattern that restricts the continuation of the minimum run d at the constraint length i = 4. In the code word string after the synchronization pattern is inserted, when the data string to be converted is (01110111), the code word immediately before that is “1” and the code word string that follows is “010”. When it is not “”, the 8 data (01110111) are replaced with the code word “010 000 000 101”. Also, this data string is divided (divided) when the immediately preceding code word is “0” or the immediately following code word string is “010”, and two data (01) is converted into the code word “010”. Converted. Then, the data (110111) is converted in the next conversion process.

  Of the conversion patterns in Table 3, the data pattern (01110111) and the corresponding code pattern “010 000 000 101” are even-oddity preservation violation patterns. That is, the remainder when the number of “1” in the data pattern is divided by 2 and the remainder when the number of “1” in the corresponding code pattern is divided by 2 are 0 and 1, which do not match. Therefore, Table 3 has a specific rule that cannot perform DSV control as a conversion rule.

  By the way, when the table of Table 2 and the table of Table 3 are compared, the different parts of them, that is, the parts added by Table 3 are as shown in Table 4.

<Table 4>
Data pattern Code pattern
01110111 (pre1) 010 000 000 101 (not010)
(Pre1) means that the immediately preceding code is “1”, and (not010) means that the immediately following code is not “010” is a condition for conversion.

On the other hand, the conversion patterns in Table 3 are divided into RLL conversion patterns and replacement patterns. The replacement pattern is a pattern that limits the continuation of the minimum run, and is shown in Table 5. Table 4 is a part of the replacement pattern of Table 5.
<Table 5>
Data pattern Code pattern
110111 001 000 000 (next010)
01110111 (pre1) 010 000 000 101 (not010)
Note that (next010) means that the code immediately after “010” is a conversion condition.

  The conversion patterns (basic rule conversion patterns) in Table 3 other than the conversion patterns (specific rule conversion patterns) shown in Table 4 are even-oddity preservation patterns. That is, the remainder when the number of “1” in the data pattern is divided by 2 and the remainder when the number of “1” in the corresponding code pattern is divided by 2 are the same in 0 and 1 (corresponding to In any pattern, the number of “1” is an odd number or an even number). Therefore, Table 3 has basic rules that can basically perform DSV control as conversion rules.

Of the conversion patterns in Table 5, the conversion patterns in the following Table 6 excluding the specific rule conversion patterns are referred to as minimum run continuation restriction patterns.
<Table 6>
Data pattern Code pattern
110111 001 000 000 (next010)

The conversion table in Table 3 of the present embodiment is configured with a maximum constraint length r = 4 for the following purpose.
1. Simplification of circuit Reduction of error propagation at the time of demodulation In the case of the table configuration of Table 3, the position of the replacement process of the specific rule conversion pattern is not limited, and can exist anywhere in the input data.

  The specific rule conversion pattern shown in Table 4 cannot perform DSV control. That is, when the specific rule conversion pattern is converted (replaced) at the DSV control bit insertion position portion in the input data string, DSV control becomes difficult in the DSV control section of that part. At this time, Table 3 including Table 4 may output a result of the DSV control not being performed.

  On the other hand, the actual input data is generally randomized as a data format by a scrambler. Therefore, it can be considered that the case where the conversion process is always performed at the DSV control bit insertion position portion in the input data string for the specific rule conversion pattern of Table 4 is limited. That is, even if the conversion process is performed on the DSV control bit insertion position portion in the input data string at a certain position, the DSV control can be performed at the next DSV control bit insertion position portion. If conversion processing having basic rules is performed, DSV control is performed as a whole.

  As described above, when the code word string is generated by applying Table 3 where DSV control may not be performed as it is, the code word string includes the minimum run d = 1, the maximum run k = 7, FS (frame sync). ) Maximum run k = 8, and the continuation of the minimum run is limited to 5 times.

  However, there may be a case where the desired DSV control performance cannot be obtained due to the existence of a section in which DSV control cannot be performed. Therefore, in this embodiment, DSV control bits of DSV control bits are implemented in order to realize DSV control by applying Table 3 without giving any exception, and to realize characteristics of simplification of circuits and reduction of error propagation during demodulation. Whether or not to convert the specific rule conversion pattern at the insertion position portion is individually controlled.

  By the way, when the code word string is generated by the conversion table of Table 3, the code word string becomes a code word string different from the modulation result by the conventional 1,7PP code of Table 2, and the modulation result by the table of Table 2 is obtained. Cannot be demodulated by a conventional 1,7PP code demodulator (decoder).

  The difference between the new table in Table 3 and the conventional 1,7PP code table in Table 2 is the part shown in Table 4, and the others are the same. Therefore, in the present embodiment, since the conversion process in Table 4 is a replacement process, whether or not to perform the replacement process is individually controlled, so that the code word string according to Table 3 2 enables demodulation in the demodulator.

As an example of another table in Table 3, the condition of the previous one codeword “1” (pre1) in Table 4 cut out from Table 3 is removed, and the following Table 7 can be used. The apparatus described below can function in the same manner. In this case, the appearance frequency of this pattern is increased as compared with the case shown in Table 4.
<Table 7>
Data pattern Code pattern
01110111 010 000 000 101 (not010)

Furthermore, as an example of another table of Table 3, as shown in the following Table 8, even if a conversion pattern of constraint length i = 5 is added to Table 4 cut out from Table 3, it will be described below. Can be made to function in the same way. In this case, the degree of freedom for limiting the minimum unit of the DSV control interval can be increased.
<Table 8>
Data pattern Code pattern
01110111 (pre1) 010 000 000 101 (not010)
1001110111 $ 0 $ 010 000 000 101 (not010)
For example, $ is an indeterminate code that is “0” when the immediately preceding code is “010” and “1” when the immediately preceding code is not “010”.

  Next, an embodiment of a modulation device according to the present invention will be described with reference to the drawings.

  FIG. 1 shows the basic configuration of the modulation apparatus of the present invention. The modulation device 1 includes an encoding device 11 and a recording unit 12 that records a code string on a recording medium 13. The encoding device 11 includes a DSV control bit insertion unit 21, a modulation unit 22, a synchronization pattern insertion unit 23, and an NRZI conversion unit 24. The modulation unit 22 includes an RLL conversion pattern processing unit 51, a conversion pattern determination unit 52, a basic rule conversion pattern detection unit 53, a specific rule conversion pattern detection unit 54, a specific rule conversion pattern processing control unit 55, and a channel bit string conversion unit 56. It is configured.

  The DSV control bit insertion unit 21 inserts DSV control bits into the input data at a predetermined interval. The DSV control bit insertion unit 21 outputs a data string in which the DSV control bits are inserted, and also outputs DSV control bit insertion position information indicating the DSV control bit insertion position. The RLL conversion pattern processing unit 51 generates a codeword string that complies with the RLL rule from the input data. The conversion pattern determination unit 52 determines a conversion pattern using the RLL conversion pattern processing information and outputs a codeword string. The basic rule conversion pattern detection unit 53 detects a replacement pattern having a rule capable of performing DSV control from the input pattern.

  The specific rule conversion pattern detection unit 54 detects a replacement pattern having a rule incapable of performing DSV control from the input pattern. The specific rule conversion pattern processing control unit 55 uses the information from the DSV control bit insertion unit 21 and the information from the specific rule conversion pattern detection unit 54 to determine whether to perform specific rule conversion pattern processing, The result is output as specific rule conversion pattern processing control information. Channel bit string conversion unit 56 performs channel bit string conversion using information from conversion pattern determination unit 52, basic rule conversion pattern detection unit 53, and specific rule conversion pattern processing control unit 55, and outputs a codeword string.

The RLL conversion pattern processing unit 51 performs conversion processing of the conversion pattern of the following Table 9 among the conversion patterns of Table 3.
<Table 9>
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

The processing of the basic rule conversion pattern detection unit 53 is to detect the pattern on the left side of the following Table 10 by expressing the input as a pattern string (channel bit string). Also, the conversion from the left side to the right side of Table 10 is the operation of the channel bit string conversion unit 56.
<Table 10>
101 010 101 (next010) 001 000 000 (next010)

The processing of the specific rule conversion pattern detection unit 54 is to detect the pattern on the left side of the following Table 11 by expressing the input as a pattern string (channel bit string). Also, the conversion from the left side to the right side of Table 11 is the operation of the channel bit string conversion unit 56.
<Table 11>
(pre1) 010 101 010 101 (not010) (pre1) 010 000 000 101 (not010)

  The information is sent to the specific rule conversion pattern processing control unit 55 when the pattern on the left side of Table 11 is detected.

  The specific rule conversion pattern processing control information output from the specific rule conversion pattern processing control unit 55 is a replacement permission flag that permits replacement of the specific rule conversion pattern. If the replacement permission flag is on, when a predetermined rule conversion pattern is detected, the channel bit string converter 56 selects a conversion process based on the predetermined rule conversion pattern. On the other hand, if the replacement permission flag is off, even if the specific rule conversion pattern is detected, the channel bit string conversion unit 56 does not select the process using the specific rule conversion pattern.

  FIG. 2 shows the configuration of a more specific embodiment of the encoding device 11 of the modulation device 1 of FIG. In this embodiment, as the basic rule conversion pattern detection unit 53, a minimum run continuation restriction pattern detection unit 111 is provided, and a preceding code detection unit 62 and a comprehensive detection unit 63 are provided.

  The RLL conversion pattern processing unit 51 has a basic pattern portion in Table 3 (conversion patterns from constraint length i = 1 to i = 3) and a replacement pattern (constraint length i = 4) for realizing the minimum run k = 7. Conversion pattern), the conversion pattern processing is performed so as to observe the RLL rule, and the processing information is supplied to the conversion pattern determination unit 52. Information from the immediately preceding code detection unit 62 is used for this conversion pattern processing. Further, the RLL conversion pattern processing unit 51 has a termination table for inserting a synchronization pattern, and uses the termination table as necessary so as to terminate at a predetermined position. When the termination table is used, the information is given in the synchronization pattern.

  Based on the information from the RLL conversion pattern processing unit 51, the conversion pattern determination unit 52 selects a finally determined conversion pattern and outputs the code. The minimum run continuation restriction pattern detection unit 111 detects a pattern for limiting the continuation of the minimum run to a predetermined number of times in units of 3 channel bits, which is a basic processing unit, from the channel bit string output from the conversion pattern determination unit 52. , Output the information. The specific rule conversion pattern detection unit 54 detects a specific rule conversion pattern from the channel bit string output from the conversion pattern determination unit 52 in units of three channel bits, which is a basic processing unit, and outputs the information. The specific rule conversion pattern processing control unit 55 uses the information from the specific rule conversion pattern detection unit 54 to control whether or not to perform channel bit string conversion processing based on a pattern having a specific rule. For example, control is performed such that channel bit string conversion processing using a specific rule conversion pattern is prohibited under predetermined conditions.

  The channel bit string conversion unit 56 applies a minimum run continuation restriction pattern detection unit 111, a specific rule conversion pattern detection unit 54, and a specific rule conversion pattern processing control unit 55 to the channel bit string output from the conversion pattern determination unit 52. Using the information, replacement processing is performed in units of 3 channel bits, which are basic processing units. In the channel bit string subjected to the replacement processing, the synchronization pattern is inserted at a predetermined interval and at a predetermined position by the synchronization pattern insertion unit 23. For the determination of the synchronization pattern, termination table processing information output from the RLL conversion pattern processing unit 51 is used as necessary.

  The immediately preceding code detection unit 62 generates information necessary to guarantee RLL from the conversion pattern finally determined by the conversion pattern determination unit 52 and the synchronization pattern output by the synchronization pattern insertion unit 23, and generates an RLL conversion pattern. Supplied to the processing unit 51.

  The comprehensive detection unit 63 generates information necessary to guarantee the minimum number of continuous runs from the conversion pattern finally determined by the conversion pattern determination unit 52 and the synchronization pattern output by the synchronization pattern insertion unit 23. To the specific rule conversion pattern detection unit 54.

  Although not shown, the specific rule conversion pattern processing control unit 55 receives a clear signal, and the clear signal can clear internal information and output as necessary. In addition, a control signal is input, and processing control can be switched according to need by the control signal.

  The operation timing of each unit is managed in synchronization with a timing signal supplied from a timing management unit (not shown).

  FIG. 3 shows a more detailed configuration of the encoding device 11. The DSV control bit insertion unit 21 includes a synthesis unit 41 and a shift register 42. The RLL conversion pattern processing unit 51 includes a conversion pattern detection unit 71, conversion tables 72 (72A to 72D), a selector 73, and an indeterminate bit determination unit 74. In the modulation unit 22, the basic rule conversion pattern detection unit 53 includes a minimum run continuous limit pattern detection prediction unit 112 in addition to the minimum run continuous limit pattern detection unit 111.

  In the DSV control bit insertion unit 21, the synthesis unit 41 inserts DSV control bits into the input data at a predetermined interval. The synthesizer 41 outputs the data string in which the DSV control bits are inserted, and also outputs DSV control bit insertion position information. The input data string including the DSV control bit is shifted one data at a time by the shift register 42. Since the processing unit is 2 data units, the conversion pattern detecting unit 71 is supplied with the necessary number of bits in 2 data units. The shift register 42 holds a maximum of 8 bits.

  The conversion pattern detection unit 71 detects a conversion pattern that observes the RLL rule from the input data string, and outputs the result information to the conversion pattern determination unit 52 and also outputs it to the conversion tables 72A to 72D. The conversion tables 72A to 72D supply the detected conversion pattern (conversion channel bit string) to the conversion pattern determination unit 52. Further, the conversion pattern detection unit 71 outputs indeterminate pattern identification information to the selector 73 and the conversion pattern determination unit 52 as necessary.

  The conversion pattern determination unit 52 selects a finally determined conversion pattern based on the information from the conversion pattern detection unit 71, and outputs the code.

  When the minimum run continuation limit pattern detection unit 111 detects a pattern sequence for limiting the minimum number of consecutive runs in units of 3 channel bits, which is the basic processing unit, from the channel bit sequence output from the conversion pattern determination unit 52 The information is output to the channel bit string converter 56 as minimum run continuation restriction pattern detection information.

  The minimum run continuation limited pattern detection predicting unit 112, from the channel bit string output from the conversion pattern determining unit 52, performs the minimum run number of times at a predetermined position that is not the head for processing in units of 3 channel bits, which is a basic processing unit. When a predetermined pattern string is detected, the information is output to the specific rule conversion pattern processing control unit 55 as minimum run continuation limited pattern detection prediction information.

  The specific rule conversion pattern processing control unit 55 uses the information from the specific rule conversion pattern detection unit 54 and the information from the minimum run continuation limited pattern detection prediction unit 112 to perform channel bit string conversion processing by a pattern having a specific rule. Control whether to do or not. For example, control is performed such that channel bit string conversion processing using a specific rule conversion pattern is prohibited under predetermined conditions.

  The channel bit string conversion unit 56 uses the information from the minimum run continuation restriction pattern detection unit 111 and the specific rule conversion pattern processing control unit 55 from the channel bit string output from the conversion pattern determination unit 52 as 3 basic processing units. A predetermined channel bit string replacement process is performed in units of channel bits.

  Next, the recording method (modulation method) of the modulation device 1 of FIGS. 1 to 3 will be described with reference to the flowchart of FIG. In step S1, the synthesizing unit 41 of the DSV control bit inserting unit 21 adds the DSV control bit to the input data string and outputs the DSV control bit to the shift register 42. At this time, the synthesis unit 41 outputs DSV control bit insertion position information indicating the insertion position of the DSV control bit to the specific rule conversion pattern processing control unit 55. In step S2, the shift register 42 holds the data string to which the DSV control bit supplied from the combining unit 41 is added in units of 2 bits. In step S3, the RLL conversion pattern processing unit 51 executes conversion pattern detection processing. The details of the processing will be described in detail with reference to FIG. 5. This process converts 8 data to 12 channel bits, converts 6 data to 9 channel bits, and converts 4 data to 6 channel bits. Or a process of converting 2 data into 3 channel bits.

  Next, in step S4, the conversion pattern determination unit 52 executes conversion pattern determination processing. The details of this conversion pattern determination processing will be described later with reference to the flowchart of FIG. .

  In step S5, the minimum run continuous limit pattern detection prediction unit 112 specifies the prediction process, in step S6 the minimum run continuous limit pattern detection unit 111 specifies the minimum run continuous limit pattern detection process, and in step S7, the specific rule conversion pattern detection unit 54 specifies Each rule conversion pattern detection process is executed.

  In practice, the processes in steps S5 to S7 are executed in parallel. As will be described later, the immediately preceding code detection process of FIG. 7 by the immediately preceding code detection unit 62 and the minimum run continuation limited comprehensive detection process of FIG. 8 by the comprehensive detection unit 63 are also executed in parallel.

  The details of the prediction process in step S5 will be described later with reference to the flowchart of FIG. 10. As a result, the code pattern “101 010 101” is included from the middle (fourth bit), and the next channel bit is When it is “010”, the prediction flag is turned on. Otherwise, the prediction flag is turned off.

  Details of the minimum run continuation limited pattern detection process in step S6 will be described later with reference to the flowchart of FIG. 11, but when the code is the conversion pattern “101 010 101” and the next channel bit is “010”. In this case, the minimum run continuous restriction pattern detection flag is turned on. Otherwise, the minimum run continuation limited data detection flag is turned off.

  The details of the specific rule conversion pattern detection process in step S7 will be described later with reference to the flowchart of FIG. 12. As a result, the code matches the conversion pattern “010 101 010 101” and the immediately preceding code is “1”. If it is, the specific rule conversion pattern detection flag is turned on.

  Next, in step S8, the specific rule conversion pattern process control unit 55 executes a specific rule conversion pattern process control process. The details of the processing will be described later with reference to the flowchart of FIG. 13, whereby the specific rule conversion pattern detection flag is on, the prediction flag is off, and the code pattern corresponds to the DSV control bit. When the channel bit is not included, the specific rule conversion pattern control flag is turned on (conversion is permitted).

  In step S9, the channel bit string conversion unit 56 performs a channel bit string conversion process. The details of the channel bit string conversion process will be described later with reference to the flowchart of FIG. 14, and as a result, the channel bit string is finally determined and output. When the specific rule conversion pattern control flag is off, use of the specific rule conversion pattern is prohibited.

  In step S10, the synchronization pattern insertion unit 23 inserts the synchronization pattern into the code string for which the conversion pattern is finally determined, which is input from the channel bit string conversion unit 56. In step S11, the NRZI conversion unit 24 converts the code string in which the synchronization pattern supplied from the synchronization pattern insertion unit 23 is inserted into NRZI. In step S12, the recording unit 12 records the recording code string converted to NRZI by the NRZI converting unit 24 on the recording medium 13.

  Next, the details of the conversion pattern detection process in step S3 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S51, the conversion pattern detection unit 71 determines whether the data input from the shift register 42 matches the data patterns (00001000) and (00000000). If the input data matches the data pattern (00001000) or (00000000), in step S52, the conversion pattern detection unit 71 outputs conversion pattern determination information of 8 data / 12 channel bits. This information is supplied to the conversion pattern determination unit 52 and the conversion tables 72A to 72D. In step S53, the conversion table 72D converts 8 data into 12 channel bits. Then, the 12 channel bits are supplied to the conversion pattern determination unit 52. That is, when the input data matches the data pattern (00001000) or (00000000), the code string “000 100 100 100” or “010 100 100 100” is output, respectively. The information output in step S52 is used in step S151 of FIG. 9 described later, and the code string converted in step S53 is selected and output in step S152.

  If it is determined in step S51 that the input data does not match the data patterns (00001000) and (00000000), in step S54, the conversion pattern detection unit 71 determines that the input data is a data pattern (000011), ( It is determined whether it matches 000010), (000001), and (000000). If the input data matches any of the four, the conversion pattern detection unit 71 outputs 6 data / 9 channel bit determination information to the conversion pattern determination unit 52 and the conversion tables 72A to 72D in step S55. In step S56, the conversion table 72C converts 6 data into 9 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, if the input data is any one of the data patterns (000011), (000010), (000001), (000000), the code string “000 100 100”, “000 100 000”, “010 100 "100" and "010 100 000" are output respectively. The information output in step S55 is used in step S153 of FIG. 9, and the code string converted in step S56 is selected and output in step S154.

  If it is determined in step S54 that the input data does not match any of the data patterns (000011), (000010), (000001), (000000), the conversion pattern detection unit 71 inputs the data in step S57. It is determined whether the obtained data matches the data patterns (0011), (0010), and (0001). If the input data matches one of these three data patterns, in step S58, the conversion pattern detection unit 71 converts the conversion pattern determination information of 4 data / 6 channel bits into the conversion pattern determination unit 52 and the conversion table 72A. To 72D. In step S59, the conversion table 72B converts the 4 data into 6 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, the code string “010 100” is output when the input data matches the data pattern (0011), and the code string “010 000” is output when the input data matches the data pattern (0010). When the input data matches the data pattern (0001), the code string “000 100” is output. The information output in step S58 is used in step S155 of FIG. 9, and the code string converted in step S59 is selected and output in step S156.

  If it is determined in step S57 that the input data does not match any of the data patterns (0011), (0010), and (0001), the conversion pattern detection unit 71 in step S60 determines that the input data It is determined whether the data pattern (11), (10), or (01) matches. If the input data matches any of the three data patterns, in step S61, the conversion pattern detection unit 71 converts the conversion pattern determination information of 2 data / 3 channel bits into the conversion pattern determination unit 52 and the conversion table 72A. To 72D. This information is used in steps S157 and S158 in FIG.

  In step S62, the conversion pattern detection unit 71 determines whether the input two data matches the data pattern (11). If the input data matches the data pattern (11), the conversion pattern detection unit 71 outputs indeterminate pattern identification information to the selector 73 and the conversion pattern determination unit 52 in step S63. The indeterminate pattern identification information is used in step S82 in FIG. 6 or step S158 in FIG.

  If it is determined in step S62 that the input data does not match the data pattern (11), the process of step S63 is skipped. After the process of step S63, or when it is determined in step S62 that the data does not match the data pattern (11), in step S64, the conversion table 72A performs 2-data / 3-channel bit processing. Details of the 2-data / 3-channel bit processing are shown in the flowchart of FIG.

  Note that the data pattern (01110111), which is an even-oddity preservation violation pattern (specific rule conversion pattern), does not match the data pattern in the determination steps of steps S51, S54, and S57. In S64, the data patterns (01), (11), (01), and (11) are individually converted.

  Next, details of the 2-data / 3-channel bit processing in step S64 of FIG. 5 will be described with reference to the flowchart of FIG.

  In step S81, the conversion table 72A converts 2 data into 3 channel bits and outputs them to the selector 73. That is, the conversion table 72A outputs the code string “* 0 *” when the input data matches the data pattern (11), and when the input data matches the data pattern (10). The code word “001” is output, and if the input data matches the data pattern (01), the code word “010” is output.

  In step S82, the indeterminate bit determination unit 74 determines whether indefinite pattern identification information has been acquired. If the indeterminate pattern identification information (output in step S63 in FIG. 5) has not been acquired from the conversion pattern detection unit 71, the selector 73 outputs 3 channel bits to the conversion pattern determination unit 52 in step S83. Execute the process. Specifically, channel bits “001” and “010” input from the conversion table 72A are output to the conversion pattern determination unit 52. The code string output in step S83 is selected and output in step S160 of FIG.

  On the other hand, if it is determined in step S82 that the indeterminate pattern identification information has been acquired from the conversion pattern detection unit 71, in step S84, the selector 73 converts the three channel bits (“* 0 *”) to the indeterminate bit. The data is output to the determination unit 74. In step S85, the indeterminate bit determination unit 74 determines whether the immediately preceding code flag is on. The immediately preceding code flag is supplied from the immediately preceding code detecting unit 62 based on the processing of steps S103 and S104 in FIG. When the immediately preceding code flag is on (when one channel bit of the immediately preceding code word string is “1”), in step S86, the uncertain bit determination unit 74 includes a code word including the uncertain bit “*”. “* 0 *” is determined to be “000”, and the code word “000” is output to the conversion pattern determination unit 52. On the other hand, when the immediately preceding code flag is not on (off) (when 1 channel bit of the immediately preceding code word string is “0”), the uncertain bit determination unit 74 determines whether the code word is a code word in step S87. “* 0 *” is determined to be “101”, and the code word “101” is output to the conversion pattern determination unit 52. The code string output in steps S86 and S87 is selected and output in step S159 of FIG.

  Next, processing of the immediately preceding code detection unit 62 and the comprehensive detection unit 63 will be described with reference to the flowcharts of FIGS. 7 and 8.

  First, the immediately preceding code detection process of the immediately preceding code detection unit 62 will be described with reference to the flowchart of FIG.

  In step S101, when the synchronization pattern is inserted immediately before in the data, the immediately preceding code detection unit 62 sets the last channel bit of the insertion pattern as one channel bit of the immediately preceding code word string. That is, the immediately preceding code detection unit 62 determines whether or not a synchronization pattern has been inserted based on the output from the synchronization pattern insertion unit 23. The last one channel bit of the insertion pattern (synchronization pattern) is selected as one channel bit of the column.

  In step S102, the immediately preceding code detection unit 62 determines whether one channel bit of the code string immediately before the next conversion process is “1” from the code string provisionally determined by the conversion pattern determination unit 52. When one channel bit of the immediately preceding code string is “1”, the immediately preceding code detection unit 62 outputs the immediately preceding code flag on in step 103. On the other hand, when it is determined in step S102 that one channel bit of the immediately preceding code string is not “1” (when it is determined that it is “0”), in step S104, the immediately preceding code detection unit 62 Outputs the immediately preceding sign flag off. This immediately preceding code flag is output to the indeterminate bit determining unit 74 and used in step S85 in FIG.

  Next, the minimum run continuous limited total detection process by the total detection unit 63 will be described with reference to the flowchart of FIG.

  In step S121, when the synchronization pattern is inserted immediately before in the data, the overall detection unit 63 sets the last one channel bit of the insertion pattern as one channel bit of the immediately preceding codeword string. That is, the comprehensive detection unit 63 determines whether a synchronization pattern has been inserted based on the output from the synchronization pattern insertion unit 23, and if it has been inserted, the codeword string immediately before in the determination of the next step S122 As the one channel bit, the last one channel bit of the insertion pattern (synchronization pattern) is selected.

  In step S122, the comprehensive detection unit 63 determines from the code string determined by the conversion pattern determination unit 52 whether one channel bit of the code word string immediately before the next conversion process is “1”. If one channel bit of the immediately preceding codeword string is “1”, the comprehensive detection unit 63 outputs the minimum run continuation limited total flag on in step S123. When it is determined in step S122 that one channel bit of the immediately preceding codeword string is not “1” (in the case of “0”), in step S124, the total detection unit 63 sets the minimum run continuation limit total flag off. Is output. The minimum run continuation restriction total flag is output to the specific rule conversion pattern detection unit 54 and used in step S243 in FIG.

  In this embodiment, since the processes in FIG. 7 and FIG. 8 are the same, they may be shared. However, when other conversion tables are used, FIG. 7 and FIG. Each detection process corresponding to is performed individually.

  Next, details of the conversion pattern determination process in step S4 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S151, the conversion pattern determination unit 52 determines whether conversion pattern determination information for 8 data / 12 channel bits has been received. This determination information is output in step S52 of FIG. When the conversion pattern determination information of 8 data / 12 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 8 data / 12 channel bits in step S152. That is, the channel bit converted in step S53 in FIG. 5 is selected and output.

  If it is determined in step S151 that the conversion pattern determination information for 8 data / 12 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 6 data / 9 channel bits in step S153. Determine if it has been received. This determination information is output in step S55 of FIG. When the 6-data / 9-channel bit conversion pattern determination information is received, in step S154, the conversion-pattern determining unit 52 selects and outputs a 6-data / 9-channel bit conversion output. That is, the data output in step S56 in FIG. 5 is selected and output.

  If it is determined in step S153 that the conversion pattern determination information for 6 data / 9 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 4 data / 6 channel bits in step S155. Determine if it has been received. This determination information is output in step S58 of FIG. When the conversion pattern determination information of 4 data / 6 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 4 data / 6 channel bits in step S156. That is, the channel bit converted in step S59 in FIG. 5 is selected and output.

  If it is determined in step S155 that conversion pattern determination information for 4 data / 6 channel bits has not been received, the conversion pattern determination unit 52 converts the conversion pattern determination information for 2 data / 3 channel bits to the conversion pattern in step S157. It is determined whether it has been received from the detection unit 71. This information is output in step S61 of FIG. When the conversion pattern determination information of 2 data / 3 channel bits is received, in step S158, the conversion pattern determination unit 52 determines whether the indeterminate pattern identification information has been acquired. That is, it is determined whether the data pattern is likely to be converted into a code including an indeterminate code. If it is determined that the indeterminate pattern identification information has been acquired, in step S159, the conversion pattern determining unit 52 selects and outputs the 3 channel bits output from the indeterminate bit determining unit 74. That is, the code string output in the processing of steps S86 and S87 in FIG. 6 is selected and output.

  On the other hand, when it is determined in step S158 that the indeterminate pattern identification information has not been acquired, the conversion pattern determination unit 52 selects and outputs the 3 channel bits of the selector 73 in step S160. That is, in this case, the code string output in step S83 in FIG. 6 is selected and output.

  When the conversion pattern is determined as described above, the data string is shifted in the shift register 42 by an amount corresponding to the determined channel bit, and the conversion pattern determination process for the next data is executed.

  Next, details of the prediction process in step S5 in FIG. 4 will be described with reference to the flowchart in FIG.

  In step S181, the minimum run continuation limited pattern detection prediction unit 112 clears the prediction flag. That is, the prediction flag output in step S184 described later is cleared. In step S182, the minimum run continuation limited pattern detection prediction unit 112 determines whether the code supplied from the shift register 42 matches the code pattern “xxx 101 010 101”. If the input code matches the code pattern “xxx 101 010 101” (the code matches the code pattern “101 010 101” from the fourth bit), in step S183, the minimum run continuation limited pattern detection prediction unit 112 determines whether the next channel bit is “010”. When the next channel bit is “010”, in step S184, the minimum run continuous restriction pattern detection prediction unit 112 outputs the prediction flag on to the conversion pattern determination unit 52 as the minimum run continuous restriction data detection prediction information. . This flag is used in step S253 in FIG. 13 and step S272 in FIG.

  If it is determined in step S182 that the code does not match the code pattern “xxx 101 010 101”, or if it is determined in step S183 that the next channel bit is not “010” (“000”, “101” "Or" 001 "), in step S185, the minimum run continuation limited pattern detection prediction unit 112 outputs the prediction flag off. Since the prediction flag off is generated when the next channel bit is not “010”, the conversion process of Table 4 can be performed (when one condition for performing the conversion process is satisfied). It means that.

  Next, the minimum run continuous restriction pattern detection process in step S6 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S201, the minimum run continuation restriction pattern detection unit 111 clears the detection flag. That is, the minimum run continuation restriction pattern detection flag output in step S204 described later is cleared. In step S202, the minimum run continuation restriction pattern detection unit 111 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “101 010 101”. This code pattern “101 010 101” is an individual conversion code pattern of the data pattern (110111). If the code matches the code pattern “101 010 101”, in step S203, the minimum run continuation restriction pattern detection unit 111 determines whether the next three channel bits are “010”. If the next three channel bits are “010”, in step S204, the minimum run continuous restriction pattern detection unit 111 converts the channel bit string using the minimum run continuous restriction pattern detection flag on as the minimum run continuous restriction pattern detection information. Output to unit 56. This flag is used in step S274 of FIG.

  If it is determined in step S202 that the input code does not match the code pattern “101 010 101”, and if it is determined in step S203 that the next three channel bits are not “010”, step In S205, the minimum run continuation restriction pattern detection unit 111 outputs the minimum run continuation restriction data detection flag off to the channel bit string conversion unit 56.

  Next, the specific rule conversion pattern detection process in step S7 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S241, the specific rule conversion pattern detection unit 54 clears the detection flag. That is, the specific rule conversion pattern detection flag output in step S244 described later is cleared. In step S242, the specific rule conversion pattern detection unit 54 determines whether the code matches the code pattern “010 101 010 101”. When the code matches the code pattern “010 101 010 101”, the specific rule conversion pattern detection unit 54 determines in step S243 whether the minimum run continuation restriction total flag is on. This flag is generated by the comprehensive detection unit 63 in the processing of steps S123 and S124 in FIG. When the minimum run continuation restriction total flag is on (when the immediately preceding one channel bit is “1”), the specific rule conversion pattern detection unit 54 outputs the specific rule conversion pattern detection flag on in step S244. . This flag is used in step S252 in FIG.

  The code string “010 101 010 101” is an even-oddity preservation violation individual conversion code pattern. When the even-oddity preservation violation data pattern (01110111) is individually divided and converted in units of 2 bits (data pattern (01), (When converted as (11), (01), (11)). Further, on of the minimum run continuation limit comprehensive flag means that the immediately preceding channel bit is “1”, so that the on of the specific rule conversion pattern detection flag is an even-oddity preservation violation that constitutes the conversion pattern of the specific rule. This means that the data pattern (01110111) may be a converted code pattern.

  When it is determined in step S242 that the code does not match the code pattern “010 101 010 101”, and when it is determined in step S243 that the minimum run continuation limited total flag is not on (off) 1 channel bit is “0”), in step S245, the specific rule conversion pattern detection unit 54 outputs a specific rule conversion pattern detection flag off.

  Next, details of the specific rule conversion pattern processing control process in step S8 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S251, the specific rule conversion pattern processing control unit 55 clears the specific rule conversion pattern control flag. That is, the specific rule conversion pattern control flag output in step S257 described later is cleared. In step S252, the specific rule conversion pattern processing control unit 55 determines whether the specific rule conversion pattern detection flag is on (determines whether an even-oddity preservation violation individual conversion code pattern has been detected). This flag is output in steps S244 and S245 of FIG. When the specific rule conversion pattern detection flag is on (when the code matches the individual conversion code pattern “010 101 010 101” and the immediately preceding channel bit is “1”), a specific rule conversion pattern process is performed in step S253. The control unit 55 determines whether the prediction flag is on. If the prediction flag is not on (off) (the code does not match the code pattern “xxx 101 010 101”, or even if it matches, the next channel bit is not “010”), the specific rule in step S254 The conversion pattern processing control unit 55 handles DSV control bit position information in units of codes. That is, the specific rule conversion pattern processing control unit 55 associates the code currently being processed with the channel bit corresponding to the DSV control bit based on the DSV control bit insertion position information from the combining unit 41. If the specific rule conversion pattern detection flag is on and the prediction flag is off, it means that conversion processing to a code pattern can be performed.

  In step S255, the specific rule conversion pattern processing control unit 55 determines whether the code that is currently processed is a pattern that includes a DSV control bit. That is, it is determined whether a channel bit corresponding to the DSV control bit is inserted in the code that is currently processed. When the channel bit corresponding to the DSV control bit is not included (hereinafter, also simply referred to as the case where the DSV control bit is not included), the specific rule conversion pattern processing control unit 55 in step S257 determines the specific rule conversion pattern. Outputs control flag on.

  On the other hand, if it is determined in step S252 that the specific rule conversion pattern detection flag is off (even if the code does not match or matches the code pattern “010 101 010 101”, the previous channel bit is “ 0 ”), when it is determined in step S253 that the prediction flag is on (when the code matches the code pattern“ xxx 101 010 101 ”and the next channel bit is“ 010 ”), If it is determined in step S255 that the code currently processed is a pattern including a DSV control bit, the specific rule conversion pattern processing control unit 55 determines that the specific rule conversion pattern control flag off in step S256. Is output.

  As will be described later with reference to FIG. 14, when the specific rule conversion pattern control flag is on, the even-oddity preservation violation individual conversion code pattern “010 101 010 101” converted in step S64 of FIG. The stored violation conversion code pattern is converted to “010 000 000 101” (steps S271 and S272 in FIG. 14). On the other hand, when the specific rule conversion pattern control flag is off, the even-oddity preservation violation individual conversion code pattern is not converted into the even-oddity preservation violation conversion code pattern (the process of step S272 in FIG. 14 is not executed). Then, the even-oddity preservation violation individual conversion code pattern is output as it is (the processing after step S274 in FIG. 14 is executed). That is, the specific rule conversion pattern control flag functions as a permission flag that defines whether or not conversion processing based on the specific rule conversion pattern is permitted.

  Next, details of the channel bit string conversion process in step S9 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S271, the channel bit string conversion unit 56 determines whether the specific rule conversion pattern control flag is on. The specific rule conversion pattern control flag is output by the specific rule conversion pattern processing control unit 55 in steps S256 and S257 in FIG. When the specific rule conversion pattern control flag is on, the DSV control bit is not included in the specific rule conversion pattern (steps S255 and S257 in FIG. 13), so even if the specific rule conversion pattern is used (adopted), DSV control is never difficult. Therefore, in step S272, the channel bit string conversion unit 56 converts the even-oddity preservation violation individual conversion code pattern “010 101 010 101” into an even-oddity preservation violation code pattern (specific rule conversion pattern) “010 000 000 101”. In step S273, the channel bit string conversion unit 56 outputs the code pattern “010 000 000 101” converted in step S272.

  If it is determined in step S271 that the specific rule conversion pattern control flag is not on (off) (when the specific rule conversion pattern includes a DSV control bit), in step S274, the channel bit string conversion unit 56 Then, it is determined whether the minimum run continuous restriction pattern detection flag is on. This detection flag is output in steps S204 and S205 in FIG. When the minimum run continuation restriction pattern detection flag is on (when the code string is “101 010 101” and the next three channel bits are “010”), in step S275, the channel bit string conversion unit 56 Converts the individual conversion code pattern “101 010 101” of the data pattern (110111) into a code pattern “001 000 000” corresponding to the data pattern (110111). In step S276, the channel bit string conversion unit 56 outputs the code pattern “001 000 000” converted in step S275.

  If it is determined in step S274 that the minimum run continuation restriction pattern detection flag is not on (off) (the code string does not match “101 010 101”, or the next three channel bits are “010” even if they match. If not, in step S277, the channel bit string conversion unit 56 outputs the input channel bit string as it is. That is, in this case, the conversion pattern determined by the conversion pattern determination unit 52 is output as it is as a code string.

  When the conversion pattern is determined as described above, the determined channel bit is transmitted, and the next processing is performed. In step S277, when the input channel bit string is output as it is, three channel bits which are basic processing units are transmitted, and the next processing is performed.

  As described above, by performing the modulation processing based on Table 3, a conversion table with less error propagation at the time of demodulation is given while reducing the continuous portion of the minimum run, which is likely to become an error pattern at the time of recording and reproduction. A more stable system can be realized.

  In addition to this, the specific rule conversion pattern processing control unit 55 can also determine the conversion pattern by always turning on the specific rule conversion pattern control flag (conversion processing permission) in response to an external control signal. This is a setting that allows a slight performance degradation of the DSV control by taking advantage of the randomness of the input data, for example. Alternatively, in a system that does not require low-frequency suppression, the specific rule conversion pattern control flag may always be on. At this time, the generated recording code string is an output in which the continuous of the minimum run is limited to a maximum of 5 times, and an error pattern is likely to be generated during recording and reproduction. Can be realized.

  Also in the conversion tables other than Table 3, DSV control can be guaranteed by the specific rule conversion pattern processing control unit 55 for the specific rule conversion pattern, so that a wide selection of patterns can be selected. .

  FIG. 15 shows the configuration of another embodiment of the modulation device of the present invention. The basic configuration of this modulation apparatus 1 is the same as that shown in FIGS. 1 to 3, but in the embodiment of FIG. 15, in addition to the configuration of the embodiment of FIG. A part 121 is provided.

  The replacement pattern processing control unit 121 includes specific rule conversion pattern processing control information output from the specific rule conversion pattern processing control unit 55, minimum run continuous restriction pattern detection prediction information output from the minimum run continuous restriction pattern detection prediction unit 112, and minimum Based on the minimum run continuation restriction pattern detection information output by the run continuation restriction pattern detection unit 111, replacement pattern processing control information is generated and output to the channel bit string conversion unit 56. Other configurations are the same as those in FIG.

  Next, recording processing (modulation processing) of the modulation device 1 in FIG. 15 will be described with reference to the flowchart in FIG.

  The recording process in steps S401 to S413 in FIG. 16 is basically the same as the recording process in steps S1 to S12 in FIG. However, in FIG. 16, the replacement pattern process control process of step S409 is inserted between the specific rule conversion pattern process control process of step S408 and the channel bit string conversion process of step S410, and the channel bit string conversion of step S410 is also performed. The processing is different from that in step S9 in FIG.

  That is, the conversion pattern detection process in step S403, the conversion pattern determination process in step S404, the prediction process in step S405, the minimum run continuous restriction pattern detection process in step S406, the specific rule conversion pattern detection process in step S407, and the specification in step S408 The rule conversion pattern process control process includes a conversion pattern detection process in step S3 (FIG. 5) in FIG. 4, a conversion pattern determination process in step S4 (FIG. 9), a prediction process in step S5 (FIG. 10), and a step S6 (FIG. 11). ) Minimum run continuous limited pattern detection processing, specific rule conversion pattern detection processing in step S7 (FIG. 12), and specific rule conversion pattern processing control processing in step S8 (FIG. 13). Detailed description will be omitted because it will be repeated. Further, the processes of the immediately preceding code detection unit 62 and the comprehensive detection unit 63 are the same as those shown in FIG. 7 or FIG.

  The replacement pattern process control process in step S409 and the channel bit string conversion process in step S410 different from step S9 (FIG. 14) will be described below with reference to FIG. 17 or FIG.

  First, with reference to FIG. 17, the details of the replacement pattern processing control processing in step S409 will be described.

  In step S451, the replacement pattern processing control unit 151 clears the count at a predetermined interval (count = 0). That is, the variable count incremented in the subsequent step S453 is initialized. This process is performed for each ECC (Error-Correcting Code) block which is a unit of error correction, for example. In step S452, the replacement pattern processing control unit 121 determines whether the specific rule conversion pattern control flag is on. This flag is output in steps S256 and S257 in FIG. If the specific rule conversion pattern control flag is on (if the specific rule conversion pattern detection flag is on, the prediction flag is not on, and no DSV control bit is included), replacement is performed in step S453. The pattern processing control unit 121 increments the variable count by 1 (count = count + 1).

  In this variable count, the specific rule conversion pattern detection flag is on (the code matches the code pattern “010 101 010 101” and the immediately preceding channel bit is “1”), and the prediction flag is off. (Even if the code does not match the code pattern “xxx 101 010 101” or even if it matches, the next channel bit is not “010”), and the DSV control bit is not included in the data pattern (01110111) part It represents the number of times a state has occurred, that is, the number of conversions using a specific rule conversion pattern (frequency of use of specific rule conversion pattern).

  In step S454, the replacement pattern processing control unit 121 determines whether the variable count is greater than or equal to the reference number. If the variable count is smaller than the predetermined reference number, in step S456, the replacement pattern processing control unit 121 outputs a replacement pattern control flag on.

  On the other hand, when it is determined in step S452 that the specific rule conversion pattern control flag is not on (off) (the previous channel bit and code pattern do not match “1” + “010 101 010 101”) Or even if they match, “xxx 101 010 101” + “010” or the DSV control bit is included), or it is determined in step S454 that the count value count is greater than or equal to the reference number In step S455, the replacement pattern processing control unit 121 outputs a replacement pattern control flag off.

  As is clear from the above processing, the replacement pattern control flag on indicates that the number of conversions using the specific rule conversion pattern has not reached the reference number, and the replacement pattern control flag off indicates that the specific rule conversion pattern is off. This indicates that the number of conversions using the conversion pattern has reached the reference number.

  Note that the processing of FIG. 17 may be performed by the channel bit string converter 56. In other words, the count value count can be built in the channel bit string conversion unit 56 to perform replacement pattern control.

  As will be described later with reference to FIG. 18, when the replacement pattern control flag is on, in step S483, from the individual conversion code pattern “010 101 010 101”, the specific rule conversion pattern (even-oddity preservation violation code pattern) “ Conversion to 010 000 000 101 ″ is selected and output (that is, conversion that cannot be demodulated by the demodulation device corresponding to the conversion table in Table 2 is performed). On the other hand, when the replacement pattern control flag is off, the conversion to “010 000 000 101” is not selected, and the code pattern (data pattern (01), ( 11), (01), and (11) converted code patterns) are selected and output (that is, conversion that can be demodulated by the demodulation device corresponding to the conversion table of Table 2 is performed).

  A conversion result of a portion that cannot be demodulated by the demodulation device (conventional device) corresponding to the conversion table of Table 2 becomes a demodulation error when demodulated by the demodulation device (conventional device) corresponding to the conversion table of Table 2. Therefore, the reference number to be compared with the count value (count) in step S454 in FIG. 17 is set in advance to a predetermined value within a range in which an error occurring in the ECC block can be corrected, for example. As a result, even if conversion that cannot be demodulated by the conventional apparatus is performed, the original data string can be obtained by error correction processing in the ECC block.

  Note that if the reference count is set to the maximum value within a range in which an error that has occurred in the ECC block can be corrected, there is a risk that correction will not be possible when errors that normally occur overlap. Therefore, it is preferable to provide a margin by setting the reference count to the maximum value of the correctable range, for example, 50%.

  Next, details of the channel bit string conversion process in step S410 of FIG. 16 will be described with reference to the flowchart of FIG.

  In step S481, the channel bit string converter 56 determines whether the specific rule conversion pattern control flag is on. The specific rule conversion pattern control flag is output by the specific rule conversion pattern processing control unit 55 in steps S256 and S257 in FIG. When the specific rule conversion pattern control flag is on, the DSV control bit is not included in the specific rule conversion pattern (steps S255 and S257 in FIG. 13), so even if the specific rule conversion pattern is used (adopted), DSV control is never difficult.

  If the specific rule conversion pattern control flag is on, in step S482, the channel bit string conversion unit 56 determines whether the replacement pattern control flag is on. This flag is output by the replacement pattern processing control unit 121 in steps S455 and S456 of FIG. When the replacement pattern control flag is on (when the count value count is smaller than the reference number), in step S483, the channel bit string conversion unit 56 selects the individual data pattern (01110111) individually converted in step S64 of FIG. The conversion code pattern “010 101 010 101” is converted into a specific rule conversion pattern (even-oddity preservation violation code pattern) “010 000 000 101”, and the code pattern “010 000 000 101” is output in step S484. On the other hand, when the replacement pattern control flag is off (when the count value (count) is greater than or equal to the reference number), the processes of steps S483 and S484 are not executed.

  Also, when the specific rule conversion pattern control flag is off, the DSV control bit is included in the specific rule conversion pattern, so using (adopting) the specific rule conversion pattern may make DSV control difficult. To do. Therefore, in this case, the processes in steps S483 and S484 are not executed.

  The specific rule conversion pattern exists in the table of Table 3, and does not exist in the conventional table of Table 2 that gives reproduction compatibility. Therefore, when a code sequence using a specific rule conversion pattern is demodulated by a conventional demodulator that demodulates the code sequence modulated according to Table 2, that portion becomes a reproduction error (error). That is, reproduction compatibility is not ensured.

  Therefore, the reference number to be compared with the count value (count) in S454 in FIG. 17 is set in advance to a predetermined value within a range in which an error that has occurred can be corrected, for example. As a result, even if conversion that cannot be demodulated by the conventional apparatus is performed, the original data string can be obtained by error correction processing in the ECC block as long as the number of conversions is within a predetermined reference number.

  That is, when it is determined in step S481 that the specific rule conversion pattern control flag is off (when the specific rule conversion pattern includes a DSV control bit), or in step S482, it is determined that the replacement pattern control flag is off. If it is determined that reproduction compatibility cannot be ensured, in step S485, the channel bit string converter 56 determines whether the minimum run continuation restriction pattern detection flag is on. This minimum run continuation restriction pattern detection flag is output in step S204 of FIG. When it is determined in step S485 that the minimum run continuation limited pattern detection flag is on (when the code matches the code pattern “101 010 101” and the next channel bit is “010”), step S486 5, the channel bit string conversion unit 56 converts the individual conversion code pattern “101 010 101” of the data pattern (110111) individually converted in step S64 of FIG. 5 into the code pattern “001 000 000” corresponding to the data pattern (110111). In step S487, the code pattern “001 000 000” is output.

  If it is determined in step S485 that the minimum run continuation restriction pattern detection flag is off (the code does not match the code pattern “101 010 101” or even if it matches, the next channel bit is not “010”) In step S488, the channel bit string conversion unit 56 outputs the input channel bit string as it is.

  When the conversion pattern is determined as described above, the determined channel bit is transmitted, and the next processing is performed. In step S488, if the input channel bit string is output as it is, three channel bits that are basic processing units are sent, and the next processing is performed.

  As a modification of the embodiment of FIG. 15, the output from the immediately preceding code detection unit 62 may be sent to the channel bit string conversion unit 56, and the processing of the indeterminate bit determination unit 74 may be performed by the channel bit string conversion unit 56. Further, the output from the general detection unit 63 sent to the specific rule conversion pattern detection unit 54 is sent to the channel bit string conversion unit 56, and the conversion pattern determined immediately before is determined by the specific rule conversion pattern detection unit 54 Alternatively, the channel bit string conversion unit 56 may perform processing for determining whether the final code word of the synchronization pattern is “1” (pre1). In this way, the same result can be obtained by moving the detection operation in each detection unit in FIG. 15 and the determination operation in the conversion pattern determination unit 53.

  As described above, the basic configuration is the same as that of the 1,7PP code, that is, the minimum run d = 1, the maximum run k = 7, and the conversion rate (m: n) = (2: 3). DSV control is efficiently performed by inserting one DSV control bit at a predetermined position in the area, and the number of consecutive minimum runs even when a synchronization pattern with a predetermined identification bit is inserted. Thus, it is possible to realize a conversion table and a modulation device that improve error propagation characteristics during recording and reproduction.

  Further, by adopting the configuration as shown in FIG. 3, even in a table including an even-oddity preservation violation pattern as shown in Table 3, the even-oddity preservation violation pattern is used at the position where the DSV control bit is inserted. You can turn off conversion. Therefore, reliable DSV control can be performed.

  Furthermore, with the configuration as shown in FIG. 15, the number of conversions shown in Table 4 is counted within a predetermined ECC block interval, and the flag is turned on (permitted) until the reference number of times. When the reference number of times is exceeded, the flag can be turned off (prohibited). Therefore, it is possible to manage the frequency with which the replacement patterns in Table 4 are performed so that reproduction compatibility with Table 2 is given.

  That is, by performing the modulation process based on Table 3, it is possible to provide a more stable system by reducing the continuous part of the minimum run, which is likely to become an error pattern at the time of recording and reproduction, and performing the DSV control reliably. Furthermore, it is possible to perform demodulation using not only the demodulator based on Table 3 but also the demodulator based on Table 2. For example, a product including a format including the table of Table 2 has already been commercialized. Also in the demodulating device, it is possible to reproduce the code string recorded using the format including the table of Table 3 according to the present embodiment.

  Indeterminate codes $, * in Table 3 may be determined using not only the immediately preceding code but also the immediately following code in order to satisfy a desired condition for the table.

  Further, in the replacement pattern processing control process of FIG. 15, the number of conversion patterns in Table 4 is one here, but in the case where there are two conversion tables in other tables, for example, the number of conversions of both is counted, What is necessary is just to compare the sum total with the reference | standard frequency | count. Furthermore, in this case, different weights may be assigned to the prohibition of use of the two conversion patterns, or one of them may be prohibited.

  In addition, a modulation device incorporating the table of Table 3 can switch and output a codeword string based on the format of Table 3 or Table 2 based on an external control signal. For example, the replacement pattern processing control unit 121 in FIG. 15 outputs information for prohibiting or permitting the conversion processing for the replacement pattern based on an external control signal (not shown). In this way, when prohibition is instructed from the outside, the channel bit string converter 56 is prohibited from performing a predetermined replacement process, and the output from the channel bit string converter 56 is encoded based on the table in Table 2. It can be a word string.

  In the above description, the case where data is modulated based on the table in Table 3 has been described. Next, in Table 3, the part described in Table 4 is configured as shown in Table 8 (Table 3. When modulation is performed using a table in which the portion described in Table 4 is replaced with the portion described in Table 8 (hereinafter, this table is referred to as the table in Table 3 (8) for convenience) Will be described with reference to FIGS. 19 to 26. FIG.

  In this case, the configuration of the modulation device 1 is the same as that shown in FIG.

  The recording process in the case of modulation using Table 3 (8) is as shown in the flowchart of FIG. The processes in steps S601 to S613 in FIG. 19 are basically the same as the processes in steps S401 to S413 in FIG. However, the processing in the subroutine of steps S605 to S610 is different from the processing in the subroutine of steps S405 to S410 in FIG. Only different processes will be described below.

  The immediately preceding code detection process by the immediately preceding code detection unit 62 in this case is the same as that shown in FIG. 7, but the minimum run continuation limited comprehensive detection process by the comprehensive detection unit 63 is different from that in FIG. First, the minimum run continuous limited total detection process by the total detection unit 63 will be described with reference to the flowchart of FIG.

  In step S631, when the synchronization pattern is inserted immediately before, the total detection unit 63 sets the last three channel bits of the insertion pattern as the three channel bits of the immediately preceding codeword string. That is, the comprehensive detection unit 63 determines whether a synchronization pattern has been inserted based on the output from the synchronization pattern insertion unit 23, and if it has been inserted, the codeword string immediately before in the determination of the next step S632 As the three channel bits, the last three channel bits of the insertion pattern (synchronization pattern) are selected.

  In step S632, the comprehensive detection unit 63 determines from the code string information from the conversion pattern determination unit 52 whether the three channel bits of the code word string immediately before the next conversion process are “010”. If the three channel bits of the immediately preceding codeword string are “010”, the comprehensive detection unit 63 outputs the minimum run continuation limited total flag (1) on in step S633. When it is determined in step S632 that the three channel bits of the immediately preceding codeword string are not “010” (in the case of “000”, “101”, “001”), in step S634, the total detection unit 63 , Output the minimum run continuation limit comprehensive flag (1) off. The minimum run continuous restriction total flag (1) is used in step S784 of FIG.

  In step S635, the comprehensive detection unit 63 determines whether one channel bit of the codeword string immediately before the next conversion process is “1” from the code string information from the conversion pattern determination unit 52. If the one channel bit of the immediately preceding codeword string is “1”, the comprehensive detection unit 63 outputs the minimum run continuation limited total flag (2) on in step S636. When it is determined in step S635 that one channel bit of the immediately preceding codeword string is not “1” (when it is “0”), in step S637, the total detection unit 63 determines that the minimum run continuation limited total flag ( 2) Output off. The minimum run continuation restriction total flag (2) is output to the specific rule conversion pattern detection unit 54 and used in step S703 in FIG.

  Next, details of the prediction process in step S605 of FIG. 19 will be described with reference to the flowchart of FIG.

  In step S651, the minimum run continuation limited pattern detection prediction unit 112 clears the prediction flag. That is, the prediction flags (C7) and (C4) output in steps S654 and S657 described later are cleared. In step S652, the minimum run continuation limited pattern detection prediction unit 112 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “xxx xxx 101 010 101”. If the input code matches the code pattern “xxx xxx 101 010 101” (the code matches the code pattern “101 010 101” from the seventh bit), in step S653, the minimum run continuation limited pattern detection prediction The unit 112 determines whether the next channel bit is “010”. When the next channel bit is “010”, the minimum run continuation limited pattern detection prediction unit 112 outputs the prediction flag (C7) on to the replacement pattern processing control unit 121 in step S654. This flag is used in step S753 of FIG.

  If it is determined in step S652 that the code does not match the code pattern “xxx xxx 101 010 101”, in step S655, the minimum run continuation limited pattern detection prediction unit 112 determines that the code is the code pattern “xxx 101 010 101”. Determine whether they match. If the input code matches the code pattern “xxx 101 010 101” (the code matches the code pattern “101 010 101” from the fourth bit), in step S656, the minimum run continuation limited pattern detection prediction unit 112 determines whether the next channel bit is “010”. If the next channel bit is “010”, in step S657, the minimum run continuation limited pattern detection prediction unit 112 performs specific rule conversion pattern processing using the prediction flag (C4) on as the minimum run continuation limited data detection prediction information. Output to the control unit 55. This flag is used in step S723 of FIG. 24 described later.

  If it is determined in step S653 that the next channel bit is not “010” (“000”, “101”, or “001”), in step S655, the code is a code pattern “xxx 101 010 101”. ", Or when it is determined in step S656 that the next channel bit is not" 010 "(" 000 "," 101 ", or" 001 "), step S658 The minimum run continuation limited pattern detection prediction unit 112 outputs the prediction flag off. This prediction flag off means that the prediction flag (C7) generated in step S654 is off, and also means that the prediction flag (C4) generated in step S657 is off.

  Next, the minimum run continuation restriction pattern detection process in step S606 of FIG. 19 will be described with reference to the flowchart of FIG.

  In step S681, the minimum run continuation restriction pattern detection unit 111 clears the detection flag. That is, the minimum run continuation limit pattern detection flags 15 and 12 output in steps S683 and S686 described later are cleared. In step S682, the minimum run continuation restriction pattern detection unit 111 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “001 010 101 010 101”. This code pattern “001 010 101 010 101” is obtained when the data pattern (1001110111) is individually converted into a code pattern (data pattern (10), (01), (11), (01), (11) This is an individual conversion code pattern generated when converted into a pattern. If the input code matches the code pattern “001 010 101 010 101”, in step S683, the minimum run continuous restriction pattern detection unit 111 detects the minimum run continuous restriction pattern detection flag 15on and detects the minimum run continuous restriction pattern. The information is output to the replacement pattern processing control unit 121 as information. This flag on means that the data pattern (1001110111) may be a converted code pattern. This flag is used in step S752 of FIG. 25 described later.

  When it is determined in step S682 that the code does not match the code pattern “001 010 101 010 101”, in step S684, the minimum run continuation limited pattern detection unit 111 matches the code pattern “101 010 101”. Determine whether. This code pattern “101 010 101” is generated when the data pattern (110111) is individually converted to a code pattern (when converted to a code pattern as data patterns (11), (01), and (11)). It is an individual conversion code pattern. If the input code matches the code pattern “101 010 101”, in step S685, the minimum run continuation restriction pattern detection unit 111 determines whether the next three channel bits are “010”. If the next three channel bits are “010”, in step S686, the minimum run continuous restriction pattern detection unit 111 converts the channel bit string using the minimum run continuous restriction pattern detection flag 12on as the minimum run continuous restriction pattern detection information. Output to unit 56. On of this flag means that the data pattern (110111) is a converted code pattern. This flag is used in step S792 of FIG. 26 described later.

  If it is determined in step S684 that the input code does not match the code pattern “101 010 101”, and if it is determined in step S685 that the next three channel bits are not “010”, step In S687, the minimum run continuation restriction pattern detection unit 111 outputs the minimum run continuation restriction data detection flag off to the replacement pattern processing control unit 121 and the channel bit string conversion unit 56. The off of the minimum run continuation restriction data detection flag means that the minimum run continuation restriction pattern detection flag 15 is off and that the minimum run continuation restriction pattern detection flag 12 is off.

  Details of the specific rule conversion pattern detection processing in step S607 of FIG. 19 are as shown in FIG. The processes in steps S701 to S705 are basically the same as those in steps S241 to S245 in FIG. However, in step S253 in FIG. 12, it is determined whether the minimum run continuous restriction total flag is on, whereas in corresponding step S703 in FIG. 23, it is determined whether the minimum run continuous restriction total flag (2) is on. Is done. This minimum run continuous restriction total flag (2) is generated in step S636 of FIG. 20, and is a flag having substantially the same meaning as the minimum run continuous restriction total flag generated in step S123 of FIG. is there. Accordingly, the processing in steps S701 through S705 in FIG. 23 is substantially the same as the processing in steps S241 through S245 in FIG.

  Details of the specific rule conversion pattern processing control processing in step S608 of FIG. 19 are as shown in FIG. The processes in steps S721 to S727 are basically the same as those in steps S251 to S257 in FIG. However, in step S253 in FIG. 13, it is determined whether the prediction flag is on, whereas in the corresponding step S723 in FIG. 24, it is determined whether the prediction flag (C4) is on. The prediction flag (C4) is generated in step S657 in FIG. 21, and has substantially the same meaning as the prediction flag generated in step S184 in FIG. Therefore, the processing in steps S721 to S727 in FIG. 24 is substantially the same as the processing in steps S251 to S257 in FIG.

  Next, with reference to FIG. 25, the replacement pattern process control process in step S609 of FIG. 19 will be described. In step S751, the replacement pattern processing control unit 121 clears the counts (count1, count2) at predetermined intervals. That is, variables count1 and count2 used in steps S754 and S759 described later are initialized here. This process is performed, for example, for each ECC (Error-Correcting Code) block that is a unit for correcting an error in the code string.

  In step S752, the replacement pattern processing control unit 121 determines whether the minimum run continuation limited pattern detection flag 15 is on. This flag is output in steps S683 and S687 in FIG. When the minimum run continuation restriction pattern detection flag 15 is on (when the code matches the individual conversion code pattern “001 010 101 010 101” of the data pattern (1001110111)), in step S753, the replacement pattern processing control unit 121 Whether the prediction flag (C7) is on is determined. This flag is output in steps S654 and S658 of FIG.

  When the prediction flag (C7) is not on (off) (when the code does not match the code pattern “xxx xxx 101 010 101” or even if it matches, the next channel bit is not “010”), In step S754, the replacement pattern processing control unit 121 increments the variable count1 by 1 (count1 = count1 + 1). In step S755, the replacement pattern processing control unit 121 determines whether (count1 + count2) is greater than or equal to the reference number. When the count value (count1 + count2) is smaller than a predetermined reference number (reference value), the replacement pattern processing control unit 121 turns on the replacement pattern control flag (1) in step S757. On the other hand, when the count value (count1 + count2) is equal to or greater than the reference number, when it is determined in step S752 that the minimum run continuation restriction pattern detection flag 15 is off, and in step S753, the prediction flag (C7) When it is determined that is on, the replacement pattern processing control unit 121 turns off the replacement pattern control flag (1) in step S756. The replacement pattern control flag (1) is used in step S781 of FIG.

  Further, after the processing in steps S756 and S757, in step S758, the replacement pattern processing control unit 121 determines whether the specific rule conversion pattern control flag is on. This flag is output in steps S727 and S726 of FIG. When the specific rule conversion pattern control flag is on (when the code matches the individual conversion code pattern “010 101 010 101” and the immediately preceding code is “1”, and the prediction flag (C4) is off In the case where the pattern further does not include the DSV control bit), in step S759, the replacement pattern processing control unit 121 increments the variable count2 by 1 (count2 = count2 + 1). In step S760, the replacement pattern processing control unit 121 determines whether (count1 + count2) is equal to or greater than the reference number. When the count value (count1 + count2) is smaller than the reference number (reference value), the replacement pattern processing control unit 121 outputs a replacement pattern control flag (2) on in step S762. On the other hand, when the count value (count1 + count2) is equal to or greater than the reference value, and when it is determined in step S758 that the specific rule conversion pattern control flag is off, the replacement pattern processing control unit 121 in step S761 The replacement pattern control flag (2) off is output. The replacement pattern control flag (2) is used in step S789 of FIG.

  The variable count1 corresponds to, for example, the number of times when the state in which the minimum run continuation restriction pattern detection flag 15 is on and the prediction flag (C7) is off, that is, the data pattern (1001110111) in the ECC block. This represents the number of times (usage frequency) that can be converted into the code pattern “$ 0 $ 010 000 000 101”. count2 is the number of times when the specific rule conversion pattern control flag is on, that is, the even-oddity preservation violation data pattern (01110111) can be converted into the corresponding even-oddity preservation violation code pattern “010 000 000 101” Indicates the number of times (frequency of use). The count value (count1 + count2) shows the number of times pattern conversion can be performed using the conversion table of Table 8.

  As will be described later with reference to FIG. 26, when the replacement pattern control flag (1) (permission flag) is on, in step S782, the individual data pattern (1001110111) converted in steps S159 and S160 of FIG. The converted code pattern “001 010 101 010 101” is converted to the code pattern “$ 0 $ 010 000 000 101” and the code string “$ 0 $” including the indeterminate bit is determined, and then the code is encoded in steps S786 and S788. The patterns “101 010 000 000 101” and “000 010 000 000 101” are selected and output (that is, conversion that cannot be demodulated by the demodulation device corresponding to the conversion table in Table 2 is performed). On the other hand, when the replacement pattern control flag (1) (permission flag) is off, the code patterns “101 010 000 000 101” and “000 010 000 000 101” are not selected and the data pattern (1001110111) The individual conversion code pattern “001 010 101 010 101” is selected and output as it is (that is, conversion that can be demodulated by the demodulation device corresponding to the conversion table of Table 2 is performed).

  Similarly, when the replacement pattern control flag (2) (permission flag) is on, in steps S790 and S791 in FIG. 26, the even-oddity preservation violation data pattern (01110111) is converted in steps S159 and S160 in FIG. The individual conversion code pattern “010 101 010 101” is converted into an even-oddity preservation violation code pattern “010 000 000 101”, and is selected and output (that is, conversion that cannot be demodulated by the demodulation device corresponding to the conversion table of Table 2) Is done). On the other hand, when the replacement pattern control flag (2) (permission flag) is off, the code pattern “010 000 000 101” is not selected, and the individual conversion code pattern “010 101 010 101” of the data pattern (01110111) is not selected. "Is selected and output (that is, conversion that can be demodulated by the demodulation device corresponding to the conversion table of Table 2 is performed).

  The conversion result of the portion that cannot be demodulated by the demodulator (conventional device) corresponding to the conversion table of Table 2 is a demodulation error. Therefore, the reference number to be compared with the count value (count1 + count2) in steps S755 and S760 in FIG. 25 is determined in advance as a predetermined value within a range in which, for example, an error that has occurred can be corrected. Keep it. As a result, even if conversion that cannot be demodulated by the conventional apparatus is performed, the original data string can be obtained by error correction processing in the ECC block.

  Next, the details of the channel bit string conversion process in step S610 of FIG. 19 will be described with reference to the flowchart of FIG.

  In step S781, the channel bit string converter 56 determines whether the replacement pattern control flag (1) is on. This flag is generated by the replacement pattern processing control unit 121 in steps S757 and S756 of FIG.

  When the replacement pattern control flag (1) (permission flag) is on (when the count value (count1 + count2) is smaller than the reference number), in step S782, the channel bit string conversion unit 56 performs steps S159 and S160 in FIG. The individual conversion code pattern “001 010 101 010 101” obtained by converting the data pattern (1001110111) is converted into the original code pattern “$ 0 $ 010 000 000 101”.

  Further, in step S783, the channel bit string converter 56 determines whether the immediately preceding code flag is on. This immediately preceding code flag is output in steps S103 and S104 in FIG. When the immediately preceding code flag is on (when 1 channel bit of the immediately preceding code word string is “1”), in step S787, the channel bit string converting unit 56 does not include the error included in the code string converted in step S782. The confirmed codeword “$ 0 $” is set to “000”. In step S788, the channel bit string converting unit 56 outputs the code string “000 010 000 000 101”.

  If it is determined in step S783 that the immediately preceding code flag is not on (off) (when one channel bit of the immediately preceding codeword string is “0”), in step S784, the channel bit string converting unit 56 It is determined whether the minimum run continuous restriction total flag (1) is on. The minimum run continuation limit comprehensive flag (1) is output in steps S633 and S634 in FIG. When the minimum run continuation restriction total flag (1) is on (when the three channel bits of the immediately preceding codeword string are “010”), as in the case where the immediately preceding code flag is on, step S787, The process of S788 is executed.

  On the other hand, when it is determined that the minimum run continuation restriction total flag (1) is not on (is off) (when the three channel bits of the immediately preceding codeword string are not “010”), in step S785 The channel bit string conversion unit 56 converts the indeterminate code word “$ 0 $” converted in step S782 into “101”. In step S786, the channel bit string converter 56 outputs the code string “101 010 000 000 101”.

  If it is determined in step S781 that the replacement pattern control flag (1) is not on (off), in step S789, the channel bit string converter 56 determines whether the replacement pattern control flag (2) (permission flag) is on. Determine. When the replacement pattern control flag (2) (permission flag) is on (when the count value (count1 + count2) is smaller than the reference number), in step S790, the channel bit string conversion unit 56 in steps S159 and S160 in FIG. The converted individual conversion code pattern “010 101 010 101” is converted into the original even-oddity preservation violation decoding code pattern “010 000 000 101”. In step S791, the channel bit string conversion unit 56 outputs the converted code string “010 000 000 101”.

  If it is determined in step S789 that the replacement pattern control flag (2) (permission flag) is not on (is off), in step S792, the channel bit string conversion unit 56 determines that the minimum run continuation restriction pattern detection flag 12 is on. Determine whether. This detection flag is output in steps S686 and S687 in FIG. When the minimum run continuation restriction pattern detection flag 12 is on (when the code string is “101 010 101” and the next three channel bits are “010”), a channel bit string conversion unit in step S793 56 converts the individual conversion code pattern “101 010 101” of the data pattern (110111) converted in steps S159 and S160 of FIG. 9 into the original code pattern “001 000 000”. In step S794, the channel bit string conversion unit 56 outputs the code string “001 000 000” converted in step S793.

  When it is determined in step S792 that the minimum run continuation restriction pattern detection flag 12 is not on (is off) (the code string is not “101 010 101”, or even so, the next three channel bits In step S795, the channel bit string converting unit 56 outputs the input channel bit string as it is. That is, in this case, the conversion pattern determined by the conversion pattern determination unit 52 is output as it is as a code string.

  As described above, the basic configuration is the same as that of the 1,7PP code, that is, the minimum run d = 1, the maximum run k = 7, and the conversion rate (m: n) = (2: 3). DSV control is efficiently performed by inserting one DSV control bit at a predetermined position in the area, and the number of consecutive minimum runs even when a synchronization pattern with a predetermined identification bit is inserted. Thus, it is possible to realize a conversion table and a modulation device that improve error propagation characteristics during recording and reproduction.

The 1,7PP code is provided with a replacement pattern that limits the number of repetitions of the minimum run length in the modulation table of minimum run d = 1, maximum run k = 7, and conversion rate (m: n) = (2: 3). Because
(1) The tolerance for recording / reproduction at high linear density and tangential tilt is improved.
(2) The portion with a low signal level is reduced, the accuracy of waveform processing such as AGC (Auto Gain Control) and PLL (Phase-Locked Loop) is improved, and the overall characteristics can be enhanced.
(3) Compared with the prior art, the path memory length for Viterbi decoding or the like can be designed to be short, and the circuit scale can be reduced.

Further, by performing conversion pattern determination processing using the specific rule conversion pattern control flag, the number of data strings “1” constituting the conversion pattern of the modulation table and the codeword string at the position where the DSV control bit is inserted. Since the remainder when dividing the number of “1” in 2 by 2 is 1 or 0,
(4) Redundant bits for DSV control can be reduced.
(5) In the minimum run d = 1 and (m, n) = (2,3), DSV control can be performed with 1.5 codewords.
(6) The redundancy is low and the minimum run and the maximum run can be protected. Furthermore, the table in Table 4 reduces the error propagation at the time of data recording / reproduction because the number of continuous runs for the minimum run is reduced from 6 to 5 times compared to the 1,7PP code in Table 2. it can.

  As described above, as a data reproduction error pattern, there is a case in which errors from the first edge to the last edge of consecutive minimum marks are erroneously shifted. That is, the generated bit error length propagates from the beginning to the end of the continuous section of the minimum run. Therefore, the problem that the error propagation becomes long appears. However, by limiting the continuous minimum run to five times, the occurrence of such errors can be reduced, and more stable data recording and reproduction can be realized.

  FIG. 27 is a block diagram showing an example of the configuration of a personal computer that executes the above-described series of processing by a program. A CPU (Central Processing Unit) 321 executes various processes according to a program stored in a ROM (Read Only Memory) 322 or a storage unit 328. A RAM (Random Access Memory) 323 appropriately stores programs executed by the CPU 321 and data. The CPU 321, ROM 322, and RAM 323 are connected to each other via a bus 324.

  An input / output interface 325 is also connected to the CPU 321 via the bus 324. Connected to the input / output interface 325 are an input unit 326 made up of a keyboard, mouse, microphone, and the like, and an output unit 327 made up of a display, speakers, and the like. The CPU 321 executes various processes in response to commands input from the input unit 326. Then, the CPU 321 outputs the processing result to the output unit 327.

  The storage unit 328 connected to the input / output interface 325 includes, for example, a hard disk, and stores programs executed by the CPU 321 and various data. The communication unit 329 communicates with an external device via a network such as the Internet or a local area network. Further, the program may be acquired via the communication unit 329 and stored in the storage unit 328.

  The drive 330 connected to the input / output interface 325 drives a removable medium 331 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives the program or data recorded therein. Get etc. The acquired program and data are transferred to and stored in the storage unit 328 as necessary.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, the program is installed in a general-purpose personal computer from the program storage medium.

  As shown in FIG. 27, a program storage medium for storing a program that is installed in a computer and can be executed by the computer is a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (including Digital Versatile Disc)), magneto-optical disk (including MD (Mini-Disc) (registered trademark)), or removable media 331, which is a package media composed of semiconductor memory, or a program is temporarily stored A ROM 322 that is stored in a permanent or permanent manner, a hard disk that constitutes the storage unit 328, or the like. The program is stored in the program storage medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 329 that is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the program storage medium is not limited to the processing performed in time series according to the described order, but is not necessarily performed in time series. Or the process performed separately is also included.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the modulation apparatus of one embodiment of this invention. It is a block diagram which shows the more detailed structure of the encoding apparatus of FIG. FIG. 3 is a block diagram showing an even more detailed configuration of the encoding device of FIG. 2. It is a flowchart explaining a recording process. It is a flowchart explaining the conversion pattern detection process of step S3 of FIG. 6 is a flowchart for explaining 2-data / 3-channel bit processing in step S64 of FIG. 5. It is a flowchart explaining the immediately preceding code detection process. It is a flowchart explaining a minimum run continuation restriction comprehensive detection process. It is a flowchart explaining the conversion pattern determination process of step S4 of FIG. It is a flowchart explaining the prediction process of step S5 of FIG. 5 is a flowchart for explaining a minimum run continuation restriction pattern detection process in step S6 of FIG. 4. It is a flowchart explaining the specific rule conversion pattern detection process of step S7 of FIG. 5 is a flowchart for explaining a specific rule conversion pattern process control process in step S8 of FIG. 5 is a flowchart for explaining a channel bit string conversion process in step S9 of FIG. It is a block diagram which shows the structure of other embodiment of the modulation apparatus of this invention. It is a flowchart explaining a recording process. FIG. 17 is a flowchart for describing replacement pattern processing control processing in step S409 of FIG. FIG. 17 is a flowchart illustrating channel bit string conversion processing in step S410 of FIG. It is a flowchart explaining another recording process. It is a flowchart explaining the other minimum run continuous restriction total detection processing. FIG. 20 is a flowchart for describing the prediction processing in step S605 of FIG. FIG. 20 is a flowchart for describing a minimum run continuation restriction pattern detection process in step S606 of FIG. It is a flowchart explaining the specific rule conversion pattern detection process of step S607 of FIG. FIG. 20 is a flowchart illustrating a specific rule conversion pattern process control process in step S608 of FIG. FIG. 20 is a flowchart illustrating a replacement pattern processing control process in step S609 of FIG. 20 is a flowchart illustrating channel bit string conversion processing in step S610 of FIG. It is a block diagram which shows the structure of a personal computer.

Explanation of symbols

  1 Modulator, 11 Encoder, 21 DSV Control Bit Insertion Unit, 22 Modulation Unit, 23 Synchronization Pattern Insertion Unit, 24 NRZI Conversion Unit, 41 Combining Unit, 51 RLL Conversion Pattern Processing Unit, 52 Conversion Pattern Determination Unit, 53 Basic Rule conversion pattern detection unit, 54 Specific rule conversion pattern detection unit, 55 Specific rule conversion pattern processing control unit, 56 Channel bit string conversion unit, 62 Immediate code detection unit, 63 Total detection unit, 71 Conversion pattern detection unit, 72A to 72D conversion Table, 73 Selector, 74 Undetermined bit decision section

Claims (15)

According to the first table that associates the first data pattern composed of the even-oddity preservation pattern with the first code pattern, the portion corresponding to the first data pattern of the input data is changed to the corresponding first code pattern. First conversion means for converting to
From the first code pattern converted by the first conversion means, the second data pattern associated with the second code pattern in the second table including the even-oddity preservation violation pattern is individually encoded. Detection means for detecting an even-oddity preservation violation individual conversion code pattern generated by converting into a pattern;
A modulation apparatus comprising: second conversion means for selecting whether to perform conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern or to use the first code pattern. Based on the position information indicating the position where the DSV control bit is inserted and the detection result of the even-oddity preservation violation individual conversion code pattern, the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern is performed. A first process control means for generating control information to be controlled;
The modulation device according to claim 1, wherein the second conversion unit performs selection based on the control information. The first processing control means prohibits the conversion processing to the second code pattern when the DSV control bit position is included in the even-oddity preservation violation individual conversion code pattern. The modulation device according to claim 2. The modulation apparatus according to claim 2, wherein the first process control unit further generates the control information for controlling the conversion process to the second code pattern based on information from the outside. The frequency of the conversion process of the even-oddity preservation violation individual conversion code pattern to the second code pattern is detected, and based on the detection result, the second code of the even-oddity preservation violation individual conversion code pattern A second process control means for generating control information for controlling the conversion process to the pattern;
The modulation apparatus according to claim 2, wherein the second conversion unit further performs selection using the control information generated by the second processing control unit. The second processing control means further includes an individual conversion code pattern generated by individually converting the data pattern which is the first data pattern and is not included in another table having reproduction compatibility into a code pattern. The frequency of the conversion process to the corresponding first code pattern is detected, and based on the detection result, the individual conversion code pattern of the first data pattern is converted to the corresponding first code pattern. Generate control information to control the conversion process,
6. The second conversion unit further selects conversion processing of the individual conversion code pattern into the first code pattern using the control information generated by the second processing control unit. The modulation device according to 1. The second processing control means, when the usage frequency does not exceed a predetermined reference number, permits the conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern, The modulation device according to claim 5, wherein the control information is generated so as to be prohibited when a reference number of times is exceeded. The modulation apparatus according to claim 7, wherein the second processing control unit sets the reference count to be limited within a range in which error correction is possible. The second process control means detects the frequency with which the even-oddity preservation violation individual conversion code pattern is converted into the second code pattern within a predetermined ECC block, and the usage frequency is The modulation device according to claim 8, wherein the control information is generated so as not to be larger than the reference number corresponding to a value within a range in which error correction is possible within the predetermined ECC block. The modulation device according to claim 1, wherein the first table is a table corresponding to another table having reproduction compatibility. The modulation device according to claim 1, wherein the conversion process to the second code pattern is a conversion process for limiting the continuation of the minimum run.   A recording medium on which a signal modulated by the modulation device according to claim 1 is recorded. According to the first table that associates the first data pattern composed of the even-oddity preservation pattern with the first code pattern, the portion corresponding to the first data pattern of the input data is changed to the corresponding first code pattern. A first conversion step to convert to
From the first code pattern converted by the processing of the first conversion step, the second data pattern associated with the second code pattern in the second table consisting of the even / oddity preservation violation pattern is individually A detection step of detecting an even-oddity preservation violation individual conversion code pattern generated by converting to a code pattern;
An information processing method comprising: a second conversion step of selecting whether to perform conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern or to use the first code pattern. According to the first table that associates the first data pattern composed of the even-oddity preservation pattern with the first code pattern, the portion corresponding to the first data pattern of the input data is changed to the corresponding first code pattern. A first conversion step to convert to
From the first code pattern converted by the processing of the first conversion step, the second data pattern associated with the second code pattern in the second table consisting of the even / oddity preservation violation pattern is individually A detection step of detecting an even-oddity preservation violation individual conversion code pattern generated by converting to a code pattern;
A program that causes a computer to execute a second conversion step of selecting whether to perform conversion processing of the even-oddity preservation violation individual conversion code pattern to the second code pattern or to use the first code pattern.   15. A recording medium on which the program according to claim 14 is recorded.

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