JP2007213656A - Modulation device and method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To limit the continuation of the minimum run to a prescribed number of times without limiting the insertion pattern of synchronizing signals or the like. <P>SOLUTION: A conversion pattern determining part 52 selects a prescribed conversion pattern from a code word string converted so as to follow an RLL rule by a conversion pattern processing part 51. A minimum run continuation limiting pattern processing part 54 performs processing so as to limit the number of times of the continuation of the minimum run. A specified rule conversion pattern detection part 53 detects a pattern having a specified rule to prohibit DSV control within a data string. A channel bit string conversion part 55 converts a channel bit string outputted from the conversion pattern determining part 52 to another channel bit string on the basis of information from the minimum run continuation limiting pattern processing part 54, the specified rule conversion pattern detection part 53, an adjacent code detection part 56 and a general detection part 57. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a modulation apparatus and method, a program, and a recording medium, and a modulation apparatus that allows a desired number of continuous runs to be performed at a predetermined number of times without limiting the insertion pattern. And a method, a program, and a recording medium.

  When data is transmitted to a predetermined transmission path or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated so as to be suitable for the transmission path or the recording medium. A block code is known as one of such modulation methods. The block code is to block a data string into units of m × i bits (hereinafter referred to as data words) and convert the data words into code words of n × i bits according to an appropriate coding rule. This code becomes a fixed length code when i = 1, and when a plurality of i can be selected, that is, when a predetermined i in the range of 1 to imax (maximum i) is selected and converted, Become. This block-coded code is represented as a variable length code (d, k; m, n; r).

  Here, i is referred to as a constraint length, and imax is r (maximum constraint length). Further, d represents, for example, the minimum continuous number of “0” that falls between consecutive “1” s, that is, the minimum run of “0”, and k represents the maximum continuous of “0” that falls between consecutive “1”. The number, that is, the maximum run of “0” is shown.

  By the way, when the code word obtained as described above is recorded on an optical disk, a magneto-optical disk, or the like, for example, in a compact disk (CD) or mini disk (MD) (registered trademark), “1” is obtained from a variable length code string. NRZI (Non Return to Zero Inverted) modulation in which “0” is non-inverted, and recording is performed based on the NRZI-modulated variable length code (hereinafter referred to as a recording waveform sequence). This is called mark edge recording. On the other hand, on an ISO standard 3.5-inch / 230 MB capacity magneto-optical disk or the like, the recording-modulated code string is recorded as it is without NRZI modulation. This is called mark position recording. Mark edge recording is often used in recording media with high recording density as at present.

  When the minimum inversion interval of the recording waveform train is Tmin and the maximum inversion interval is Tmax, in order to perform high density recording in the linear velocity direction, the longer the minimum inversion interval Tmin, that is, the larger the minimum run d is. From the viewpoint of clock reproduction, it is desirable that the maximum inversion interval Tmax is shorter, that is, the maximum run k is smaller. In consideration of overwrite characteristics, it is desirable that Tmax / Tmin is small. Furthermore, various modulation methods have been proposed and put into practical use in light of the media conditions, for example, it is important that the detection window width Tw = m / n is large from the point of Jitter and S / N.

  Here, specifically, modulation schemes proposed or actually used in optical disks, magnetic disks, magneto-optical disks, and the like will be listed. EFM code used in CD and MD (also expressed as (2,10; 8,17; 1)) and 8-16 code ((2,10; 1,2; 1) used in DVD (Digital Versatile Disc) ) And RLL (2,7) (also referred to as (2,7; m, n; r)) used in PD (120mm 650MB capacity) is an RLL code with minimum run d = 2 is there. RLL (1,7) (also expressed as (1,7; 2,3; r)) used in MD-DATA2 or ISO standard 3.5inchMO (640MB capacity) is the RLL with the minimum run d = 1 Sign. In addition, in a recording / reproducing disk device such as an optical disk or a magneto-optical disk having a high recording density that is currently being developed and researched, an RLL code with a minimum run d = 1 in which the size of the minimum mark and the conversion efficiency are balanced. (Run Length Limited code) is often used.

The modulation table of the variable length RLL (1,7) code is, for example, the following table.
<Table 1>
RLL (1,7): (d, k; m, n; r) = (1,7; 2,3; 2)
Data pattern Code pattern i = 1 11 00x
10 010
01 10x
i = 2 0011 000 00x
0010 000 010
0001 100 00x
0000 100 010

  Here, the symbol x in the modulation table is “1” when the next channel bit is “0”, and is “0” when the next channel bit is “1”. The maximum constraint length r is 2.

  The parameter of the variable length RLL (1,7) is (1,7; 2,3,2), and the minimum inversion interval Tmin represented by (d + 1) T is 2 when the bit interval of the recording waveform sequence is T. (= 1 + 1) T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin represented by (m / n) × 2 is 1.33 (= (2/3) × 2) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is Tmax = 8 (= 7 + 1) T (= (m / n) × 8Tdata = (2/3) × 8Tdata = 5.33Tdata). Further, the detection window width Tw is expressed by (m / n) × Tdata, and its value is Tw = 0.67 (= 2/3) Tdata.

  By the way, in the channel bit string modulated by RLL (1, 7) in Table 1, the frequency of occurrence is 2T, which is Tmin, and the following is the order of 3T, 4T, 5T, 6T,. When 2T, which is the minimum run (Tmin), is repeated, that is, when a large amount of edge information is generated in an early cycle, it is often advantageous for clock recovery.

  However, for example, when the recording linear density is further increased in recording / reproducing of an optical disc, the minimum run is a portion where an error is likely to occur. This is because the waveform output of the minimum run is smaller than that of other runs during disk reproduction, and is easily affected by, for example, defocusing or tangential tilt. Furthermore, continuous recording / reproduction of the minimum mark at a high recording linear density is easily affected by disturbances such as noise, and therefore, data reproduction errors are likely to occur. As a data reproduction error pattern at this time, there is a case in which an error is caused by a simultaneous shift from the first edge to the last edge of consecutive minimum marks. That is, the generated bit error length propagates from the beginning to the end of the continuous section of the minimum run. Therefore, the problem that the error propagation becomes long appears.

  For stabilization when data is recorded / reproduced at a high linear density, it is effective to limit the continuation of the minimum run.

  On the other hand, when recording data on a recording medium or transmitting data, encoding modulation suitable for the recording medium or the transmission path is performed. If these modulation codes include a low-frequency component, for example, In addition, various error signals such as tracking errors in servo control of the disk device are likely to fluctuate or jitter is likely to occur. Therefore, it is desirable for the modulation code to suppress the low frequency component as much as possible.

  There is a DSV (Digital Sum Value) control as a method for suppressing the low frequency component. The DSV is a recording code string obtained by converting a channel bit string into NRZI (that is, level coding), and the bit string (data symbol) is set to “+1” and “0” to “−1”. It means the sum when adding up. DSV is a measure of the low frequency component of the recording code string. Decreasing the absolute value of the positive / negative fluctuation of the DSV, that is, performing the DSV control, suppresses the low-frequency component except for the DC component of the recording code string.

  The modulation codes according to the variable length RLL (1,7) table shown in Table 1 are not subjected to DSV control. In such a case, DSV control is performed by performing DSV calculation at a predetermined interval in the encoded sequence (channel bit sequence) after modulation, and inserting the predetermined DSV control bits into the encoded sequence (channel bit sequence). This is realized (for example, Patent Document 1).

  The number of DSV control bits to be inserted into the channel bit string is determined by the minimum run d. When d = 1, DSV control bits are inserted at arbitrary positions in the codeword so as to keep the minimum run, the required number of bits is 2 (= d + 1) channel bits. Further, the number of bits required to insert a DSV control bit at an arbitrary position in the codeword so as to keep the maximum run is 4 (= 2 × (d + 1)) channel bits. If DSV control is performed with fewer channel bits, DSV control may not be possible depending on the pattern before and after being sandwiched.

In the RLL (1,7) code in which (d, k; m, n) = (1,7; 2,3), when the DSV control bit is converted into data together with the conversion rate,
4 channel bits x 2/3 = 8/3 = 2.67 data equivalent (2.67 Tdata)
become.

  By the way, the DSV control bit is basically a redundant bit. Therefore, from the viewpoint of code conversion efficiency, it is better to have as few DSV control bits as possible.

  Furthermore, it is preferable that the minimum run d and the maximum run k do not change depending on the inserted DSV control bit. This is because if (d, k) changes, the recording / reproducing characteristics are affected.

  However, in an actual RLL code, since the minimum run has a great influence on the recording / reproducing characteristics, it must be protected, but the maximum run is not always protected. In some cases, there are formats that use a pattern that breaks the maximum run as a synchronization pattern. For example, the maximum run in the 8-16 code of DVD (Digital Versatile Disk) is 11T, but 14T exceeding the maximum run is given in the sync pattern portion to increase the detection capability of the sync pattern.

Based on the above, the present inventors previously proposed the 1,7PP code in Table 2 as a modulation scheme corresponding to a higher recording density with (d, k) = (1,7) (for example, patents). Reference 2).
<Table 2>
1,7PP: (d, k; m, n; r) = (1,7; 2,3; 4)
Data pattern Code pattern
11 * 0 *
10 001
01 010

0011 010 100
0010 010 000
0001 000 100

000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

110111 001 000 000 (next010)
00001000 000 100 100 100
00000000 010 100 100 100

if xx1 then * 0 * = 000
xx0 then * 0 * = 101
=============================
Sync & Termination
# 01 001 000 000 001 000 000 001 (24 channel bits)
# = 0 not terminate case
# = 1 terminate case

Termination table
00 000
0000 010 100

110111 001 000 000 (next010):
When next channel bits are '010',
convert '11 01 11 'to' 001 000 000 '.

  The modulation table in Table 2 is a basic pattern (a conversion pattern consisting of data patterns from (11) to (000000)) that cannot be converted without it as a conversion pattern, and conversion processing is possible without it. However, by doing so, a replacement pattern (a conversion pattern consisting of data patterns (110111), (00001000), and (00000000)) that realizes more effective conversion processing, and the data string is terminated at an arbitrary position. Terminal patterns (conversion patterns composed of data patterns (00) and (0000)).

  In Table 2, the minimum run d = 1 and the maximum run k = 7, and an indeterminate code (a code represented by *) is included in the elements of the basic pattern. The indeterminate code is determined to be “0” or “1” so as to protect the minimum run d and the maximum run k regardless of the codeword string immediately before and immediately after. That is, in Table 2, when the two data patterns to be converted are (11), the code pattern of “000” or “101” is selected according to the code word string (channel bit string) immediately before that, and converted to one of them. Is done. For example, when one channel bit of the immediately preceding code word string is “1”, the data pattern (11) is converted to the code pattern “000” in order to protect the minimum run d, and 1 of the immediately preceding code word string. When the channel bit is “0”, the data pattern (11) is converted into the code pattern “101” so that the maximum run k is protected.

  The basic pattern of the modulation table in Table 2 has a variable length structure. In other words, the basic pattern in the constraint length i = 1 is composed of three (* 0 *, 001, and 010), which is smaller than the required number (2 ^ m = 2 ^ 2 = 4). . As a result, there is a data string that cannot be converted only with the constraint length i = 1 when the data string is converted. After all, in Table 2, in order to convert all the data strings (in order to hold as a modulation table), it is necessary to refer to the basic pattern up to the constraint length i = 3.

  Further, since the modulation table of Table 2 has a replacement pattern that restricts the continuation of the minimum run d, when the data pattern is (110111), the codeword string that follows is referred to, which is “010”. Is replaced with the six data pattern code pattern “001 000 000”. Also, this data pattern is converted into a code pattern in units of two data ((11), (01), (11)) when the code word string that follows is other than “010”. * 0 * 010 * 0 * ”is converted. As a result, the code word string obtained by converting the data is limited to the minimum run continuation, and the maximum run repeats up to 6 times at the maximum.

  The modulation table of Table 2 has a maximum constraint length r = 4. The conversion pattern with the constraint length i = 4 is composed of a replacement pattern (maximum run guarantee pattern) for realizing the maximum run k = 7. That is, the data pattern (00001000) is converted to the code pattern “000 100 100 100”, and the data pattern (00000000) is converted to the code pattern “010 100 100 100”. Also in this case, the minimum run d = 1 is maintained.

  Further, in Table 2, when a data string is terminated at an arbitrary position in order to sandwich a synchronization pattern, the termination pattern is used when the data string is terminated at (00) or (0000). In the synchronization pattern to be inserted, the first code word is the termination pattern use identification bit, and when the termination pattern is used, the first code word of the immediately following synchronization pattern string is “1”. When no termination pattern is used, “0” is set. The synchronization pattern in Table 2 consists of the above-mentioned termination pattern use identification bit and the code pattern of k = 8 exceeding the maximum run k = 7 twice for detection of the synchronization pattern, and is composed of a total of 24 code words. It is.

  By the way, the conversion pattern of Table 2 is obtained by dividing the number of “1” as an element of the data pattern by 2 and the number of “1” as the element of the code pattern to be converted by 2. The remainder has a conversion rule in which either 1 or 0 is the same (the number of “1” in each corresponding element is an odd number or an even number). For example, the data pattern (000001) in the conversion pattern corresponds to the code pattern “010 100 100”, but the number of “1” as each element is one in the data pattern and the corresponding code. In the pattern, the number is 3, and the remainder when divided by 2 is equal to 1 (odd number). Similarly, the data pattern (000000) of the conversion patterns corresponds to the code pattern “010 100 000”, but the number of “1” s is 0 for the data pattern and 0 for the corresponding code pattern, respectively. There are two, and when both are divided by 2, the remainder is equal to 0 (even number).

  Next, a method for performing DSV control will be described. Conventional DSV control in the case where DSV control is not performed in the modulation table, such as the RLL (1,7) code in Table 1, is performed by, for example, modulating a data string and then adding a predetermined value to a channel bit string after modulation. This was done by adding at least (d + 1) bits of DSV control bits at intervals. Even in the modulation table as shown in Table 2, DSV control can be performed in the same manner as in the prior art. However, DSV control can be performed more efficiently by utilizing the relationship between the data pattern and the code pattern in Table 2. That is, in the modulation table, the remainder when the number of “1” as the element of the data pattern and the number of “1” as the element of the code pattern are divided by 2 is equal to 1 or 0. When having a conversion rule, inserting a DSV control bit of “1” indicating “inverted” or “0” indicating “non-inverted” into the channel bit string as described above is included in the data bit string. If “inverted”, it is equivalent to inserting a DSV control bit of (1), and if “non-inverted”, (0).

For example, in Table 2, when 3 bits to be converted are followed by (001) and a DSV control bit is included after that, the data is (001−x) (x is 1 bit, “0” or “1”). Here, if “0” is given to x, in the modulation table of Table 2,
Data pattern Code pattern
0010 010 000
Is converted, and if "1" is given,
Data pattern Code pattern
0011 010 100
Conversion is performed. When the codeword string is converted to NRZI and the level code string is generated, these are the data pattern code pattern level code string
0010 010 000 011111
0011 010 100 011000
Thus, the last 3 bits of the level code string are mutually inverted. This means that the DSV control can be performed in the data string by selecting (1) and (0) of the DSV control bit x.

  Considering the redundancy by DSV control, DSV control with 1 bit in the data string is 1.5 channel bits from the conversion rate (m: n = 2: 3) in Table 2 when expressed in channel bit string. This is equivalent to performing DSV control. On the other hand, in order to perform DSV control in the RLL (1,7) table as shown in Table 1, it is necessary to perform DSV control in the channel bit string. At this time, in order to keep the minimum run, at least 2 channel bits are required. This is necessary, and the degree of redundancy is greater when compared with the DSV control in Table 2. In other words, when the table structure of Table 2 is used, DSV control can be performed efficiently by performing DSV control within the data string.

  The modulation table of Table 2 corresponding to a high recording density having the minimum run and the maximum run of (d, k) = (1, 7) described above is, for example, a Blu-ray Disc which is a high-density optical disc system. It is adopted as a format in ReWritable ver1.0 (registered trademark).

  Further, in the future, there is a demand for a more stable system even in the modulation system for a higher recording density, specifically, for example, a higher density standard for a high density optical disk.

  At that time, compared to the already commercialized Blu-ray Disc ReWritable ver1.0, a more stable system with the same parameters as the conventional (1,7) PP code and the same modulation table configuration. If the modulation scheme to be realized is realized, the conventional design technique can be used, and the design risk at the time of hardware design can be reduced.

By the way, the synchronization pattern corresponding to Patent Document 2 is also shown in, for example, Patent Document 3, but according to this, # 01 010 000 000 010 000 000 010 (24 channel bits) is given as the synchronization pattern. Have a plurality of types of synchronization patterns, and six code words are given to identify them. Specifically, for example, the following seven types are given.
<Table 3>
# 01 010 000 000 010 000 000 010 000 001 (30 channel bits)
000 100
001 001
010 000
010 010
100 001
101 000
# = 0 not terminate case
# = 1 terminate case

Termination table
00 000
0000 010 100

JP-A-6-197024 JP-A-11-346154 JP 2000-68846 A

  When the last code word is “1” among the synchronization patterns in Table 3, a maximum of six minimum run continuations may occur depending on the subsequent code pattern. Now, in order to improve the continuation of the minimum run, it is necessary to give “0” as the last code word of the synchronization pattern, and there are restrictions on the 6 code words for synchronization pattern identification as shown in Table 3. The problem of having to add is generated.

  The present invention has been made in view of such a situation, and makes it possible to limit the continuation of the minimum run to a predetermined number of times without limiting the insertion pattern such as a synchronization signal. It is.

  An aspect of the present invention provides data having a basic data length of m bits, a variable length code (d, k; m) having a minimum run of d (d> 0) and a maximum run of k, and a basic codeword length of n bits. , n), a first conversion means for converting the input data into a code string made up of a code pattern so as to comply with the RLL rule, in accordance with a conversion table describing the correspondence between the data pattern and the code pattern. Then, it is determined from the code string converted into the code pattern that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern. When it is determined that the determination means and the input data have a condition for converting a portion that matches the even-oddity preservation violation data pattern to the corresponding even-oddity preservation violation code pattern, Conversion means for converting an even-oddity preservation violation individual conversion code pattern generated by individually converting a portion that matches the even-oddity preservation violation data pattern of the received data into the even-oddity preservation violation code pattern; Is a modulation device.

  The determination means includes a code string in which the code string converted into the code pattern includes the even-oddity preservation violation individual conversion code pattern, and a code immediately before and after the even-oddity preservation violation individual conversion code pattern is predetermined. If it is, it can be determined that the input data has the condition.

  Synchronization pattern insertion means for inserting a synchronization pattern at a predetermined position of the input data can be further provided.

  DSV control bit insertion means for inserting a DSV control bit into a DSV section including the synchronization pattern and the even-oddity preservation violation code pattern so as to enable DSV control can be further provided.

  The signal modulated by the modulation device can be recorded on a recording medium.

  Data having a basic data length of m bits is converted to a variable length code (d, k; m, n) having a minimum run of d (d> 0), a maximum run of k, and a basic codeword length of n bits. In the modulation method, program, or recording medium on which the program is recorded, according to a conversion table that describes the correspondence between the data pattern and the code pattern, the input data is converted into a code string composed of the code pattern so as to comply with the RLL rule. The first conversion step and that the input data has a condition to convert a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern is converted into the code pattern. A determination step based on a code string, and a portion where the input data matches the even-oddity preservation violation data pattern is changed to the corresponding even-oddity preservation violation code pattern. If it is determined that the condition to be satisfied is satisfied, the even-oddity preservation violation individual conversion code pattern generated by individually converting the portion of the input data that matches the even-oddity preservation violation data pattern is stored as the even-oddity preservation. A modulation method, a program, or a recording medium on which a program is recorded, including a second conversion step for converting into a violation code pattern.

  In the aspect of the present invention, when the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern, the even-oddity preservation of the input data is performed. The even-oddity preservation violation individual conversion code pattern generated by individually converting the portion that matches the violation data pattern is converted into the even-oddity preservation violation code pattern.

  According to the aspects of the present invention, error propagation during data recording / reproducing can be further reduced, and as a result, it is more suitable for high linear density recording / reproducing. In addition, according to an aspect of the present invention, DSV control within a data string is possible. Furthermore, according to the aspect of the present invention, it is possible to limit the continuation of the minimum run to a predetermined number of times without limiting the insertion pattern.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  An aspect of the present invention provides data having a basic data length of m bits, a variable length code (d, k; m) having a minimum run of d (d> 0) and a maximum run of k, and a basic codeword length of n bits. , n) in the modulation device, the input data is encoded so as to comply with the RLL rule according to a conversion table (for example, conversion table 72 in FIGS. 4 and 21) describing the correspondence between the data pattern and the code pattern. First conversion means (for example, the conversion pattern processing unit 51 in FIGS. 4 and 21) for converting into a code string composed of patterns, and the input data is an even-oddity preservation violation data pattern (for example, the data pattern in Table 4). (01110111)) is converted to the code pattern that has a condition to convert the portion that matches with the even-oddity preservation violation code pattern (for example, code pattern “010 000 000 101” in Table 4). Judgment based on code sequence Corresponding to the portion where the input data matches the even-oddity preservation violation data pattern (for example, the specific rule conversion pattern detection unit 53 and the minimum run continuation restriction pattern detection prediction unit 111 in FIGS. 4 and 21) The even-oddity preservation | save produced | generated by converting separately the part which corresponds to the said even-oddity preservation | save violation data pattern of the input data, when it determines with having the conditions which should be converted into the said even-oddity preservation | save violation code pattern Second conversion means (for example, FIG. 4 and FIG. 4) that converts the violation individual conversion code pattern (for example, “010 101 010 101” in step S241 of FIG. 16 and step S641 of FIG. 30) into the even-oddity preservation violation code pattern. 21 is a modulation device (for example, the modulation device 1 in FIG. 1 or FIG. 33).

  The determination means includes a code string converted into the code pattern including the even-oddity preservation violation individual conversion code pattern (for example, “010 101 010 101” in step S241 of FIG. 16 or step S641 of FIG. 30), When the code immediately before and after the even-oddity preservation violation individual conversion code pattern is a predetermined code (for example, the specific rule conversion pattern detection flag is on in step S293 in FIG. If it is determined that the general flag (2) is on) and the prediction flag (C4) is off (the channel bit immediately after is not “010”) in step S294, or step S693 in FIG. Thus, it is determined that the specific rule conversion pattern detection flag is on (minimum run continuation restriction total flag (2) is on), and the prediction flag (C4) is off in step S695 (the channel bit immediately after is “ 010 ” If it is determined that a)), it is possible to input data is determined to have the condition.

  Synchronization pattern insertion means (for example, the synchronization pattern insertion unit 23 in FIG. 1 or FIG. 33) for inserting a synchronization pattern at a predetermined position of the input data can be further provided.

  A DSV section (for example, span1 of FIG. 2 or FIG. 34) including the synchronization pattern (for example, Sync of FIG. 2 or FIG. 34) and the even-oddity preservation violation code pattern (for example, violate-code of FIG. 2 or FIG. 34). DSV control bit insertion means (for example, the DSV control bit determination insertion unit 21 in FIG. 1, the DSV control bit insertion unit 201 in FIG. 33, A DSV controller 202) can be further provided.

  The signal modulated by the modulation device can be recorded on a recording medium (for example, the recording medium 13 in FIGS. 1 and 33).

  An aspect of the present invention provides data having a basic data length of m bits, a variable length code (d, k; d) where the minimum run is d (d> 0), the maximum run is k, and the basic codeword length is n bits. In the modulation method for converting to m, n), the input data is kept in accordance with the RLL rule according to a conversion table (for example, the conversion table 72 in FIGS. 4 and 21) describing the correspondence between the data pattern and the code pattern. A first conversion step (for example, step S3 in FIG. 8 and step S403 in FIG. 22) for converting into a code string consisting of a code pattern, and the input data is an even-oddity preservation violation data pattern (for example, the data in Table 4). The fact that the portion that matches the pattern (01110111)) should be converted into the corresponding even-oddity preservation violation code pattern (for example, the code pattern “010 000 000 101” in Table 4) is converted into the code pattern. From the code string A determination step (for example, steps S5 and S7 in FIG. 8, steps S405 and S407 in FIG. 22), and a portion where the input data matches the even-oddity preservation violation data pattern, the corresponding even-oddity preservation. When it is determined that the condition to be converted into the violation code pattern is satisfied, the even-oddity preservation violation individual conversion code pattern generated by individually converting the portion that matches the even-oddity preservation violation data pattern of the input data 16 (for example, “010 101 010 101” in step S241 in FIG. 16 or step S641 in FIG. 30) is converted into the even-oddity preservation violation code pattern (for example, step S8 in FIG. 8 and FIG. 22). Step S408) includes a modulation method (for example, the modulation method of FIG. 8 or FIG. 22).

  Embodiments of the present invention will be described below. Hereinafter, the data string (data pattern) before conversion is delimited by () as (000011), and the channel bit string (code pattern) after conversion is delimited by “” as “000 100 100”. Further, in this specification, it is a variable length code in which the minimum run d = 1, the maximum run k = 7, and the conversion rate (m: n) = (2: 3). A code with a conversion table that performs complete DSV control with efficient DSV control bits while restricting and protecting the minimum and maximum runs, is a 1,7PP code (PP: Parity-preserve Prohibit-repeated-minimum -transition-runlength).

  Table 4 below shows a modulation table as an embodiment of the present invention.

<Table 4>
1,7PP-rmtr5_code.rev.11 RLL (1,7; 2,3; 5)
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

i = 3 110111 001 000 000 (next010)
i = 4 01110111 (pre1) 010 000 000 101 (not010)
i = 5 1001110111 $ 0 $ 010 000 000 101 (not010)

If xx1 then * 0 * = 000
xx0 then * 0 * = 101
If x10 or x01 then $ 0 $ = 000
x00 then $ 0 $ = 101

Sync & Termination
# 01 010 000 000 010 000 000 010 yyy yyy (30 cbits = SY_24 cbits + ID_6 cbits)
# = 0 not terminate case
# = 1 terminate case

Termination table
00 000
0000 010 100

  The code pattern “001 000 000” (next010) means that conversion is performed when the code pattern next to the code pattern “001 000 000” is “010”. (Pre1) of the code pattern “(pre1) 010 000 000 101 (not010)” means that conversion is performed when the immediately preceding code is “1”, and (not010) If it is not “010”, it means that conversion is performed. The same applies to other conversion patterns.

  Similar to the modulation table of Table 1 or Table 2, the modulation table of Table 4 includes a conversion pattern composed of a data pattern and a code pattern. When the modulation device performs modulation according to the modulation table of Table 4, if the data sequence input to the modulation device matches the data pattern described in Table 4, the portion that matches the data pattern of the data sequence is: It is converted into a corresponding code pattern (shown on the right side in Table 4) and output as a code word string.

  The modulation table in Table 4 is a 1,7PP code, and the basic configuration is the same as in Table 2. The modulation table shown in Table 4 includes a basic table, a replacement table, and a termination table.

  The basic table is composed of conversion patterns (basic patterns) that cannot be converted without it, and the replacement table can be converted without it, but more effective conversion is possible by doing it. It is configured by a conversion pattern (replacement pattern) that can realize processing (limit the maximum run or limit the continuation of the minimum run). The termination table includes a conversion pattern (termination pattern) for terminating the code at an arbitrary position.

  Specifically, in the modulation table shown in Table 4, the basic data pattern consisting of the data patterns (11) to (000000) and the corresponding codes from “* 0 *” to “010 100 000” A portion composed of a conversion pattern (basic pattern) including a basic code pattern consisting of patterns is a modulation table as a basic table, and data of (00001000), (00000000), (110111), (01110111), (1001110111) Replacement data pattern consisting of patterns and the corresponding “000 100 100 100”, “010 100 100 100”, “001 000 000 (next010)”, “(pre1) 010 000 000 101 (not010)”, “$ 0 $ A portion constituted by a replacement code pattern (replacement pattern) composed of a code pattern of “010 000 000 101 (not 010)” is a modulation table as a replacement table.

  The part of the replacement table that includes replacement data patterns consisting of data patterns (00001000) and (00000000) and corresponding replacement code patterns consisting of code patterns “000 100 100 100” and “010 100 100 100” , A replacement pattern table for limiting the maximum run, and a replacement data pattern composed of the data patterns (110111), (01110111), (1001110111) and the corresponding “001 000 000 (next010)”, “( This is a table of replacement patterns in which a portion constituted by a replacement code pattern composed of code patterns of “pre1) 010 000 000 101 (not010)” and “$ 0 $ 010 000 000 101 (not010)” restricts the continuation of the minimum run.

  Further, the data patterns (11) to (00000000) are fixedly converted into corresponding code patterns from “* 0 *” to “010 100 100 100” regardless of the conditions. In this sense, hereinafter, these conversion patterns are also referred to as fixed conversion patterns.

  On the other hand, the data patterns of (110111), (01110111), and (1001110111) are collectively “001 000 000”, “010 000 000 101”, “$ 0 $ 010 000 000 101” depending on the conditions. ”, But depending on the conditions, the entire data pattern is not converted all at once, but is divided into individual data patterns (fixed conversion patterns), and the corresponding code pattern for each data pattern Is converted to In that sense, hereinafter, these conversion patterns are also referred to as conditional conversion patterns.

  Also, it is constituted by a conversion pattern (termination pattern) including a termination data pattern composed of data patterns (00) and (0000) and a termination code pattern composed of code patterns “000” and “010 100” corresponding thereto. The portion is a modulation table as a termination table.

  The modulation table describes the correspondence between the data pattern and the code pattern. In the following, a part of Table 4 is also described as a modulation table or a conversion table as necessary.

  Table 4 has a minimum run d = 1 and a maximum run k = 7, and has an indeterminate code (a code represented by *) as an element of the basic code. The indeterminate code is determined to be “0” or “1” so as to protect the minimum run d and the maximum run k regardless of the codeword string immediately before and immediately after. That is, in Table 4, when the two data to be converted is (11), “000” or “101” is selected according to the immediately preceding code word string (channel bit string) and converted into one of them. For example, when one channel bit of the immediately preceding code word string is “1”, in order to keep the minimum run d, 2 data (11) is converted into a code word “000”, and 1 of the immediately preceding code word string is 1 When the channel bit is “0”, the two data (11) is converted into the code word “101” so that the maximum run k is protected.

  Since the conversion table of Table 4 has a variable length structure, the basic pattern has i = 1 to i = 3.

  Further, the conversion table of Table 4 has a replacement pattern that restricts the continuation of the minimum run d when the constraint length is i = 3. When the data pattern is (110111), the code word immediately after is referred to. When the subsequent code word string matches the code pattern of “010”, these 6 data are replaced with the code pattern “001 000 000”. Further, these 6 data are converted into code words in divided 2 data units ((11), (01), (11)) when the code word string immediately after this does not match the code pattern “010”. It is converted into the code word “* 0 * 010 * 0 *”, that is, the code word “* 0 * 010 101”.

  The conversion table of Table 4 further has a replacement pattern that restricts the continuation of the minimum run d at the constraint length i = 5. When the data string is (1001110111), except for the exception processing described later (when the following code is “010”), this 10-bit data string is replaced with the code word “$ 0 $ 010 000 000 101” It is done.

  “$” Is an indeterminate code for observing the RLL rule and limiting the continuation of the minimum run to a predetermined number of times. Specifically, in order to protect the minimum run, when one channel bit of the immediately preceding codeword string is “1”, the codeword “$ 0 $” is converted to the codeword “000” and the maximum run is protected. Therefore, when one channel bit of the immediately preceding code word string is “0”, the code word “$ 0 $” is converted to the code word “101”. Further, in order to limit the continuation of the minimum run to a predetermined number of times, the codeword “$ 0 $” is converted to the codeword “000” when the three channel bits of the immediately preceding codeword string are “010”. .

  To summarize the above, when the two channel bits of the immediately preceding code word string are “10” or “01”, the code word “$ 0 $” is converted to the code word “000”. In the case of “00”, the code word “$ 0 $” is converted to the code word “101”.

  Although there are four 2-channel bit patterns, the remaining “11” does not satisfy the minimum run d = 1 and is not used as a conversion pattern.

  The exception handling is as follows. That is, when the data string matches the data pattern (1001110111), the codeword string immediately after is referred to, and when the codeword string following is “010”, the codeword “$ 0 $ 010” as described above is used. Only the first two bits (10) are converted into the code word “001” without performing the batch replacement process to “000 000 101”. Thereafter, similarly, the data are sequentially converted by being divided (divided) into (01) and (110111).

  The modulation table in Table 4 has a replacement pattern that restricts the continuation of the minimum run d at the constraint length i = 4. In the code word string after the synchronization pattern is inserted, when the data string to be converted is (01110111), the code word immediately before that is “1” and the code word string that follows is “010”. If not, these 8 data are replaced with the code word “010 000 000 101”. Also, this data string is divided (divided) when the immediately preceding code word is “0” or the immediately following code word string is “010”, and two data (01) is converted into the code word “010”. Converted. Then, the data (110111) is converted in the next conversion process.

  As described above, the code word string obtained by converting the data with the synchronization pattern inserted is limited in the minimum run, and is the minimum run repetition up to 5 times at the maximum.

  The conversion table in Table 4 has a replacement pattern (maximum run guarantee pattern) for realizing the maximum run k = 7 in the conversion pattern with the constraint length i = 4. That is, the data pattern (00001000) is converted into the code pattern “000 100 100 100”, and the data pattern (00000000) is converted into the code pattern “010 100 100 100”. In this case as well, the minimum run d = 1 is maintained.

  Further, in Table 4, when the data string is terminated at an arbitrary position in order to sandwich the synchronization pattern, the termination pattern is used when the data string is terminated at (00) or (0000). In the synchronization pattern to be inserted, the first code word is the termination pattern use identification bit. When the termination pattern is used, the first code word of the immediately following synchronization pattern sequence is “1”, and the termination pattern is When not used, it is “0”. In addition, the synchronization pattern in Table 4 has the above-described termination pattern use identification bit and a code word (pattern for specifying the synchronization position) of k = 8 exceeding the maximum run k = 7 for synchronization signal detection, Furthermore, 6 code words are provided as identification bits for identifying which one of the plurality of synchronization patterns. These six code words can be arbitrarily selected so as to comply with the RLL rule. As described above, for example, as shown in Table 4, the synchronization pattern is composed of 30 code words (channel bits) in total by repeating k = 8 twice.

  By the way, the conversion pattern in Table 4 basically has the remainder when the number of “1” in the data pattern is divided by 2 and the remainder when the number of the corresponding code pattern “1” is divided by 2. Also have a conversion rule such that 1 or 0 is the same (the number of “1” in each corresponding pattern is odd or even). For example, the data pattern (000001) in the conversion pattern corresponds to the code pattern “010 100 100”, but the number of “1” in each pattern is one in the data pattern and the corresponding code pattern. The number is 3 and both of them are divided by 2 so that the remainder is equal to 1 (odd number). Similarly, the data pattern (000000) of the conversion patterns corresponds to the code pattern “010 100 000”, but the number of “1” is 0 for the data pattern and 2 for the corresponding code pattern, respectively. In both cases, the remainder when divided by 2 is equal to 0 (even number). That is, these patterns are even-oddity preservation patterns in which even-oddity is preserved.

  In the data string, 1 bit of DSV control bit is inserted as a redundant bit. When this DSV control bit is (1), the data string including the DSV control bit part is converted to a channel bit string, converted into NRZI, and recorded code string The polarity of “1” and “0” is reversed. When the DSV control bit is (0), the polarity is not inverted when the data string including the DSV control bit portion is converted to a channel bit string and converted into NRZI to create a recording code string. Accordingly, the polarity after data conversion and conversion into NRZI can be changed by one bit inserted as a redundant bit in the data string, so that DSV control can be performed in the data string. That is, Table 4 is a table having a rule (basic rule) that can control the DSV of the code by the data string.

  On the other hand, Table 4 shows that when conversion of the replacement pattern that restricts the continuation of the minimum run d is performed at the constraint length i = 4, the 8-bit data pattern (01110111) is the 12-channel bit code pattern “010 000 000. Replaced with 101 ”. In these patterns, the oddity that the remainder when the number of “1” in the data pattern is divided by 2 and the remainder when the number of “1” in the code pattern is divided by 2 does not match 0 and 1 This is a storage violation pattern. Therefore, this modulation table is a table having a rule (specific rule) in which the DSV of the code cannot be controlled by the data string.

  Therefore, in the embodiment of the present invention, the appearance position of the replacement pattern that restricts the continuation of the minimum run d of the constraint length i = 4 where DSV control cannot be performed is limited to immediately after the synchronization pattern. . Since the synchronization pattern is 30 code words and the even / oddity preservation violation pattern “010 000 000 101” is 12 channel bits, the total number of channel bits is 42. The 42 channel bits are 28 bits when converted into data bits at a conversion rate (m / n) (42 × (conversion rate) = 42 × 2/3 = 28). Therefore, one DSV control bit is inserted at intervals of 28 data or more in the data string (DSV section is 28 bits or more). Thereby, the influence by the even-odd preservation | save violation pattern can be avoided. Therefore, in Table 4, 28 data + 1 DSV control bit is the minimum value not affected by the even-oddity preservation violation pattern. If the DSV interval is longer than this (for example, 45 + 1 DSV), the DSV control can be performed as usual.

  In other words, Table 4 corresponds to the sum length (42 bits) of the pattern inserted into the data (30-bit synchronization pattern) and the even-oddity preservation violation pattern (12-bit pattern “010 000 000 101”). It is a table having a rule that a length before conversion (28 bits) is a reference length, and a DSV section in which one DSV control bit is inserted is a length greater than the reference length. As a result, not only the even / oddity preservation pattern but also the even / oddity preservation violation pattern can be used in the modulation table, and the degree of freedom of the conversion pattern that can be adopted in the modulation table is improved.

  With the above configuration, when the minimum run d = 1, the maximum run k = 7, the conversion rate (m: n) = (2: 3), and a synchronization pattern is inserted at an arbitrary position , DSV control can be performed by inserting one DSV control bit into the data string, and a code word string in which the continuation of the minimum run is limited to a maximum of five times can be obtained.

  Here, in Table 4, when the first 8 bits of the input data match the even-odd storage violation data pattern (01110111), the immediately preceding channel bit is “1” and the immediately following 3 channel bits are “010”. Otherwise, it is converted to the even-oddity preservation violation code pattern “010 000 000 101”. Even if the first 8 bits of the input data match the even-odd storage violation data pattern (01110111), the immediately preceding channel bit is “0” or the immediately following 3 channel bits are “010” Is not converted into the even-oddity preservation violation code pattern “010 000 000 101”.

  At this time, the conversion to the even / oddity preservation violation code pattern “010 000 000 101” does not occur in the DSV section in which the synchronization pattern is not inserted, but only in the DSV section in which the synchronization pattern is inserted. Hereinafter, this reason will be described. There is a possibility that the channel bit immediately before the even-odd preservation violation data pattern (01110111) may be “1”, from Table 4, the data pattern before the even-odd preservation violation data pattern (01110111) is (10) (Converted to code pattern “001”) or (11) (converted to code pattern “* 0 *” (“101”)).

  However, when the data pattern is (10), the conversion of the constraint length i = 5 in Table 4 (the conversion of the data pattern (1001110111)) has already been performed. If the immediately preceding data pattern is (11), the first 6 bits match the data pattern (110111) with the constraint length i = 3 in Table 4, and the corresponding conversion has already been performed. Will be. After all, the channel bit immediately before the even-odd preservation violation data pattern (01110111), which is a condition for applying the even-odd preservation violation code pattern, may be “1” regardless of the rule of the modulation table. Only when the channel bits are freely determined, that is, when a synchronization pattern is inserted.

  Specifically, the channel bit immediately before the even-odd storage violation data pattern (01110111) becomes “1” because the last one channel of the identification bit “yyy yyy” behind the inserted synchronization pattern string This is the case where the bit “y” is “1”. Therefore, the even-odd preservation violation pattern is used only in the DSV section in which the synchronization pattern is inserted, and is not used in the DSV section in which the synchronization pattern is not inserted.

In addition to Table 4, the following table can be considered as another embodiment of a similar modulation table. That is, i = 4 in Table 4 01110111 (pre1) 010 000 000 101 (not010)
Part of
i = 4 01110111 010 000 000 101 (not 010) However, it is applied only immediately after the insertion pattern (for example, synchronization signal), and the constraint length i cannot be controlled by DSV control even when other parts are set to the same table. The appearance position of the replacement pattern that restricts the continuation of the minimum run d = 4 can be limited to immediately after the synchronization pattern.

  Of course, the pattern to be inserted can be various patterns other than the synchronization pattern, and the length of the even-oddity preservation violation pattern can be other than 12 bits.

  Next, the configuration of the modulation device according to the embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a modulation device 1 according to an embodiment of the present invention. The modulation device 1 includes an encoding device 11 that encodes and outputs an input data string, and a recording unit 12 that records the output of the encoding device 11 on a recording medium 13. The encoding device 11 includes a DSV control bit decision insertion unit 21, a modulation unit 22, a synchronization pattern insertion unit 23, and an NRZI conversion unit 24.

  The DSV control bit decision insertion unit 21 performs DSV control on the input data string at an arbitrary interval according to a predetermined format, and as a result, the DSV control bit “1” or “0” is set at an arbitrary interval. Make a decision and make an insertion. The modulation unit 22 modulates the data string in which the DSV control bits are inserted. The synchronization pattern insertion unit 23 inserts a synchronization pattern at a predetermined position at a predetermined interval. The NRZI converting unit 24 converts the data in which the synchronization pattern is inserted into a recording code string (or converts it into a transmission code string when outputting to a transmission path). The recording unit 12 records the recording code string input from the NRZI converting unit 24 on a recording medium 13 configured by, for example, an optical disk, a magnetic disk, a magneto-optical disk, or the like. Although not shown, a timing management unit is provided that generates a timing signal and supplies the timing signal to each unit to manage timing.

  FIG. 2 is a diagram showing a data format of data input / output to / from each unit of the modulation device 1, and shows a relationship of insertion of DSV control bits including a synchronization pattern. The data string (FIG. 2A) input to the DSV control bit decision insertion unit 21 from a device (not shown) includes information data such as ECC (Error-Correcting Code) in addition to user data. The DSV control bit determining / inserting unit 21 inserts one DSV control bit at predetermined intervals in the data string (FIG. 2B).

The first section is preliminarily set to a length different from other sections on the assumption that a sync SYNC (synchronization pattern) is inserted. When the length of the DSV section (DATA1, DATA2, and DATA3) in Fig. 2B is a data, b data, and b data, respectively, a modulation table (Table 4) with a conversion ratio of m: n = 2: 3 was used. The modulation cbit (channel bit) section of each DSV section (DATA1, DATA2, and DATA3) is (a × 3/2) = (1.5a) or (b × 3/2) = (1.5b) (Fig. 2C). Thereafter, the synchronization pattern insertion unit 23 inserts a sync (SYNC) at a predetermined position (the leading position before the DATA1 position in FIG. 2) (FIG. 2D). If the number of SYNC channel bits is c (cbit), the relationship of the following equation (1) is established between a, b, and c.
1.5a + c = 1.5b (1)

  At this time, even in a format including a synchronization pattern, DSV control is performed at equal intervals.

The DSV control bits in the channel bits according to FIG. 2 are equivalent to 1.5 channel bits. That is, since one DSV control bit is inserted into the data string, the channel bit equivalent increases by the conversion rate,
1 bit x n / m = 1 x 3/2 = 1.5 channel bits (2)
It becomes.

  Compared with the conventional method, for example, in order to perform DSV control within channel bits while keeping the minimum run d = 1, two channel bits are required. Alternatively, 4 channel bits are required to perform DSV control while protecting both the minimum run and the maximum run. Therefore, as compared with the conventional DSV control method, it can be seen that the insertion of the DSV control bit in the data string of this method can reduce the redundant channel bits for the DSV control.

  If the last one channel bit of the synchronization pattern is “1”, the data immediately after it matches the data pattern (01110111), and the subsequent three channel bits are not “010”, that part is The signal is converted into the code pattern “010 000 000 101” by the modulation unit 22 (FIG. 2E). This code pattern is an even-oddity preservation violation pattern. However, since the even-odd conservation violation pattern is included in the DSV section, DSV control is possible in the DSV section. In addition, the modulation unit 22 is the data of the section in which the synchronization pattern is inserted, or if the synchronization pattern is inserted, what is its ID, and therefore whether to use the even-oddity preservation violation pattern? Necessary information is supplied from each part so that it can be determined.

  The channel bit string into which the synchronization pattern is inserted is converted to NRZI by the NRZI converting unit 24 (FIG. 2F), supplied to the recording unit 12 as a recording code string, and recorded on the recording medium 13.

  FIG. 3 is a block diagram illustrating a configuration of a main part of the encoding device 11. The DSV control bit decision insertion unit 21 includes an adder 41 that adds a DSV control bit to input data. The modulation unit 22 includes a conversion pattern processing unit 51, a conversion pattern determination unit 52, a specific rule conversion pattern detection unit 53, a minimum run continuation restriction pattern processing unit 54, a channel bit string conversion unit 55, a previous code detection unit 56, and an overall detection unit. 57.

  In the encoding device 11 of FIG. 3, DSV control bits are inserted into the input data string by the adder 41 at predetermined intervals. The input data string in which the DSV control bit is inserted is sent to the conversion pattern processing unit 51. The conversion pattern processing unit 51 has a basic pattern portion in Table 4 and a replacement pattern for realizing the maximum run k = 7, performs conversion pattern processing so as to comply with the RLL rule, and converts the processing information into the conversion pattern. It supplies to the determination part 52. Information from the immediately preceding code detection unit 56 is used for the conversion pattern processing. Further, the conversion pattern processing unit 51 has a termination table for inserting a synchronization pattern, and uses the termination table as necessary so as to terminate at a predetermined position. When the termination table is used, the information is embedded in the synchronization pattern. The conversion pattern determination unit 52 selects and outputs a predetermined conversion pattern from the codeword string output by the conversion pattern processing unit 51.

  The minimum run continuation restriction pattern processing unit 54 includes a replacement pattern for restricting the continuation of the minimum run d that can perform DSV control in the data string, as shown in Table 4. Then, the processing information is supplied to the channel bit string conversion unit 55. The specific rule conversion pattern detection unit 53 includes a replacement pattern having a specific rule that cannot be subjected to DSV control within the data string, and performs processing so as to limit the number of consecutive minimum runs, The processing information is supplied to the channel bit string converter 55. Information from the comprehensive detection unit 57 is used for the processing of the specific rule conversion pattern detection unit 53.

  The channel bit string conversion unit 55 outputs the channel bit string output from the conversion pattern determination unit 52 from the minimum run continuation restriction pattern processing unit 54, the specific rule conversion pattern detection unit 53, the immediately preceding code detection unit 56, and the total detection unit 57. Based on the information, it is converted into another channel bit string.

  The immediately preceding code detection unit 56 uses the information from the conversion pattern determination unit 52 and the synchronization pattern insertion unit 23 as information necessary to guarantee RLL from the finally determined conversion pattern, immediately before the next conversion process. Is detected as “1”, and the detection result is supplied to the conversion pattern processing unit 51 and the channel bit string conversion unit 55. Based on the information from the conversion pattern determination unit 52 and the synchronization pattern insertion unit 23, the comprehensive detection unit 57 uses information that is necessary to guarantee the minimum number of continuous runs from the finally determined conversion pattern and synchronization pattern. Is supplied to the channel bit string converter 55 and the specific rule conversion pattern detector 53. Specifically, it is detected whether the code immediately before the next conversion process is “010” or “1”.

  In the detection of the immediately preceding code detection unit 56 or the comprehensive detection unit 57, the input information for obtaining the finally determined conversion pattern is the information from the conversion pattern determination unit 52. Even if the output from the bit string conversion unit 55 to the synchronization pattern insertion unit 23 is used, the same operation can be performed. Also, if the conversion pattern processing unit 51 and the channel bit string conversion unit 55, which are output destinations of the immediately preceding code detection unit 56, have different processing timings, the detection result for the immediately preceding code at each timing is provided. .

  The synchronization pattern insertion unit 23 inserts a synchronization pattern into the codeword output from the channel bit string conversion unit 55 at a predetermined interval and a predetermined position. The output of the synchronization pattern insertion unit 23 is converted to NRZI by the NRZI conversion unit 24 and output as a recording code string (or a transmission code string when output to a transmission path). This output is recorded on the recording medium 13 by the recording unit 12 or transmitted to a predetermined transmission path.

  The operation timing of each unit is managed in synchronization with a timing signal supplied from a timing management unit (not shown).

  FIG. 4 shows a more detailed configuration of the encoding device 11 of FIG. The DSV control bit decision insertion unit 21 includes an adder 41 and a shift register 42. The shift register 42 is configured to hold data of up to 8 bits. The conversion pattern processing unit 51 includes a conversion pattern detection unit 71, a conversion table 72 (conversion tables 72A to 72D), a selector 73, and an indeterminate bit determination unit 74.

  The conversion pattern detection unit 71 detects a conversion pattern that observes the RLL rule from the data string input from the shift register 42, and outputs the result information (conversion pattern determination information) to the conversion pattern determination unit 52. Also output to the conversion tables 72A to 72D. The conversion table 72A performs a conversion process with a constraint length i = 1. That is, 2 data is converted into 3 channel bits and output to the selector 73. The conversion table 72B performs conversion processing with a constraint length i = 2. That is, 4 data is converted into 6 channel bits and output to the conversion pattern determination unit 52. The conversion table 72C performs conversion processing with a constraint length i = 3. That is, 6 data is converted into 9 channel bits and output to the conversion pattern determination unit 52. The conversion table 72D performs conversion processing with a constraint length i = 4. That is, 8 data is converted into 12 channel bits and output to the conversion pattern determination unit 52. Further, the conversion pattern detection unit 71 outputs uncertain pattern identification information to the selector 73 when detecting uncertain data corresponding to the uncertain code.

  Based on the uncertain pattern identification information from the conversion pattern detection unit 71, the selector 73 determines that the channel bit string supplied from the conversion table 72A includes an uncertain code (the uncertain pattern identification information indicates the presence of the uncertain code). If it is represented, the channel bit string supplied from the conversion table 72A is output to the indeterminate bit determination unit 74.

  The indeterminate bit determining unit 74 determines the indeterminate bit included in the 3 channel bits supplied from the selector 73 based on the output of the immediately preceding code detecting unit 56, and the 3 channel bits after the indeterminate bit is determined Are output to the conversion pattern determination unit 52. On the other hand, when an indeterminate code is not included, the selector 73 directly outputs the channel bit string supplied from the conversion table 72A to the conversion pattern determination unit 52.

  Further, the conversion pattern processing unit 51 has a termination table for inserting a synchronization pattern, and uses the termination table as necessary so as to terminate at a predetermined position. When the termination table is used, the information is embedded in the synchronization pattern.

  The specific rule conversion pattern detection unit 53 detects that the code pattern is “010 101 010 101” and that the immediately preceding code is “1” based on the information from the comprehensive detection unit 57.

  The minimum run continuous restriction pattern processing unit 54 includes a minimum run continuous restriction pattern detection predicting unit 111 and a minimum run continuous restriction pattern detecting unit 112.

  When the minimum run continuation limited pattern detection prediction unit 111 detects a predetermined pattern sequence for limiting the number of continuations of the minimum run at a predetermined position that is not the head, the information is used as the minimum run continuation limited pattern detection prediction information. The data is output to the bit string converter 55. Specifically, the minimum run continuation restriction pattern detection predicting unit 111 performs processing corresponding to exception pattern replacement processing for restricting continuation of the minimum run d having a constraint length i = 5 in Table 4 as predetermined channel bit string detection. In the channel bit string that includes the synchronization pattern but does not include the synchronization pattern, the 7th channel bit from the top is “101 010 101” and the subsequent 3 channel bits are “010”. The detection process is performed on the detected part. That is, it is detected whether or not “xxx xxx 101 010 101” + “010”. Further, the minimum run continuation limited pattern detection prediction unit 111 performs detection processing on the portion where the fourth channel bit from the head is “101 010 101” and the subsequent three channel bits are “010”. That is, whether or not “xxx 101 010 101” + “010” is detected.

  The minimum run continuation restriction pattern detection unit 112 performs a process corresponding to a replacement pattern for restricting the continuation of the minimum run d of constraint length i = 3 and 5 in Table 4 as predetermined channel bit string detection, and is a basic processing unit 3 When viewed in units of channel bits, detection processing is performed for “101 010 101” and subsequent portions where the three channel bits are “010”. Further, detection processing is performed for a portion of “001 010 101 010 101” when viewed in units of 3 channel bits, which is a basic processing unit.

  When the minimum run continuation limit pattern detection unit 112 detects that the code pattern “101 010 101” and the subsequent three channel bits are “010”, the channel bit string conversion unit 55 detects the code pattern “101 Processing to replace “010 101” with the code pattern “001 000 000” is performed.

  The channel bit string conversion unit 55 also detects the detection prediction information from the first 7 channel bits as “xxx xxx 101 010” when the code pattern “001 010 101 010 101” is detected by the minimum run continuous restriction pattern detection unit 112. When “101” + “not 010”, the code pattern “001 010 101 010 101” is converted to the code pattern “$ 0 $ 010 000 000 101”. “$ 0 $” is converted to “000” when the immediately preceding code is “1” or the immediately preceding three codewords are “010”, and is converted to “101” otherwise.

  Furthermore, when the specific rule conversion pattern detection unit 53 detects that the code pattern “010 101 010 101” and the immediately preceding code are “1”, the channel bit string conversion unit 55 further starts from the first 4 channel bits. When the predicted detection information is “xxx 101 010 101” + “not 010”, the code pattern “010 101 010 101” is converted to the code pattern “010 000 000 101”.

  As shown in FIG. 5, the immediately preceding code detection unit 56 stores the last channel bit string of the determined conversion pattern (channel bit string), and information on whether this is “1” or “0” (preceding code). Flag). As shown in FIG. 6, the total detection unit 57 stores three channel bits from the end of the determined conversion pattern (channel bit string), and information indicating whether this is “010” or not (total flag (1 )) And “1” information (general flag (2)). As shown in FIG. 7, the indeterminate bit determination unit 74 corresponds to a table for converting the input data string data pattern (11) into “* 0 *” in Table 4. “000” when the previous channel bit is “1” (when the previous code flag is on), “101” when the previous channel bit is “0” (when the previous code flag is off) Are output respectively.

  Next, the recording method (modulation method) of the modulation device 1 of FIG. 1 will be described with reference to the flowchart of FIG. In step S1, the adder 41 of the DSV control bit determination insertion unit 21 adds a DSV control bit to the input data string. In step S2, the shift register 42 holds the data string to which the DSV control bit supplied from the adder 41 is added in units of 2 bits. In step S3, the conversion pattern processing unit 51 executes conversion pattern detection processing. The details of the processing will be described in detail with reference to FIG. 9. By this, processing for converting 8 data into 12 channel bits, processing for converting 6 data into 9 channel bits, and converting 4 data into 6 channel bits Or a process of converting 2 data into 3 channel bits.

  Next, in step S4, the conversion pattern determination unit 52 executes conversion pattern determination processing. The details of this conversion pattern determination processing will be described later with reference to the flowchart of FIG. 13, and thereby any one of the code patterns converted by the conversion tables 72A to 72D of the conversion pattern processing unit 51 is selected and output.

  In step S5, the minimum run continuous limit pattern detection prediction unit 111 specifies the prediction process, in step S6 the minimum run continuous limit pattern detection unit 112 specifies the minimum run continuous limit pattern detection process, and in step S7, the specific rule conversion pattern detection unit 53 specifies Each rule conversion pattern detection process is executed.

  In practice, the processes in steps S5 to S7 are executed in parallel. As will be described later, the immediately preceding code detection process of FIG. 11 by the immediately preceding code detection unit 56 and the minimum run continuation limited comprehensive detection process of FIG. 12 by the comprehensive detection unit 57 are also executed in parallel.

  The details of the prediction process in step S5 will be described later with reference to the flowchart of FIG. 14. As a result, the code pattern “101 010 101” is included from the middle (seventh bit), and the next channel bit is When it is “010”, the prediction flag (C7) is turned on, the code pattern “101 010 101” is included from the middle (fourth bit), and the next channel bit is “010” The prediction flag (C4) is turned on. Otherwise, the prediction flag is turned off.

  Details of the minimum run continuous restriction pattern detection process in step S6 will be described later with reference to the flowchart of FIG. 15. When the code is the conversion pattern “001 010 101 010 101”, the minimum run continuous restriction pattern detection is performed. When the flag 15 is turned on, the sign is the conversion pattern “101 010 101”, and the next channel bit is “010”, the minimum run continuation restriction pattern detection flag 12 is turned on. Otherwise, the minimum run continuation limited data detection flag is turned off.

  The details of the specific rule conversion pattern detection process in step S7 will be described later with reference to the flowchart of FIG. 16. As a result, the code matches the conversion pattern “010 101 010 101” and the immediately preceding code is “1”. If it is, the specific rule conversion pattern detection flag is turned on.

  Returning to FIG. 8, next, in step S8, the channel bit string conversion unit 55 executes a channel bit string conversion process. The details of the channel bit string conversion process will be described later with reference to the flowchart of FIG. 17, and as a result, the channel bit string is finally determined and output.

  In step S9, the synchronization pattern insertion unit 23 inserts the synchronization pattern into the code string that is finally input from the channel bit string conversion unit 55 and for which the conversion pattern is finalized. In step S10, the NRZI conversion unit 24 converts the code string in which the synchronization pattern supplied from the synchronization pattern insertion unit 23 is inserted into NRZI. In step S11, the recording unit 12 records the recording code string converted to NRZI by the NRZI converting unit 24 on the recording medium 13.

  Next, details of the conversion pattern detection process in step S3 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S51, the conversion pattern detection unit 71 determines whether the data input from the shift register 42 matches the data patterns (00001000) and (00000000). If the input data matches the data pattern (00001000) or (00000000), in step S52, the conversion pattern detection unit 71 outputs conversion pattern determination information of 8 data / 12 channel bits. This information is supplied to the conversion pattern determination unit 52 and the conversion tables 72A to 72D. In step S53, the conversion table 72D converts 8 data into 12 channel bits. Then, the 12 channel bits are supplied to the conversion pattern determination unit 52. That is, when the input data matches the data pattern (00001000) or (00000000), the code string “000 100 100 100” or “010 100 100 100” is output, respectively. The information output in step S52 is used in step S151 of FIG. 13 described later, and the code string converted in step S53 is selected and output in step S152.

  If it is determined in step S51 that the input data does not match the data patterns (00001000) and (00000000), in step S54, the conversion pattern detection unit 71 determines that the input data is a data pattern (000011), ( It is determined whether it matches 000010), (000001), and (000000). If the input data matches any of the four, the conversion pattern detection unit 71 outputs 6 data / 9 channel bit determination information to the conversion pattern determination unit 52 and the conversion tables 72A to 72D in step S55. In step S56, the conversion table 72C converts 6 data into 9 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, if the input data is any one of the data patterns (000011), (000010), (000001), (000000), the code string “000 100 100”, “000 100 000”, “010 100 "100" and "010 100 000" are output respectively. The information output in step S55 is used in step S153 of FIG. 13, and the code string converted in step S56 is selected and output in step S154.

  If it is determined in step S54 that the input data does not match any of the data patterns (000011), (000010), (000001), (000000), the conversion pattern detection unit 71 inputs the data in step S57. It is determined whether the obtained data matches the data patterns (0011), (0010), and (0001). If the input data matches one of these three data patterns, in step S58, the conversion pattern detection unit 71 converts the conversion pattern determination information of 4 data / 6 channel bits into the conversion pattern determination unit 52 and the conversion table 72A. To 72D. In step S59, the conversion table 72B converts the 4 data into 6 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, the code string “010 100” is output when the input data matches the data pattern (0011), and the code string “010 000” is output when the input data matches the data pattern (0010). When the input data matches the data pattern (0001), the code string “000 100” is output. The information output in step S58 is used in step S155 of FIG. 13, and the code string converted in step S59 is selected and output in step S156.

  If it is determined in step S57 that the input data does not match any of the data patterns (0011), (0010), and (0001), the conversion pattern detection unit 71 determines that 2 data / 3 channels in step S60. The bit conversion pattern determination information is output to the conversion pattern determination unit 52 and the conversion tables 72A to 72D. This information is used in steps S157 and S158 in FIG.

  In step S61, the conversion pattern detection unit 71 determines whether the input two data matches the data pattern (11). If the input data matches the data pattern (11), the conversion pattern detection unit 71 outputs indeterminate pattern identification information to the selector 73 in step S62. The indeterminate pattern identification information is used in step S82 of FIG. 10 described later.

  If it is determined in step S61 that the input data does not match the data pattern (11), the process of step S62 is skipped. After the process of step S62, or when it is determined in step S61 that the data does not match the data pattern (11), in step S63, the conversion table 72A performs 2-data / 3-channel bit processing. Details of the 2-data / 3-channel bit processing are shown in the flowchart of FIG.

  Next, details of the 2-data / 3-channel bit processing in step S63 in FIG. 9 will be described with reference to the flowchart in FIG.

  In step S81, the conversion table 72A converts 2 data into 3 channel bits and outputs them to the selector 73. That is, the conversion table 72A outputs the code string “* 0 *” when the input data matches the data pattern (11), and when the input data matches the data pattern (10). The code word “001” is output, and if the input data matches the data pattern (01), the code word “010” is output.

  In step S82, the selector 73 determines whether indefinite pattern identification information has been acquired. If the indeterminate pattern identification information (output in step S62 in FIG. 9) is not acquired from the conversion pattern detection unit 71, the selector 73 outputs 3 channel bits to the conversion pattern determination unit 52 in step S83. Execute the process. Specifically, channel bits “001” and “010” input from the conversion table 72A are output to the conversion pattern determination unit 52. The code string output in step S83 is selected and output in step S160 of FIG.

  On the other hand, if it is determined in step S82 that the indeterminate pattern identification information has been acquired from the conversion pattern detection unit 71, in step S84, the selector 73 converts the three channel bits (“* 0 *”) to the indeterminate bit. The data is output to the determination unit 74. In step S85, the indeterminate bit determination unit 74 determines whether the immediately preceding code flag is on. This immediately preceding code flag is supplied from the immediately preceding code detection unit 56 based on the processing of steps S103 and S104 in FIG. When the immediately preceding code flag is on (when one channel bit of the immediately preceding code word string is “1”), in step S86, the indeterminate bit determining unit 74 converts the code word “000” into the conversion pattern determining unit. Output to 52. On the other hand, when the immediately preceding code flag is not on (off) (when 1 channel bit of the immediately preceding code word string is “0”), the uncertain bit determination unit 74 determines whether the code word is a code word in step S87. “101” is output to the conversion pattern determination unit 52. The code string output in steps S86 and S87 is selected and output in step S159 of FIG.

  Next, the processes of the immediately preceding code detection unit 56 and the comprehensive detection unit 57 will be described with reference to the flowcharts of FIGS.

  First, the immediately preceding code detection process of the immediately preceding code detection unit 56 will be described with reference to the flowchart of FIG.

  In step S101, when the synchronization pattern is inserted immediately before, the immediately preceding code detection unit 56 sets the last channel bit of the insertion pattern as one channel bit of the immediately preceding code word string. That is, the immediately preceding code detection unit 56 determines whether or not a synchronization pattern has been inserted based on the output from the synchronization pattern insertion unit 23. If it has been inserted, the immediately preceding code word in the determination of the next step S102 The last one channel bit of the insertion pattern (synchronization pattern) is selected as one channel bit of the column.

  In step S102, the immediately preceding code detection unit 56 determines from the code string information from the conversion pattern determination unit 52 whether one channel bit of the code string immediately before the next conversion process is “1”. If one channel bit of the immediately preceding code string is “1”, the immediately preceding code detection unit 56 outputs the immediately preceding code flag on in step 103. In contrast, when it is determined in step S102 that one channel bit of the immediately preceding code string is not “1” (when it is determined that it is “0”), in step S104, the immediately preceding code detection unit 56 Outputs the immediately preceding sign flag off. This immediately preceding code flag is output to the indeterminate bit determination unit 74 and the channel bit string conversion unit 55, and is used in step S85 in FIG. 10 and step S284 in FIG.

  Next, the minimum run continuous limited total detection process by the total detection unit 57 will be described with reference to the flowchart of FIG.

  In step S121, when the synchronization pattern is inserted immediately before, the total detection unit 57 sets the last three channel bits of the insertion pattern as the three channel bits of the immediately preceding codeword string. That is, the comprehensive detection unit 57 determines whether a synchronization pattern has been inserted based on the output from the synchronization pattern insertion unit 23, and if it has been inserted, the codeword string immediately before in the determination in the next step S122 As the three channel bits, the last three channel bits of the insertion pattern (synchronization pattern) are selected.

  In step S122, the comprehensive detection unit 57 determines from the code string information from the conversion pattern determination unit 52 whether the three channel bits of the code word string immediately before the next conversion process are “010”. If the three channel bits of the immediately preceding codeword string are “010”, the comprehensive detection unit 57 outputs the minimum run continuation limited total flag (1) on in step S123. If it is determined in step S122 that the three channel bits of the immediately preceding codeword string are not “010” (in the case of “000”, “101”, “001”), in step S124, the total detection unit 57 , Output the minimum run continuation limit comprehensive flag (1) off. The minimum run continuation restriction total flag (1) is output to the channel bit string converter 55 and used in step S285 in FIG.

  In step S125, the comprehensive detection unit 57 determines from the code string information from the conversion pattern determination unit 52 whether one channel bit of the code word string immediately before the next conversion process is “1”. If the one channel bit of the immediately preceding code word string is “1”, the comprehensive detection unit 57 outputs the minimum run continuation limited total flag (2) on in step S126. When it is determined in step S125 that one channel bit of the immediately preceding codeword string is not “1” (when it is “0”), in step S127, the total detection unit 57 determines that the minimum run continuation limited total flag ( 2) Output off. This minimum run continuation restriction total flag (2) is output to the specific rule conversion pattern detection unit 53 and used in step S242 of FIG.

  Next, details of the conversion pattern determination process in step S4 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S151, the conversion pattern determination unit 52 determines whether conversion pattern determination information for 8 data / 12 channel bits has been received. This determination information is output in step S52 of FIG. When the conversion pattern determination information of 8 data / 12 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 8 data / 12 channel bits in step S152. That is, the channel bit converted in step S53 in FIG. 9 is selected and output.

  If it is determined in step S151 that the conversion pattern determination information for 8 data / 12 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 6 data / 9 channel bits in step S153. Determine if it has been received. This determination information is output in step S55 of FIG. When the 6-data / 9-channel bit conversion pattern determination information is received, in step S154, the conversion-pattern determining unit 52 selects and outputs a 6-data / 9-channel bit conversion output. That is, the data output in step S56 in FIG. 9 is selected and output.

  If it is determined in step S153 that the conversion pattern determination information for 6 data / 9 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 4 data / 6 channel bits in step S155. Determine if it has been received. This determination information is output in step S58 of FIG. When the conversion pattern determination information of 4 data / 6 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 4 data / 6 channel bits in step S156. That is, the channel bits converted in step S59 in FIG. 9 are selected and output.

  If it is determined in step S155 that conversion pattern determination information for 4 data / 6 channel bits has not been received, the conversion pattern determination unit 52 converts the conversion pattern determination information for 2 data / 3 channel bits to the conversion pattern in step S157. It is determined whether it has been received from the detection unit 71. This information is output in step S60 of FIG. When the conversion pattern determination information of 2 data / 3 channel bits is received, in step S158, the conversion pattern determination unit 52 further determines that the conversion pattern determination information of 2 data / 3 channel bits is the conversion pattern of data (11). Determine whether it is decision information. That is, it is determined whether the data pattern is likely to be converted into a code including an indeterminate code. If it is determined that the conversion pattern determination information of data (11) has been received, in step S159, the conversion pattern determination unit 52 selects and outputs the three channel bits output from the indeterminate bit determination unit 74. Execute. That is, the code string output in the processing of steps S86 and S87 in FIG. 10 is selected and output.

  On the other hand, when it is determined in step S158 that the conversion pattern determination information of 2 data / 3 channel bits is not the conversion pattern determination information of data (11) (data to be converted into a code including an indeterminate code). In step S160, the conversion pattern determination unit 52 selects and outputs the three channel bits of the selector 73. That is, in this case, the code string output in step S83 in FIG. 10 is selected and output.

  When the conversion pattern is determined as described above, the data string is shifted in the shift register 42 by an amount corresponding to the determined channel bit, and the conversion pattern determination process for the next data is executed.

  Next, details of the prediction process in step S5 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S181, the minimum run continuation limited pattern detection prediction unit 111 clears the prediction flag. That is, the prediction flags (C7) and (C4) output in steps S184 and S187 described later are cleared. In step S182, the minimum run continuation limited pattern detection prediction unit 111 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “xxx xxx 101 010 101”. If the input code matches the code pattern “xxx xxx 101 010 101” (the code matches the code pattern “101 010 101” from the seventh bit), in step S183, the minimum run continuation limited pattern detection prediction Unit 111 determines whether the next channel bit is “010”. When the next channel bit is “010”, in step S184, the minimum run continuation limited pattern detection prediction unit 111 uses the prediction flag (C7) on as the minimum run continuation limited data detection prediction information, and the channel bit string conversion unit 55 Output to. This flag is used in step S282 of FIG. 17 described later.

  If it is determined in step S182 that the code does not match the code pattern “xxx xxx 101 010 101”, in step S185, the minimum run continuation limited pattern detection prediction unit 111 determines that the code is the code pattern “xxx 101 010 101”. Determine whether they match. If the input code matches the code pattern “xxx 101 010 101” (the code matches the code pattern “101 010 101” from the fourth bit), in step S186, the minimum run continuation limited pattern detection prediction unit 111 determines whether the next channel bit is “010”. When the next channel bit is “010”, in step S187, the minimum run continuation limited pattern detection prediction unit 111 uses the prediction flag (C4) on as the minimum run continuation limited data detection prediction information, and the conversion pattern determination unit 52 Output to. This flag is used in step S294 of FIG.

  If it is determined in step S183 that the next channel bit is not “010” (“000”, “101”, or “001”), the code is a code pattern “xxx 101 010 101” in step S185. If it is determined that it does not match “”, or if it is determined in step S186 that the next channel bit is not “010” (“000”, “101”, or “001”), step S188 , The minimum run continuation limited pattern detection prediction unit 111 outputs the prediction flag off. This prediction flag off means that the prediction flag (C7) generated in step S184 is off, and also means that the prediction flag (C4) generated in step S187 is off.

  Next, the minimum run continuation restriction pattern detection process in step S6 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S201, the minimum run continuation restriction pattern detection unit 112 clears the detection flag. That is, the minimum run continuation restriction pattern detection flags 15 and 12 output in steps S203 and S206 described later are cleared. In step S202, the minimum run continuation restriction pattern detection unit 112 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “001 010 101 010 101”. If the input code matches the code pattern “001 010 101 010 101”, in step S203, the minimum run continuous restriction pattern detection unit 112 detects the minimum run continuous restriction pattern detection flag 15on and detects the minimum run continuous restriction pattern. Information is output to the channel bit string converter 55. This flag is used in step S281 of FIG. 17 described later.

  When it is determined in step S202 that the code does not match the code pattern “001 010 101 010 101”, in step S204, the minimum run continuation limited pattern detection unit 112 matches the code with the code pattern “101 010 101”. Determine whether. If the input code matches the code pattern “101 010 101”, in step S205, the minimum run continuation restriction pattern detection unit 112 determines whether the next three channel bits are “010”. If the next three channel bits are “010”, in step S206, the minimum run continuous restriction pattern detection unit 112 converts the channel bit string using the minimum run continuous restriction pattern detection flag 12on as the minimum run continuous restriction pattern detection information. Output to unit 55. This flag is used in step S290 of FIG.

  If it is determined in step S204 that the input code does not match the code pattern “101 010 101”, and if it is determined in step S205 that the next three channel bits are not “010”, step In S207, the minimum run continuation restriction pattern detection unit 112 outputs the minimum run continuation restriction data detection flag off to the channel bit string conversion unit 55. The off of the minimum run continuation restriction data detection flag means that the minimum run continuation restriction pattern detection flag 15 is off and that the minimum run continuation restriction pattern detection flag 12 is off.

  Next, the specific rule conversion pattern detection process in step S7 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S241, the specific rule conversion pattern detection unit 53 determines whether the code matches the code pattern “010 101 010 101”. If the code matches the code pattern “010 101 010 101”, the specific rule conversion pattern detection unit 53 determines in step S242 whether the minimum run continuation restriction general flag (2) is on. This flag is generated by the comprehensive detection unit 57 in the processing of steps S126 and S127 in FIG. When the minimum run continuation restriction total flag (2) is on (when the immediately preceding one channel bit is “1”), in step S243, the specific rule conversion pattern detection unit 53 sets the specific rule conversion pattern detection flag on. Is output. This flag is used in step S293 in FIG.

  The code string “010 101 010 101” is an even-oddity preservation violation individual conversion code pattern. When the even-oddity preservation violation pattern (01110111) is individually divided and converted in units of 2 bits (data pattern (01), ( 11) (when converted as (01), (11)). Also, on of the minimum run continuation limit comprehensive flag (2) means that the immediately preceding channel bit is “1”, so that the on of the specific rule conversion pattern detection flag is even or odd that constitutes the conversion pattern of the specific rule. This means that there is a possibility that the data storage violation data pattern (01110111) is a converted code pattern.

  When it is determined in step S241 that the code does not match the code pattern “010 101 010 101”, and in step S242, it is determined that the minimum run continuation limited total flag (2) is not on (is off). In the case (when the immediately preceding one channel bit is “0”), in step S244, the specific rule conversion pattern detection unit 53 outputs a specific rule conversion pattern detection flag off.

  Next, details of the channel bit string conversion process in step S8 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S281, the channel bit string converter 55 determines whether the minimum run continuation restriction pattern detection flag 15 is on. This flag is output in steps S203 and S207 in FIG. When it is determined in step S281 that the minimum run continuation limited pattern detection flag 15 is on (when the code is the code pattern “001 010 101 010 101”), in step S282, the channel bit string converting unit 55 Determine whether C7) is on. The prediction flag (C7) is output in steps S184 and S188 in FIG. If the prediction flag (C7) is off (the code string is not “xxx xxx 101 010 101”, or even if the next channel bit is not “010”), the channel is set in step S283. The bit string conversion unit 55 converts the code string “001 010 101 010 101” to “$ 0 $ 010 000 000 101”.

  Further, in step S284, the channel bit string converting unit 55 determines whether the immediately preceding code flag is on. The immediately preceding code flag is output in steps S103 and S104 in FIG. When the immediately preceding code flag is on (when 1 channel bit of the immediately preceding code word string is “1”), in step S288, the channel bit string converting unit 55 does not include the error included in the code string converted in step S283. The confirmed codeword “$ 0 $” is set to “000”. In step S289, the channel bit string converting unit 55 outputs the code string “000 010 000 000 101”.

  When it is determined in step S284 that the immediately preceding code flag is not on (is off) (when one channel bit of the immediately preceding code word string is “0”), in step S285, the channel bit string converting unit 55 It is determined whether the minimum run continuous restriction total flag (1) is on. The minimum run continuation limit comprehensive flag (1) is output in steps S123 and S124 in FIG. When the minimum run continuation restriction total flag (1) is on (when the 3 channel bits of the immediately preceding codeword string are “010”), as in the case where the immediately preceding code flag is on, step S288, The process of S289 is executed.

  On the other hand, when it is determined that the minimum run continuation restriction total flag (1) is not on (is off) (when the three channel bits of the immediately preceding codeword string are not “010”), in step S286 The channel bit string conversion unit 55 converts the indeterminate code word “$ 0 $” converted in step S283 into “101”. In step S287, the channel bit string conversion unit 55 outputs the code string “101 010 000 000 101”.

  When it is determined in step S281 that the minimum run continuation restriction pattern detection flag 15 is not on (is off) (when the code string is not “001 010 101 010 101”), the channel bit string conversion unit 55 in step S290 Then, it is determined whether the minimum run continuous restriction pattern detection flag 12 is on. This detection flag is output in steps S206 and S207 in FIG. When the minimum run continuation restriction pattern detection flag 12 is on (when the code string is “101 010 101” and the next three channel bits are “010”), a channel bit string conversion unit in step S291 55 converts the code string “101 010 101” into a code string “001 000 000”. In step S292, the channel bit string converting unit 55 outputs the code string “001 000 000” converted in step S291.

  When it is determined in step S290 that the minimum run continuation limited pattern detection flag 12 is not on (is off) (the code string is not “101 010 101”, or the next three channel bits Is not “010”), in step S293, the channel bit string conversion unit 55 determines whether the specific rule conversion pattern detection flag is on. This flag is output in steps S243 and S244 in FIG. If it is determined in step S293 that the specific rule conversion pattern detection flag is on (if the code string is “010 101 010 101” and the immediately preceding code is “1”), the channel in step S294 The bit string conversion unit 55 determines whether the prediction flag (C4) is on. This flag is output in steps S187 and S188 in FIG.

  The fact that the specific rule conversion pattern detection flag is on means that the even-oddity preservation violation pattern (01110111) constituting the conversion pattern of the specific rule may have been converted. If the prediction flag (C4) is not on (is off), the code string is “xxx 101 010 101” and the next three channel bits are not “010”. The target code is a code obtained by converting the even-oddity preservation violation data pattern (01110111). Therefore, in step S295, the channel bit string conversion unit 55 converts the code string “010 101 010 101” into an even-oddity preservation violation code pattern “010 000 000 101”. In step S296, the channel bit string conversion unit 55 outputs the code string “010 000 000 101” converted in step S295.

  If it is determined in step S282 that the prediction flag (C7) is on (the minimum run continuation restriction pattern detection flag 15 is on, the code string is “xxx xxx 101 010 101”, and the next channel bit is If it is “010”, if it is determined in step S293 that the specific rule conversion pattern detection flag is not on (off) (the code string is not “010 101 010 101” or is). Even if the immediately preceding code is not “1”) and when it is determined in step S294 that the prediction flag (C4) is on (the specific rule conversion pattern detection flag is on, and the code string is When “xxx 101 010 101” and the next three channel bits are “010”), in step S297, the channel bit string conversion unit 55 outputs the input channel bit string as it is. That is, in this case, the conversion pattern determined by the conversion pattern determination unit 52 is output as it is as a code string.

  The processing of the conversion pattern processing unit 51 in the above processing will be further described as shown in FIG. That is, the conversion pattern is detected by referring to 8 data from the input data string and comparing whether or not it matches the conversion table of 8 data of constraint length i = 4 in Table 4. If there is a matching pattern, the conversion pattern is determined based on the information from the conversion table 72D. If it does not match, up to 6 data are referred to and compared with the conversion table of 6 data with constraint length i = 3 in Table 4 to compare. If there is a matching pattern, the conversion pattern is determined based on the information from the conversion table 72C. If it does not match, up to 4 data are referred to and compared with the conversion table of 4 data with constraint length i = 2 in Table 4. If there is a matching pattern, the conversion pattern is determined based on the information from the conversion table 72B. If they do not match, the last two data are referenced, and whether or not they match in the two data tables (11), (10), (01) with constraint length i = 1 in Table 4 is compared. The A conversion pattern for the matching pattern is determined based on information from the conversion table 72A.

  Further, the processing of the minimum run continuation restriction pattern processing unit 54 and the specific rule conversion pattern detection unit 53 is summarized as shown in FIG. That is, when the code is the code pattern “xxx xxx 101 010 101” and the next channel bit is “010”, the minimum run continuation limited pattern detection prediction unit 111 turns on the prediction flag (C7), and so on. Otherwise it is off. The minimum run continuation limited pattern detection prediction unit 111 turns on the prediction flag (C4) when the code is the code pattern “xxx 101 010 101” and the next channel bit is “010”, and so on. If not, set to off.

  When the minimum run continuation restriction pattern detection unit 112 detects that the code is the code pattern “001 010 101 010 101”, the minimum run continuation restriction pattern detection flag 15 is turned on and the prediction flag (C7) is turned off. The channel bit string “001 010 101 010 101” is converted to the channel bit string “$ 0 $ 010 000 000 101”. On the other hand, even if the minimum run continuation restriction pattern detection flag 15 is on, if the prediction flag (C7) is on, the code pattern “001 010 101 010 101” is not converted.

  If the code is not the code pattern “001 010 101 010 101”, then it is determined whether the code pattern is “101 010 101” and the next channel bit string is “010”, and if so, The minimum run continuation restriction pattern detection flag 12 is turned on, otherwise it is turned off. When the minimum run continuation restriction pattern detection flag 12 is on, the channel bit string “101 010 101” is converted to the channel bit string “001 000 000”. On the other hand, when the minimum run continuous restriction pattern detection flag 12 is off, the conversion process is not performed.

  Further, regarding the specific rule conversion pattern detection flag in the specific rule conversion pattern detection unit 53, when the code pattern “010 101 010 101” is detected and the immediately preceding code is “1”, the specific rule conversion pattern detection flag Is turned on, or if the code pattern “010 101 010 101” is not detected, or if the code immediately before it is detected is not “1”, the specific rule conversion pattern detection flag is turned off. When the specific rule conversion pattern detection flag is on and the prediction flag (C4) is off, the channel bit string “010 101 010 101” is converted to the channel bit string (even-oddity preservation violation code pattern) “010 000 000 101” Is done. On the other hand, even if the specific rule conversion pattern detection flag is on, if the prediction flag (C4) is on, the code pattern “010 101 010 101” is not converted. Also, the conversion process is not performed when the specific rule conversion pattern detection flag is off.

  As described above, the basic configuration is the same as that of the 1,7PP code, that is, the minimum run d = 1, the maximum run k = 7, and the conversion rate (m: n) = (2: 3). DSV control is efficiently performed by inserting one DSV control bit at a predetermined position in the area, and the number of consecutive minimum runs even when a synchronization pattern with a predetermined identification bit is inserted. Thus, it is possible to realize a conversion table and a modulation device that limit error propagation to 5 times and improve error propagation characteristics during recording and reproduction.

The order of arrangement within the data pattern and code pattern constraint lengths in Table 4 may be changed within the rules of the present invention. For example, the portion of the constraint length i = 1 in Table 4 shown in Table 5 may be arranged as shown in Table 6 below.
<Table 5>
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010
<Table 6>
Data pattern Code pattern i = 1 11 * 0 *
10 010
01 001
Even in this case, the number of data patterns “1” and the number of code patterns “1” are divided so that the remainder when divided by 2 is 1 or 0.

  In addition, (1) and (0) of each element of the data string in Table 4 may be inverted. That is, the part shown in Table 7 of Table 4 may be configured as shown in Table 8. Even in this case, the number of the data pattern “1” and the number of the code pattern “1” divided by 2 are both equal to 1 or 0.

<Table 7>
Data pattern Code pattern
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
………
<Table 8>
Data pattern Code pattern
00 * 0 *
01 001
10 010
1100 010 100
1101 010 000
1110 000 100
………

  In addition, the fact that the final code word of the conversion pattern or synchronization pattern determined immediately before by the specific rule conversion pattern detection unit 53 is “1” (final run continuation restriction total flag (2)) is used for detection. When the position of the synchronization pattern inserted at a predetermined interval is used as information, it matches with (01110111) immediately after the insertion of the synchronization pattern, and when the subsequent channel bit string is not “010”, the specific rule conversion pattern of 8 data Detection processing may be performed. Even in this case, the conditions of the DSV control interval by the specific rule pattern in which DSV control cannot be performed are the same as those described above.

  Then, when the table is changed as the supply destination of the flags output by the immediately preceding code detection unit 56 and the comprehensive detection unit 57, and the position of the indeterminate bit is changed, the flag may be supplied to the changed position.

  FIG. 20 shows the configuration of another embodiment of the modulation device 1 of the present invention. The basic configuration in this embodiment is the same as in the embodiment of FIG. 3, but in the embodiment of FIG. 3, the output from the immediately preceding code detection unit 56 is the conversion pattern processing unit 51 and the channel bit string conversion. However, in this embodiment, the signal is supplied only to the channel bit string converter 55. Further, the output from the comprehensive detection unit 57 is not supplied to the specific rule conversion pattern detection unit 53 but is supplied only to the channel bit string conversion unit 55. In the embodiment of FIG. 20, the channel bit string conversion unit 55 detects the indeterminate bit and detects whether the last code word of the conversion pattern or synchronization pattern determined immediately before is “1”. Done.

  FIG. 21 shows a more detailed configuration of the modulation device 1 of FIG. The basic configuration is the same as that in FIG. 4 except that the indeterminate bit determination unit 74 is omitted in the conversion pattern processing unit 51.

  22 to 32 are flowcharts for explaining the operation of the modulation device 1 shown in FIGS.

  FIG. 22 shows a recording process (modulation method) of the modulation device 1 shown in FIGS.

  In step S401, the adder 41 of the DSV control bit determination insertion unit 21 adds a DSV control bit to the input data string. In step S402, the shift register 42 holds the data string to which the DSV control bit supplied from the adder 41 is added in units of 2 bits.

  In step S403, the conversion pattern processing unit 51 executes conversion pattern detection processing. The details of the conversion pattern detection processing will be described later with reference to the flowchart of FIG. 23. By this, processing for converting 8 data into 12 channel bits, processing for converting 6 data into 9 channel bits, and processing 4 data with 6 channel bits. Or a process of converting 2 data into 3 channel bits.

  In step S404, the conversion pattern determination unit 52 executes conversion pattern determination processing. The details of this conversion pattern determination processing will be described later with reference to the flowchart of FIG. 27, whereby one of the code patterns converted by the conversion tables 72A to 72D of the conversion pattern processing unit 51 is selected and output.

In step S405, the minimum run continuous limit pattern detection prediction unit 111 specifies the prediction process, in step S406 the minimum run continuous limit pattern detection unit 112 specifies the minimum run continuous limit pattern detection process, and in step S407, the specific rule conversion pattern detection unit 53 specifies Each rule conversion pattern detection process is executed.

  In practice, the processes in steps S405 to S407 are executed in parallel.

  The details of the prediction process in step S405 will be described later with reference to the flowchart of FIG. 28. As a result, the conversion pattern “101 010 101” is included in the channel bit string from the middle (seventh bit), and When the channel bit is “010”, the prediction flag (C7) is turned on, the conversion pattern “101 010 101” is included from the middle (fourth bit), and the next channel bit is “010”. If it is, the prediction flag (C4) is turned on. Otherwise, the prediction flag is turned off.

  Details of the minimum run continuous restriction pattern detection process in step S406 will be described later with reference to the flowchart of FIG. 29. When the channel bit string is the conversion pattern “001 010 101 010”, the minimum run continuous restriction pattern detection is performed. Flag 15 is turned on. When the channel bit string is the conversion pattern “101 010 101” and the next channel bit is “010”, the minimum run continuation restriction pattern detection flag 12 is turned on. Otherwise, the minimum run continuation limited data detection flag is turned off.

  Details of the specific rule conversion pattern detection process in step S407 will be described later with reference to the flowchart of FIG. 30. Thus, when the channel bit string is the conversion pattern “010 101 010 101”, the specific rule conversion pattern detection is performed. The flag is turned on.

  In step S408, the channel bit string conversion unit 55 performs a channel bit string conversion process. The details of this channel bit string conversion processing will be described later with reference to the flowchart of FIG. 31. Thus, processing when the minimum run continuous restriction pattern detection flag 15 and the minimum run continuous restriction pattern detection flag 12 are on, as well as specifying Processing is performed when the rule conversion pattern detection flag and the prediction flag (C4) are off. In addition, an indeterminate code conversion process is also performed here.

  In step S409, the synchronization pattern insertion unit 23 inserts the synchronization pattern into the code string that is finally input from the channel bit string conversion unit 55 and whose conversion pattern is finalized. In step S410, the NRZI conversion unit 24 converts the code string in which the synchronization pattern supplied from the synchronization pattern insertion unit 23 is inserted into NRZI. In step S411, the recording unit 12 records the recording code string converted to NRZI by the NRZI converting unit 24 on the recording medium 13.

  Next, the details of the conversion pattern detection processing in step S403 in FIG. 22 will be described with reference to the flowchart in FIG.

  In step S451, the conversion pattern detection unit 71 determines whether the data input from the shift register 42 matches the data patterns (00001000) and (00000000). If the input data matches the data pattern (00001000) or (00000000), in step S452, the conversion pattern detection unit 71 outputs conversion pattern determination information of 8 data / 12 channel bits. This information is supplied to the conversion pattern determination unit 52 and the conversion tables 72A to 72D. In step S453, the conversion table 72D converts 8 data into 12 channel bits. Then, the 12 channel bits are supplied to the conversion pattern determination unit 52. That is, when the input data matches the data pattern (00001000) or (00000000), the code string “000 100 100 100” or “010 100 100 100” is output, respectively. The information output in step S452 is used in step S551 of FIG. 27 described later, and the code string converted in step S453 is selected and output in step S552.

  If it is determined in step S451 that the input data does not match the data patterns (00001000) and (00000000), in step S454, the conversion pattern detection unit 71 determines that the input data is the data pattern (000011), ( It is determined whether it matches 000010), (000001), and (000000). If the input data matches any of the four, the conversion pattern detection unit 71 outputs 6 data / 9 channel bit determination information to the conversion pattern determination unit 52 and the conversion tables 72A to 72D in step S455. In step S456, the conversion table 72C converts 6 data into 9 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, when the input data is one of the data patterns (000011), (000010), (000001), (000000), the code string “000 100 100”, “000 100 000”, “010 100” "100" and "010 100 000" are output respectively. The information output in step S455 is used in step S553 in FIG. 27, and the code string converted in step S456 is selected and output in step S554.

  If it is determined in step S454 that the input data does not match any of the data patterns (000011), (000010), (000001), and (000000), the conversion pattern detection unit 71 inputs the data in step S457. It is determined whether the obtained data matches the data patterns (0011), (0010), and (0001). If the input data matches any of these three data patterns, in step S458, the conversion pattern detection unit 71 converts the conversion pattern determination information of 4 data / 6 channel bits into the conversion pattern determination unit 52 and the conversion table 72A. To 72D. In step S459, the conversion table 72B converts the 4 data into 6 channel bits and outputs the converted data to the conversion pattern determination unit 52. That is, the code string “010 100” is output when the input data matches the data pattern (0011), and the code string “010 000” is output when the input data matches the data pattern (0010). When the input data matches the data pattern (0001), the code string “000 100” is output. The information output in step S458 is used in step S555 of FIG. 27, and the code string converted in step S459 is selected and output in step S556.

  If it is determined in step S457 that the input data does not match any of the data patterns (0011), (0010), and (0001), the conversion pattern detection unit 71 determines that 2 data / 3 channels in step S460. The bit conversion pattern determination information is output to the conversion pattern determination unit 52 and the conversion tables 72A to 72D. This information is used in steps S557 and S558 in FIG.

  In step S461, the conversion pattern detection unit 71 determines whether the input two data matches the data pattern (11). If the input data matches the data pattern (11), the conversion pattern detection unit 71 outputs indeterminate pattern identification information to the selector 73 in step S462. The indeterminate pattern identification information is used in step S482 in FIG. 24 described later.

  If it is determined in step S461 that the input data does not match the data pattern (11), the process of step S462 is skipped. After the process of step S462, or when it is determined in step S461 that the data does not match the data pattern (11), in step S463, the conversion table 72A performs 2-data / 3-channel bit processing. Details of the 2-data / 3-channel bit processing are shown in the flowchart of FIG.

  Next, the details of the 2-data / 3-channel bit processing in step S463 of FIG. 23 will be described with reference to the flowchart of FIG.

  In step S481, the conversion table 72A converts 2 data into 3 channel bits and outputs them to the selector 73. That is, the conversion table 72A outputs the code string “* 0 *” when the input data matches the data pattern (11), and when the input data matches the data pattern (10). Outputs the code word “001”, and outputs the code word “010” when the input data matches the data pattern (01).

  In step S482, the selector 73 determines whether indeterminate pattern identification information has been acquired. If the indeterminate pattern identification information (output in step S462 in FIG. 23) is not acquired from the conversion pattern detection unit 71, the selector 73 outputs 3 channel bits to the conversion pattern determination unit 52 in step S483. Execute the process. Specifically, channel bits “001” and “010” input from the conversion table 72A are output to the conversion pattern determination unit 52. The code string output in step S483 is selected and output in step S560 of FIG.

  On the other hand, when it is determined in step S482 that the indeterminate pattern identification information has been acquired from the conversion pattern detection unit 71, the selector 73 determines 3 channel bits (“* 0 *”) as the conversion pattern in step S484. To the unit 52. This output is processed in steps S698 and S699 of FIG. For the output of “* 0 *”, information for final determination is not yet provided here, so it is assumed to be “101”, for example. Of course, “000” is also acceptable.

  Next, the immediately preceding code detection process of the immediately preceding code detection unit 56 will be described with reference to the flowchart of FIG. This process is basically the same as the immediately preceding code detection process of FIG.

  That is, in step S491, when the synchronization pattern is inserted immediately before, the immediately preceding code detection unit 56 sets the last channel bit of the insertion pattern as one channel bit of the immediately preceding code word string. That is, the immediately preceding code detection unit 56 determines whether or not a synchronization pattern is inserted based on the output from the synchronization pattern insertion unit 23, and if it is inserted, the immediately preceding code in the determination in the next step S492. The last one channel bit of the insertion pattern (synchronization pattern) is selected as one channel bit of the word string.

  In step S492, the immediately preceding code detection unit 56 determines from the code string information from the conversion pattern determination unit 52 whether one channel bit of the code string immediately before the next conversion process is “1”. When one channel bit of the immediately preceding code string is “1”, the immediately preceding code detection unit 56 outputs the immediately preceding code flag on in step S493. On the other hand, when it is determined in step S492 that one channel bit of the immediately preceding code string is not “1” (when it is determined to be “0”), in step S494, the immediately preceding code detection unit 56 Outputs the immediately preceding sign flag off. This immediately preceding code flag is output to the conversion pattern determination unit 52 and used in step S684 of FIG.

  Next, the minimum run continuous limited total detection process by the total detection unit 57 will be described with reference to the flowchart of FIG. This process is basically the same process as the minimum run continuous restriction total detection process of FIG.

  That is, in step S521, when the synchronization pattern is inserted immediately before, the total detection unit 57 sets the last 3 channel bits of the insertion pattern as the 3 channel bits of the immediately preceding code word string. That is, the comprehensive detection unit 57 determines whether a synchronization pattern is inserted based on the output from the synchronization pattern insertion unit 23, and if it is inserted, the codeword immediately before in the determination in the next step S522. As the 3 channel bits of the column, the last 3 channel bits of the insertion pattern (synchronization pattern) are selected.

  In step S522, based on the code string information from the conversion pattern determination unit 52, the overall detection unit 57 determines whether the three channel bits of the code word string immediately before the next conversion process are “010”. If the three channel bits of the immediately preceding codeword string are “010”, the comprehensive detection unit 57 outputs the minimum run continuation limited total flag (1) on in step S523. When it is determined in step S522 that the three channel bits of the immediately preceding codeword string are not “010” (in the case of “000”, “101”, “001”), in step S524, the total detection unit 57 , Output the minimum run continuation limit comprehensive flag (1) off. The minimum run continuation restriction total flag (1) is output to the conversion pattern determination unit 52 and used in step S685 in FIG.

  In step S525, the comprehensive detection unit 57 determines from the code string information from the conversion pattern determination unit 52 whether one channel bit of the code word string immediately before the next conversion process is “1”. If the channel bit of the immediately preceding codeword string is “1”, in step S526, the total detection unit 57 outputs the minimum run continuation limit total flag (2) on. When it is determined in step S525 that one channel bit of the immediately preceding codeword string is not “1” (when it is “0”), in step S527, the total detection unit 57 determines the minimum run continuation limited total flag ( 2) Output off. The minimum run continuation restriction total flag (2) is output to the conversion pattern determination unit 52 and used in step S694 in FIG.

  FIG. 27 shows the conversion pattern determination process in step S404 of FIG. The conversion pattern determination processing in steps S551 to S560 shown in FIG. 27 is basically the same processing as the processing in steps S151 to S160 in FIG. 13, but the processing in steps S559 and S560 is the corresponding step S159 in FIG. Therefore, it is different from the processing of S160.

  That is, in the conversion pattern determination process of FIG. 27, in step S551, the conversion pattern determination unit 52 determines whether conversion pattern determination information for 8 data / 12 channel bits has been received. This determination information is output in step S452 of FIG. When the conversion pattern determination information of 8 data / 12 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 8 data / 12 channel bits in step S552. That is, the channel bits converted in step S453 in FIG. 23 are selected and output.

  If it is determined in step S551 that the conversion pattern determination information for 8 data / 12 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 6 data / 9 channel bits in step S553. Determine if it has been received. This determination information is output in step S455 of FIG. When the 6-data / 9-channel bit conversion pattern determination information is received, in step S554, the conversion-pattern determining unit 52 selects and outputs a 6-data / 9-channel bit conversion output. That is, the data output in step S456 of FIG. 23 is selected and output.

  If it is determined in step S553 that the conversion pattern determination information for 6 data / 9 channel bits has not been received, the conversion pattern determination unit 52 determines the conversion pattern determination information for 4 data / 6 channel bits in step S555. Determine if it has been received. This determination information is output in step S458 of FIG. When the conversion pattern determination information of 4 data / 6 channel bits is received, the conversion pattern determination unit 52 selects and outputs the conversion output of 4 data / 6 channel bits in step S556. That is, the channel bits converted in step S459 in FIG. 23 are selected and output.

  If it is determined in step S555 that the conversion pattern determination information for 4 data / 6 channel bits has not been received, the conversion pattern determination unit 52 converts the conversion pattern determination information for 2 data / 3 channel bits to the conversion pattern in step S557. It is determined whether it has been received from the detection unit 71. This information is output in step S460 of FIG. When the conversion pattern determination information of 2 data / 3 channel bits is received, the conversion pattern determination unit 52 further determines that the conversion pattern determination information of 2 data / 3 channel bits is the conversion pattern of data (11) in step S558. Determine whether it is decision information. That is, it is determined whether the data pattern is likely to be converted into a code including an indeterminate code. If it is determined that the conversion pattern determination information of the data (11) has been received, in step S559, the conversion pattern determination unit 52 executes a process of selecting and outputting three channel bits including an indeterminate bit. That is, the code string output in the process of step S484 in FIG. 24 is selected and output.

  On the other hand, if it is determined in step S558 that the conversion pattern determination information of 2 data / 3 channel bits is not the conversion pattern determination information of data (11) (data to be converted into a code including an indeterminate code). In step S560, the conversion pattern determination unit 52 selects and outputs three channel bits that originally do not include an indeterminate bit. That is, in this case, the code string output in step S483 in FIG. 24 is selected and output.

  When the conversion pattern is determined as described above, the data string is shifted in the shift register 42 by an amount corresponding to the determined channel bit, and the conversion pattern determination process for the next data is executed.

  Next, the details of the prediction process in step S405 in FIG. 22 will be described with reference to the flowchart in FIG. This process is basically the same as the prediction process of FIG.

  In step S581, the minimum run continuation limited pattern detection prediction unit 111 clears the prediction flag. That is, the prediction flags (C7) and (C4) output in steps S584 and S587 described later are cleared. In step S582, the minimum run continuation limited pattern detection prediction unit 111 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “xxx xxx 101 010 101”. If the input code matches the code pattern “xxx xxx 101 010 101” (the code matches the code pattern “101 010 101” from the seventh bit), in step S583, the minimum run continuation limited pattern detection prediction Unit 111 determines whether the next channel bit is “010”. When the next channel bit is “010”, in step S584, the minimum run continuation limited pattern detection prediction unit 111 uses the prediction flag (C7) on as the minimum run continuation limited data detection prediction information, and the channel bit string conversion unit 55 Output to. This flag is used in step S682 in FIG.

  If it is determined in step S582 that the code does not match the code pattern “xxx xxx 101 010 101”, in step S585, the minimum run continuation limited pattern detection prediction unit 111 determines that the code is the code pattern “xxx 101 010 101”. Determine whether they match. If the input code matches the code pattern “xxx 101 010 101” (the code matches the code pattern “101 010 101” from the fourth bit), in step S586, the minimum run continuation limited pattern detection prediction unit 111 determines whether the next channel bit is “010”. If the next channel bit is “010”, in step S587, the minimum run continuation limited pattern detection prediction unit 111 uses the prediction flag (C4) on as the minimum run continuation limited data detection prediction information, and the conversion pattern determination unit 52 Output to. This flag is used in step S695 of FIG.

  If it is determined in step S583 that the next channel bit is not “010” (“000”, “101”, or “001”), the code is a code pattern “xxx 101 010 101” in step S585. If it is determined that it does not match “”, or if it is determined in step S586 that the next channel bit is not “010” (“000”, “101”, or “001”), step S588 , The minimum run continuation limited pattern detection prediction unit 111 outputs the prediction flag off. The prediction flag off means that the prediction flag (C7) generated in step S584 is turned off, and also means that the prediction flag (C4) generated in step S587 is off.

  Next, the minimum run continuation restriction pattern detection process in step S406 of FIG. 22 will be described with reference to the flowchart of FIG. This process is basically the same process as the minimum run continuous restriction pattern detection process of FIG.

  That is, in step S601, the minimum run continuation restriction pattern detection unit 112 clears the detection flag. That is, the minimum run continuation restriction pattern detection flags 15 and 12 output in steps S603 and S606 described later are cleared. In step S602, the minimum run continuation restriction pattern detection unit 112 determines whether the code supplied from the conversion pattern determination unit 52 matches the code pattern “001 010 101 010 101”. If the input code matches the code pattern “001 010 101 010 101”, in step S603, the minimum run continuous restriction pattern detection unit 112 detects the minimum run continuous restriction pattern detection flag 15on and detects the minimum run continuous restriction pattern. Information is output to the channel bit string converter 55. This flag is used in step S681 of FIG.

  When it is determined in step S602 that the code does not match the code pattern “001 010 101 010 101”, in step S604, the minimum run continuation limited pattern detection unit 112 matches the code with the code pattern “101 010 101”. Determine whether. If the code matches the code pattern “101 010 101”, in step S605, the minimum run continuation restriction pattern detection unit 112 determines whether the next three channel bits are “010”. If the next three channel bits are “010”, in step S606, the minimum run continuous restriction pattern detection unit 112 converts the channel bit string using the minimum run continuous restriction pattern detection flag 12on as the minimum run continuous restriction pattern detection information. Output to unit 55. This flag is used in step S690 of FIG.

  If it is determined in step S604 that the input code does not match the code pattern “101 010 101”, and if it is determined in step S605 that the next three channel bits are not “010”, step In S607, the minimum run continuation restriction pattern detection unit 112 outputs the minimum run continuation restriction data detection flag off to the channel bit string conversion unit 55. The off of the minimum run continuation restriction data detection flag means that the minimum run continuation restriction pattern detection flag 15 is off and that the minimum run continuation restriction pattern detection flag 12 is off.

  Next, the specific rule conversion pattern detection process in step S407 of FIG. 22 will be described with reference to the flowchart of FIG. This process is basically the same as the specific rule conversion pattern detection process in FIG. 16, except that step S242 is inserted between steps S641 and S642 in FIG. 30 corresponding to steps S241 and S243 in FIG. Is different.

  That is, in step S641, the specific rule conversion pattern detection unit 53 determines whether the code matches the code pattern “010 101 010 101”. If the code matches the code pattern “010 101 010 101”, the specific rule conversion pattern detection unit 53 outputs a specific rule conversion pattern detection flag on in step S642. This flag is used in step S693 of FIG.

  The code string “010 101 010 101” matches the code string obtained when the even-oddity preservation violation pattern (01110111) is individually divided and converted in units of 2 bits. That is, on of the specific rule conversion pattern detection flag means that the even-oddity preservation violation pattern (01110111) constituting the conversion pattern of the specific rule may have been converted.

  If it is determined in step S641 that the code does not match the code pattern “010 101 010 101”, the specific rule conversion pattern detection unit 53 outputs a specific rule conversion pattern detection flag off in step S643.

  Next, details of the channel bit string conversion process in step S408 of FIG. 22 will be described with reference to the flowchart of FIG. This process is basically the same as the channel bit string conversion process in FIG. 17, but step S694 is inserted between steps S693 and S695 corresponding to steps S293 and S294 in FIG. The difference is that step S698 is inserted between steps S693 and S700 corresponding to steps S293 and S297.

  In step S681, the channel bit string converter 55 determines whether the minimum run continuation restriction pattern detection flag 15 is on. This flag is output in steps S603 and S607 in FIG. If it is determined in step S681 that the minimum run continuation restriction pattern detection flag 15 is on, in step S682, the channel bit string conversion unit 55 determines whether the prediction flag (C7) is on. This prediction flag (C7) is output in steps S584 and S588 in FIG. If the prediction flag (C7) is off (the code string is not “xxx xxx 101 010 101”, or even if the next channel bit is not “010”), the channel is set in step S683. The bit string conversion unit 55 converts the code string “001 010 101 010 101” to “$ 0 $ 010 000 000 101”.

  In step S684, the channel bit string converter 55 determines whether the immediately preceding code flag is on. This immediately preceding code flag is output in steps S493 and S494 in FIG. When the immediately preceding code flag is on (when 1 channel bit of the immediately preceding code word string is “1”), in step S688, the channel bit string converting unit 55 determines whether the immediately preceding code flag is included in the code string converted in step S683. The confirmed codeword “$ 0 $” is set to “000”. In step S689, the channel bit string converting unit 55 outputs the code string “000 010 000 000 101”.

  In step S684, when it is determined that the immediately preceding code flag is not on (off) (when one channel bit of the immediately preceding code word string is “0”), in step S685, the channel bit string converting unit 55 It is determined whether the minimum run continuous restriction total flag (1) is on. This minimum run continuation limit comprehensive flag (1) is output in steps S523 and S524 of FIG. When the minimum run continuation restriction total flag (1) is on (when the 3 channel bits of the immediately preceding codeword string are “010”), as in the case where the immediately preceding code flag is on in step S684, Steps S688 and S689 are executed.

  On the other hand, when it is determined that the minimum run continuation restriction total flag (1) is not on (is off) (when the three channel bits of the immediately preceding codeword string are not “010”), in step S686 The channel bit string conversion unit 55 converts the indeterminate code word “$ 0 $” converted in step S683 into “101”. In step S687, the channel bit string converting unit 55 outputs the code string “101 010 000 000 101”.

  When it is determined in step S681 that the minimum run continuation restriction pattern detection flag 15 is not on (is off) (when the code string is not “001 010 101 010 101”), the channel bit string conversion unit 55 in step S690 Then, it is determined whether the minimum run continuous restriction pattern detection flag 12 is on. This detection flag is output in steps S606 and S607 in FIG. When the minimum run continuation restriction pattern detection flag 12 is on (when the code string is “101 010 101” and the next three channel bits are “010”), the channel bit string conversion unit in step S691 55 converts the code string “101 010 101” into a code string “001 000 000”. In step S692, the channel bit string converting unit 55 outputs the code string “001 000 000” converted in step S691.

  When it is determined in step S690 that the minimum run continuation limited pattern detection flag 12 is not on (is off) (the code string is not “101 010 101”, or even so, the next three channel bits Is not “010”), in step S693, the channel bit string conversion unit 55 determines whether or not the specific rule conversion pattern detection flag is on. This flag is output in steps S642 and S643 in FIG. If it is determined in step S693 that the specific rule conversion pattern detection flag is on (if the code string is “010 101 010 101”), in step S694, whether the minimum run continuation restriction total flag (2) is on. Determine. This flag is generated by the comprehensive detection unit 57 in the processing of steps S526 and S527 of FIG. When the minimum run continuation restriction total flag (2) is on (when the immediately preceding code is “1”), in step S695, the channel bit string conversion unit 55 further checks whether the prediction flag (C4) is on. judge. This flag is output in steps S587 and S588 in FIG.

  When the specific rule conversion pattern detection flag is on and the minimum run continuation restriction comprehensive flag (2) is on, the even-oddity preservation violation pattern (01110111) that constitutes the conversion pattern of the specific rule is converted. It means that there is a possibility. If the prediction flag (C4) is not on (is off), the code string is “xxx 101 010 101”, and the next three channel bits are not “010”. Is a code obtained by converting (01110111), which is an even-oddity preservation violation pattern. Therefore, in step S696, the channel bit string converting unit 55 converts the code string “010 101 010 101” into the code string “010 000 000 101”. In step S697, the channel bit string converting unit 55 outputs the code string “010 000 000 101” converted in step S696.

  When it is determined in step S693 that the specific rule conversion pattern detection flag is not on (is off) (when the code string is not “010 101 010 101”), in step S698, the channel bit string conversion unit 55 It is determined whether three channel bits (“* 0 *”) including an indeterminate bit have been received. This channel bit “* 0 *” is output by the selector 73 in step S484 of FIG. 24, and is selected and output by the conversion pattern determination unit 52 in step S559 of FIG. If it is determined in step S698 that the three-channel bit “* 0 *” including the uncertain bit has been received, the channel bit string conversion unit 55 executes the three-channel bit selection process for determining the uncertain bit in step S699.

  Details of the 3-channel bit selection process for determining the indeterminate bit are shown in FIG. That is, in step S721, the channel bit string converter 55 determines whether the immediately preceding code flag is on. The immediately preceding code flag is supplied from the immediately preceding code detection unit 56 based on the processing of steps S493 and S494 in FIG. When the immediately preceding code flag is on (when 1 channel bit of the immediately preceding codeword string is “1”), in step S772, the channel bit string converting unit 55 outputs 3 channel bits “000”. On the other hand, when the immediately preceding code flag is not on (is off) (when 1 channel bit of the immediately preceding code word string is “0”), in step S723, the channel bit string converting unit 55 determines that the channel bit “ 101 ”is output.

  Returning to FIG. 31, when it is determined in step S682 that the prediction flag (C7) is on (the minimum run continuous restriction pattern detection flag 15 is on and the code string is “xxx xxx 101 010 101”, Further, when the next channel bit is “010”), when it is determined in step S694 that the minimum run continuation limited total flag (2) is off (the specific rule conversion pattern detection flag is on, and the immediately preceding When the code is not “1”, or when it is determined in step S695 that the prediction flag (C4) is on (the specific rule conversion pattern detection flag is on, the immediately preceding code is “1”, and In the case where the code string is “xxx 101 010 101” and the next three channel bits are “010”), it is determined in step S698 that the three channel bits “* 0 *” including the indeterminate bit have not been received. Step S700 The channel bit string converter 55 outputs the input channel bit string as it is. That is, in this case, the conversion pattern determined by the conversion pattern determination unit 52 is output as it is as a code string.

  In the modulation device 1 of FIG. 1, the DSV control bit decision insertion unit 21 determines and adds the optimum one of the DSV control bits, 1 or 0. However, the data string with 0 added and 1 are added. It is also possible to prepare both data strings, process each, and select one of them at the final stage. FIG. 33 shows an embodiment of the modulation device in this case.

  In the encoding device 11 of the modulation device 1 in FIG. 33, a DSV control bit insertion unit 201 is arranged instead of the DSV control bit determination insertion unit 21. A DSV control unit 202 is inserted after the NRZI conversion unit 24 (before the recording unit 12). Other configurations are the same as those shown in FIG.

  That is, in the modulation device 1 of FIG. 33, the DSV control bit insertion unit 201 uses “0” as the DSV control bit as the data sequence (FIG. 34B) in which the DSV control bit is inserted with respect to the input data sequence (FIG. 34A). "Is inserted (FIG. 34B0) and" 1 "is inserted (FIG. 34B1). Then, each is supplied to the modulation unit 22 and converted into a channel bit string (FIG. 34C0, C1). The synchronization pattern insertion unit 23 inserts a synchronization pattern into each of the two series of channel bit strings input from the modulation unit 22 and outputs two series of channel bit strings. As described above, when the synchronization pattern is not inserted, the even-oddity preservation violation pattern is not used (FIG. 35A), but the data matches the data pattern (01110111), and the code immediately before is “1”. If the code immediately after is not “010”, the even-odd preservation violation pattern is used immediately after the synchronization pattern (Sync) of the two series of channel bit strings (FIG. 34C0, C1, FIG. 35B). The NRZI conversion unit 24 converts the two series of channel bit strings into NRZIs and outputs them to the DSV control unit 202.

  The DSV control unit 202 selects the most suitable one of the two series of channel bit strings (the one in which the DSV is close to 0) for each span (DSV section). The DSV control unit 202 calculates the DSV value of the currently selected DSV value (calculated after NRZI conversion of Cbit_1) (if the selected one is the one inserted with 0) 34C0 is calculated after NRZI is calculated)) If one is inserted, the section DSV value (calculated after NRZI of FIG. 34C1)) is added, and this is used as a new integrated DSV. Then, the next DSV section is selected using this new integrated DSV. The recording unit 12 records the recording code string finally selected by the DSV control unit 202 on the recording medium 13.

  The indeterminate code $, * may be determined using not only the immediately preceding code but also the immediately following code in order to satisfy a desired condition for the table.

For example, when the modulation table is configured as shown in Table 9 below, the modulation table is shown in Table 10 in order to enable a DSV control and insert a predetermined pattern at an arbitrary position. It can be configured as shown.
<Table 9>
1,7PP-rmtr5_code.rev.2 RLL (1,7; 2,3; 5)
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

i = 3 110111 001 000 000 (next010)
i = 5 1001110111 $ 0 $ 010 000 000 101
i = 6 100111011101 001 (no-change)

if xx1 then * 0 * = 000
xx0 then * 0 * = 101
if x10 or x01 then $ 0 $ = 000
x00 $ 0 $ = 101
-----------------------------
Sync & Termination
# 01 010 000 000 010 000 000 010 (24 cbits)
# = 0 not terminate case
# = 1 terminate case

Termination table
Data pattern Code pattern
00 000
0000 010 100
-----------------------------

<Table 10>
1,7PP-rmtr5_code.rev.21 RLL (1,7; 2,3; 5)
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

i = 3 110111 001 000 000 (next010)
i = 4 01110111 (not01) (pre1) 010 000 000 101
i = 5 1001110111 $ 0 $ 010 000 000 101
i = 6 100111011101 001 (no-change)

If xx1 then * 0 * = 000
xx0 then * 0 * = 101
If x10 or x01 then $ 0 $ = 000
x00 then $ 0 $ = 101
-----------------------------
Sync & Termination
# 01 010 000 000 010 000 000 010 yyy yyy (30 cbits = SY_24 cbits + ID_6 cbits)
# = 0 not terminate case
# = 1 terminate case

Termination table
Data pattern Code pattern
00 000
0000 010 100
-----------------------------

In the embodiment shown in Table 10, the even-oddity preservation violation pattern is used in the following table of constraint length i = 4.
i = 4 01110111 (not01) (pre1) 010 000 000 101

Table 10 also shows
Data pattern Code pattern
01110111 (not01) (pre1) 010 000 000 101
Part of
Data pattern Code pattern
01110111 (pre1) 010 000 000 101 (not010)
The conversion rule may be replaced with the configuration shown in Table 11.

<Table 11>
1,7PP-rmtr5_code.rev.22 RLL (1,7; 2,3; 5)
Data pattern Code pattern i = 1 11 * 0 *
10 001
01 010

i = 2 0011 010 100
0010 010 000
0001 000 100

i = 3 000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000

i = 4 00001000 000 100 100 100
00000000 010 100 100 100

i = 3 110111 001 000 000 (next010)
i = 4 01110111 (pre1) 010 000 000 101 (not010)
i = 5 1001110111 $ 0 $ 010 000 000 101
i = 6 100111011101 001 (no-change)

If xx1 then * 0 * = 000
xx0 then * 0 * = 101
If x10 or x01 then $ 0 $ = 000
x00 then $ 0 $ = 101
-----------------------------
Sync & Termination
# 01 010 000 000 010 000 000 010 yyy yyy (30 cbits = SY_24 cbits + ID_6 cbits)
# = 0 not terminate case
# = 1 terminate case

Termination table
Data pattern Code pattern
00 000
0000 010 100
-----------------------------

  In both Table 10 and Table 11, the generation part of the specific rule conversion pattern in which DSV control cannot be performed is limited to just after the synchronization signal, so the performance of DSV control is also equivalent.

  Further, for the 27PP code table shown in the following Table 12, the table shown in Table 13 can be considered.

<Table 12>
(d, k; m, n) = (2,7; 1,2)
Data pattern Code pattern
10 10 00
01 01 00
001 00 10 00
000 10 01 00
111 00 01 00
1101 00 00 10 00
1100 00 10 01 00
00000 00 00 10 01 00

The minimum run d = 2, that is, the continuation of 3T is limited to a maximum of 4 times by the replacement code of “00000”.

<Table 13>
(d, k; m, n) = (2,7or8; 1,2)
Data pattern Code pattern
10 10 00
01 01 00
001 00 10 00
000 10 01 00
111 00 01 00
1101 00 00 10 00
SY + 1100 00 00 01 00
1100 00 10 01 00
00000 00 00 10 01 00

Since the data pattern (1100) is a basic table, it can occur anywhere in the data string. Therefore, as shown in Table 13, as “SY + 1100”, a pattern that breaks the even-oddity rule can be applied only immediately after the synchronization pattern.
By doing in this way, it can implement | achieve similarly by the modulation apparatus based on this invention.

  Table 13 gives a new rule, but there is no improvement in characteristics compared to Table 12, but although the appearance position is limited to just after the synchronization pattern, the appearance frequency when the minimum run continues can be reduced, An improvement in reproduction signal quality with respect to a high linear density can be expected.

  And if some degradation is acceptable for the performance of the DSV control, for example, in Table 4, only the part of the constraint length i = 4 is configured so that the even-oddity is opposite to the other part, It is also possible to use a table in which the rule of evenness is partially different from other parts.

  In addition, in all patterns of each table, the number of data patterns “1” and the number of code patterns “1” divided by 2 can be selected so that the remainders do not coincide with each other. . However, in that case, it is necessary to do so uniformly for all patterns.

The 1,7PP code is provided with a replacement pattern that limits the number of repetitions of the minimum run length in the modulation table of minimum run d = 1, maximum run k = 7, and conversion rate (m: n) = (2: 3). Because
(1) The tolerance for recording / reproduction at high linear density and tangential tilt is improved.
(2) The portion with a low signal level is reduced, the accuracy of waveform processing such as AGC (Auto Gain Control) and PLL (Phase-Locked Loop) is improved, and the overall characteristics can be enhanced.
(3) Compared with the prior art, the path memory length for Viterbi decoding or the like can be designed to be short, and the circuit scale can be reduced.

Also, at the position where the DSV control bit is inserted, which is the remainder when dividing the number of data strings “1” constituting the conversion pattern of the modulation table and the number of codeword strings “1” by 2? Also matched with 1 or 0,
(4) Redundant bits for DSV control can be reduced.
(5) In the minimum run d = 1 and (m, n) = (2,3), DSV control can be performed with 1.5 codewords.
(6) The redundancy is low and the minimum run and the maximum run can be protected. Furthermore, the table in Table 4 reduces the error propagation at the time of data recording / reproduction because the number of continuous runs for the minimum run is reduced from 6 to 5 times compared to the 1,7PP code in Table 2. it can.

  As described above, as a data reproduction error pattern, there is a case in which errors from the first edge to the last edge of consecutive minimum marks are erroneously shifted. That is, the generated bit error length propagates from the beginning to the end of the continuous section of the minimum run. Therefore, the problem that the error propagation becomes long appears. However, by limiting the continuous minimum run to five times, the occurrence of such errors can be reduced, and more stable data recording and reproduction can be realized.

  FIG. 36 is a block diagram showing an example of the configuration of a personal computer that executes the above-described series of processing by a program. A CPU (Central Processing Unit) 321 executes various processes according to a program stored in a ROM (Read Only Memory) 322 or a storage unit 328. A RAM (Random Access Memory) 323 appropriately stores programs executed by the CPU 321 and data. The CPU 321, ROM 322, and RAM 323 are connected to each other via a bus 324.

  An input / output interface 325 is also connected to the CPU 321 via the bus 324. Connected to the input / output interface 325 are an input unit 326 made up of a keyboard, mouse, microphone, and the like, and an output unit 327 made up of a display, speakers, and the like. The CPU 321 executes various processes in response to commands input from the input unit 326. Then, the CPU 321 outputs the processing result to the output unit 327.

  The storage unit 328 connected to the input / output interface 325 includes, for example, a hard disk, and stores programs executed by the CPU 321 and various data. The communication unit 329 communicates with an external device via a network such as the Internet or a local area network. Further, the program may be acquired via the communication unit 329 and stored in the storage unit 328.

  The drive 330 connected to the input / output interface 325 drives a removable medium 331 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives the program or data recorded therein. Get etc. The acquired program and data are transferred to and stored in the storage unit 328 as necessary.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, the program is installed in a general-purpose personal computer from the program storage medium.

  As shown in FIG. 36, a program storage medium that stores a program that is installed in a computer and can be executed by the computer is a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (including Digital Versatile Disc)), magneto-optical disk (including MD (Mini-Disc) (registered trademark)), or removable media 331, which is a package media composed of semiconductor memory, or a program is temporarily stored A ROM 322 that is stored in a permanent or permanent manner, and a hard disk that constitutes the storage unit 328. The program is stored in the program storage medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 329 that is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the program storage medium is not limited to the processing performed in time series according to the described order, but is not necessarily performed in time series. Or the process performed separately is also included.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the modulation apparatus of one embodiment of this invention. It is a figure explaining a data format. It is a block diagram which shows the detailed structure of the encoding apparatus of FIG. It is a block diagram which shows the more detailed structure of the encoding apparatus of FIG. It is a figure explaining the function of an immediately preceding code | symbol detection part. It is a figure explaining the function of a comprehensive detection part. It is a figure explaining the function of an indeterminate bit decision part. It is a flowchart explaining a recording process. It is a flowchart explaining the conversion pattern detection process of step S3 of FIG. 10 is a flowchart for explaining 2-data / 3-channel bit processing in step S63 of FIG. It is a flowchart explaining the immediately preceding code detection process. It is a flowchart explaining a minimum run continuation restriction comprehensive detection process. It is a flowchart explaining the conversion pattern determination process of step S4 of FIG. It is a flowchart explaining the prediction process of step S5 of FIG. FIG. 9 is a flowchart for explaining a minimum run continuation restriction pattern detection process in step S6 of FIG. 8. It is a flowchart explaining the specific rule conversion pattern detection process of step S7 of FIG. It is a flowchart explaining the channel bit string conversion process of step S8 of FIG. It is a figure explaining the process of a conversion pattern process part. It is a figure explaining the process of a minimum run continuation restriction pattern process part and a specific rule conversion pattern detection part. It is a block diagram which shows the structure of other embodiment of the modulation apparatus of this invention. FIG. 21 is a block diagram showing a more detailed configuration of the modulation device in FIG. FIG. 22 is a flowchart for describing recording processing of the modulation device in FIG. 21. FIG. FIG. 23 is a flowchart for describing conversion pattern detection processing in step S403 of FIG. FIG. 24 is a flowchart for describing 2-data / 3-channel bit processing in step S463 of FIG. 23. FIG. It is a flowchart explaining the immediately preceding code detection process. It is a flowchart explaining a minimum run continuation restriction comprehensive detection process. FIG. 23 is a flowchart for describing conversion pattern determination processing in step S404 of FIG. FIG. 23 is a flowchart for describing prediction processing in step S405 of FIG. FIG. 23 is a flowchart for describing a minimum run continuation restriction pattern detection process in step S406 of FIG. FIG. 23 is a flowchart for describing specific rule conversion pattern detection processing in step S407 of FIG. 23 is a flowchart for describing channel bit string conversion processing in step S408 of FIG. FIG. 32 is a flowchart for describing 3-channel bit selection processing for determining indeterminate bits in step S699 of FIG. 31. It is a block diagram which shows the structure of the modulation apparatus of further another embodiment of this invention. FIG. 34 is a diagram illustrating a data format of the modulation device in FIG. FIG. 34 is a diagram illustrating a data format when there is no synchronization pattern of the modulation device in FIG. It is a block diagram which shows the structure of a personal computer.

Explanation of symbols

  1 Modulator, 11 Encoder, 21 DSV control bit decision insertion unit, 22 Modulation unit, 23 Synchronization pattern insertion unit, 24 NRZI conversion unit, 41 Adder, 51 Conversion pattern processing unit, 52 Conversion pattern determination unit, 53 Identification Rule conversion pattern detection unit, 54 Minimum run continuation restriction pattern processing unit, 55 Channel bit string conversion unit, 56 Immediate code detection unit, 57 Total detection unit, 71 Conversion pattern detection unit, 72A to 72D conversion table, 73 Selector, 74 Undetermined Bit decision unit, 111 Minimum run continuous limit pattern detection prediction unit, 112 Minimum run continuous limit pattern detection unit

Claims (8)

Data having a basic data length of m bits is converted to a variable length code (d, k; m, n) having a minimum run of d (d> 0), a maximum run of k, and a basic codeword length of n bits. In the modulation device,
First conversion means for converting input data into a code string composed of a code pattern so as to comply with the RLL rule, in accordance with a conversion table that describes the correspondence between the data pattern and the code pattern;
Determination means for determining from the code string converted to the code pattern that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern When,
When it is determined that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into the corresponding even-oddity preservation violation code pattern, the even-odd preservation of the input data A modulator comprising: a second conversion unit configured to convert an even-oddity preservation violation individual conversion code pattern generated by individually converting a portion that matches the violation data pattern into the even-odd preservation violation code pattern. The determination means includes a code string in which the code string converted into the code pattern includes the even-oddity preservation violation individual conversion code pattern, and a code immediately before and after the even-oddity preservation violation individual conversion code pattern is predetermined. 2. The modulation device according to claim 1, wherein the input data is determined to have the condition. The modulation device according to claim 1, further comprising synchronization pattern insertion means for inserting a synchronization pattern at a predetermined position of the input data. The modulation device according to claim 3, further comprising DSV control bit insertion means for inserting a DSV control bit into a DSV section including the synchronization pattern and the even-odd preservation violation code pattern so that DSV control is possible.   A recording medium on which a signal modulated by the modulation device according to claim 1 is recorded. Data having a basic data length of m bits is converted to a variable length code (d, k; m, n) having a minimum run of d (d> 0), a maximum run of k, and a basic codeword length of n bits. In the modulation method,
A first conversion step of converting input data into a code string made up of a code pattern so as to comply with the RLL rule, according to a conversion table describing the correspondence between the data pattern and the code pattern;
A determination step of determining from the code string converted to the code pattern that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern When,
When it is determined that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into the corresponding even-oddity preservation violation code pattern, the even-odd preservation of the input data A modulation method comprising: a second conversion step of converting an even-oddity preservation violation individual conversion code pattern generated by individually converting portions that match the violation data pattern into the even-odd preservation violation code pattern. Data having a basic data length of m bits is converted to a variable length code (d, k; m, n) having a minimum run of d (d> 0), a maximum run of k, and a basic codeword length of n bits. In the program
A first conversion step of converting input data into a code string made up of a code pattern so as to comply with the RLL rule, according to a conversion table describing the correspondence between the data pattern and the code pattern;
A determination step of determining from the code string converted to the code pattern that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into a corresponding even-oddity preservation violation code pattern When,
When it is determined that the input data has a condition for converting a portion that matches the even-oddity preservation violation data pattern into the corresponding even-oddity preservation violation code pattern, the even-odd preservation of the input data A program that causes a computer to execute a second conversion step of converting an even-oddity preservation violation individual conversion code pattern generated by individually converting portions that match the violation data pattern into the even-odd preservation violation code pattern.   A recording medium on which the program according to claim 7 is recorded.

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