JP4207073B2 - Modulation apparatus and method, recording medium, and demodulation apparatus and method - Google Patents

Description

  The present invention relates to a modulation apparatus and method, a recording medium, and a demodulation apparatus and method, and more particularly to a modulation apparatus and method for modulating and reproducing data so as to be suitable for data transmission and recording on a recording medium, a recording medium, and a demodulation apparatus. And methods.

  When data is transmitted through a predetermined transmission path or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated so as to be suitable for transmission or recording. A block code is known as one of such modulation methods. In this block code, a data string is divided into units of m × i bits (hereinafter simply referred to as data words), and the data words are converted into code words of n × i bits according to an appropriate code rule. is there. This code becomes a fixed length code when i is 1, and when a plurality of i can be selected, that is, when a predetermined i in the range of 1 to imax (maximum i) is selected and converted, Variable length code. The block-coded code is represented as a variable length code (d, k; m, n; r).

  Here, i is referred to as a constraint length, and imax is referred to as a maximum constraint length r. The minimum run d indicates the minimum number of consecutive “0” s that fall between consecutive “1” s in the code sequence, and the maximum run k is between consecutive “1” s in the code sequence. The maximum number of consecutive “0” s entered is shown.

  For compact discs, minidiscs, etc., NRZI (Non Return to Zero Inverted) modulation is applied to the variable length code obtained as described above, with “1” being inverted and “0” being non-inverted. A modulated variable length code (hereinafter, an NRZI modulated variable length code is referred to as a level code) is recorded.

  Also, when the level code is inverted from “1” to “0” or from “0” to “1”, that is, when an edge is reached, “1” is set, and when inverse NRZI modulation is performed, the original EFM The same code string as the code or the RLL (1-7) code can be obtained. This inverse NRZI code string is referred to as an edge code.

  When the minimum inversion interval of the level code is Tmin and the maximum inversion interval is Tmax, in order to perform high-density recording in the linear velocity direction, the minimum inversion interval Tmin is longer, that is, the minimum run d is larger. Further, from the viewpoint of clock regeneration, it is desirable that the maximum inversion interval Tmax is shorter, that is, the maximum run k is smaller, and various modulation methods have been proposed.

  For example, there is RLL (1-7) as a modulation method used for recording on a magnetic disk or a magneto-optical disk. The parameter of this modulation scheme is (1,7; 2,3; 2), and the minimum inversion interval Tmin obtained by (d + 1) T is 2T from (1 + 1) T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin is 1.33 Tdata from (m / n) × Tmin = (2/3) × 2. Further, the maximum inversion interval Tmax obtained by (k + 1) T is 8 (= 7 + 1) T (= 2/3 × 8Tdata = 5.33Tdata). Further, the detection window width Tw obtained by (m / n) T is 0.67 (= 2/3) Tdata.

  The RLL (1-7) code conversion table is, for example, a table as shown in Table 1.

<Table 1>
RLL (1,7; 2,3; 2)
Data code i = 1 1 1 1 00x
10 010
01 10x
i = 2 0011 000 00x
0010 000 010
0001 100 00x
0000 100 010
Here, the symbol x in the conversion table gives “1” when the next channel bit is “0”, or “0” when the next channel bit is “1”. The maximum constraint length r is 2.

  By the way, the channel bit string that has been modulated by RLL (1-7) has the highest occurrence frequency of 2T, which is Tmin, followed by 3T and 4T. If edge information such as 2T or 3T is generated frequently at an early cycle, it is advantageous for clock reproduction. However, if 2T continues, the recorded waveform is likely to be distorted (2T waveform output is small and defocused). And is susceptible to tangential tilt). Further, continuous recording of a minimum mark at a higher linear density is likely to be affected by disturbances such as noise and is likely to cause data reproduction errors.

  Therefore, the present applicant has proposed, as Japanese Patent Application No. Hei 9-133379, that Tmin is limited to continue for a predetermined number of times or more, but the conversion table of RML (1-7) as its code is, for example, It is a table shown in Table 2.

<Table 2>
RML (1,7; 2,3; 3)
Data code i = 1 1 1 1 00x
10 010
01 10x
i = 2 0011 000 00x
0010 000 010
0001 100 00x
0000 100 010
i = 3 100110 100 000 010
Here, the symbol x in the conversion table gives “1” when the next channel bit is “0”, and gives “0” when the next channel bit is “1”. The maximum constraint length r is 3.

  The conversion using Table 2 refers to the following 4 data when the data string becomes “10”, and when the total of 6 data strings becomes “100110”, the code that limits the repetition of the minimum run d "100 000 010" is given. The minimum run d of the code obtained by this conversion is repeated up to 5 times.

  By the way, at the time of recording on a recording medium and data transmission, encoding modulation suitable for each medium (transmission) is performed. When a DC component is included in these modulation codes, Variations in various error signals such as tracking errors in servo control are likely to occur, or jitter is likely to occur. Therefore, it is better not to include a DC component as much as possible.

  Here, the variable length minimum run d = 1, the conversion rate m = 2, and the conversion rate m = 2 and n = 3 RLL code is not subjected to DSV (Digital Sum Value) control. In DSV control, a channel bit string is converted to NRZI (ie, level-encoded), and when the bit string (data symbol) is added with a code where “1” is +1 and “0” is −1, the sum ( This means control to reduce the absolute value of DSV). DSV is a measure of the DC component of the code string, and decreasing the absolute value of DSV suppresses the DC component of the code string.

  In general, 2 × (d + 1) bits are used as DSV control bits for performing this DSV control. For example, when d = 1, 2 × (1 + 1) = 4 bits. At this time, complete DSV control is performed at an arbitrary interval, which can keep the minimum run and the maximum run, and can also perform inversion or non-inversion.

  However, the DSV control bit is basically a redundant bit. Therefore, from the viewpoint of code conversion efficiency, it is better to have as few DSV control bits as possible.

  Therefore, even when the DSV control bit is 1 × (d + 1), that is, when d = 1, 1 × (1 + 1) = 2 bits, complete DSV control that can be inverted / non-inverted at an arbitrary interval is performed. Is called. However, although the minimum run is protected, the maximum run becomes large and becomes (k + 2). The minimum run must be kept as a recording code, but the maximum run is not limited to this. In some cases, there is a format that uses a pattern that breaks the maximum run as a sync signal (the EFM plus of DVD is the maximum run 11T, but 14T is allowed for format reasons).

  Then, there is a 17PP (Parity Preserve) code as a table capable of performing DSV control more efficiently than these while maintaining the basic performance of the RML code of Table 2. The 17PP code is a modulation code having run restrictions d = 1 and k = 7, further restricting the continuation of the minimum run, and giving rules to the corresponding elements of the data word and the code word.

  The conversion table of the 17PP code proposed by the present applicant in Japanese Patent Application No. 10-15280 is, for example, as follows.

<Table 3>
17PP-32 (1,7; 2,3; 4)
Data sign
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
"110111 001 000 000 (next010)
00001000 000 100 100 100
00000000 010 100 100 100
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
-----------------------------
"110111 001 000 000 (next010):
When next channel bits are '010',
convert '11 01 11 'to' 001 000 000 'after
using main table and termination table.
-----------------------------

  Table 3 shows that the minimum run d = 1 and the maximum run k = 7, and the elements in the conversion table have uncertain codes. For the indeterminate code, when 2 bits of the data string to be converted is (11), “000” or “101” is selected depending on the code word string immediately before that. When one channel bit of the immediately preceding code word string is “1”, the conversion of (11) becomes “000” in order to keep the minimum run. Further, when one channel bit of the immediately preceding code word string is “0”, it is set to “101” so that the maximum run can be protected.

  The conversion table in Table 3 is a variable length structure table. That is, the conversion code in the constraint length i = 1 is composed of three less than the required number of four (2 ^ (m x i) = 2 ^ (2 x 1) = 4). That is, when data strings are converted, there are data strings that cannot be converted only with the constraint length i = 1. Eventually, in order to correspond to all data strings in the conversion table of Table 3, that is, to hold as a conversion table, a constraint length i = 3 is required.

  Further, the conversion table of Table 3 has a replacement code that limits the continuation of the minimum run in the conversion table. For example, the data string (110111) refers to the codeword string that follows, and when it is “010”, it is replaced with “001 000 000”. If the subsequent code word string is other than “010”, it is converted to “* 0 * 010 * 0 *”. As a result, the code word string after data conversion is limited in the minimum run, and the minimum run is repeated up to six times.

  Furthermore, the conversion table in Table 3 shows that the number of “1” in the element of the data string and the number of “1” in the element of the codeword string to be converted, which is the remainder when divided by 2 Also have a conversion rule that is the same at 1 or 0. For example, the element (000001) of the data string corresponds to the code word string “010 100 100”, but the number of “1” is one for the data string and three for the corresponding code word string, respectively. In both cases, the remainder after dividing by 2 is equal to 1. Similarly, the element (000000) of the data string corresponds to a code word string of “010 100 000”, but the number of “1” s is 0 for each data string and 2 for the corresponding code word string. Both of them are the same, and the remainder when divided by 2 matches with 0.

  The conversion table in Table 3 has a maximum constraint length r = 4. The conversion code of i = 4 has a replacement code for realizing the maximum run k = 7.

  The data string is modulated according to the conversion table of Table 3, and the modulated channel bit string can be DSV controlled at a predetermined interval as before, but the relationship between the data string and the codeword string to be converted is Utilizing this, DSV control can be performed more efficiently.

  That is, in the conversion table, the number of “1” in the element of the data string and the number of “1” in the element of the codeword string to be converted are divided by 2, and the remainder is 1 Alternatively, when the conversion rule is the same as 0, inserting a DSV control bit of “1” indicating “inverted” or “0” indicating “non-inverted” in the channel bit is not included in the data bit string. If “inverted”, “1” is read, and if “non-inverted”, it is equivalent to inserting a DSV control bit of “0”.

For example, in Table 3, when 3 bits for data conversion are followed by “001” and the DSV control bit is included after that, the data conversion is (001-x) (x is 1 bit, 0 or 1). It becomes. Here, if “0” is given to x, the conversion table of Table 3 is
Data sign
0010 010 000
And if you give “1”,
Data sign
0011 010 100
It becomes. When codeword strings are level-coded with NRZI, these are data code level code
0010 010 000 011111
0011 010 100 011000
Thus, the last 3 bits of the level code string are mutually inverted. That is, by selecting “1” and “0” of the DSV control bit x, DSV control can be performed even in the data string.

  Considering the redundancy by DSV control, performing 1-bit DSV control within a data string is expressed as a channel bit string, since conversion rate m = 2 and n = 3 in Table 3, 1.5 channels This is equivalent to performing DSV control with bits. Here, in order to perform DSV control in the RLL (1-7) table as shown in Table 1, for example, DSV control is performed in the channel bit string. In order to keep the minimum run, as described above, at least two channels are used. Bits are required and the redundancy is greater.

  The conversion table shown in Table 3 can perform DSV control within the data string, so that efficient DSV control can be performed and the repetition of the minimum run is limited, so that a code suitable for high linear density recording and reproduction is generated. .

  In order to actually use the conversion table of Table 3, it is necessary to provide a synchronization signal for identifying the head of data, for example, when reproducing the recorded code string. It is desirable that the synchronization signal has a pattern that can be reliably distinguished from others. In addition, when it is necessary to provide a plurality of synchronization signals, it is desirable that the synchronization signals have a pattern that can identify the synchronization signals as reliably as possible.

  As described above, when a recording medium such as a magnetic disk, a magneto-optical disk, or an optical disk is increased in density, a code having a minimum run d = 1 is selected as a modulation code, and distortion during recording / reproduction is further reduced. Thus, when the PP17 code is selected as a code suitable for higher-density recording / reproduction, the synchronization signal corresponding to this is required.

  The present invention has been made in view of such a situation, and an object thereof is to provide a more reliable sync signal pattern.

A modulation device according to a first aspect of the present invention is a modulation device that modulates data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits, The code sequence includes a synchronization signal adding means for adding a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run, and the synchronization signal is a pattern other than the pattern that breaks the maximum run, For DSV (Digital Sum Value) control, one uncertain bit that can be replaced with “0” and “1” is included, and even if the synchronization signal includes the minimum run, it is included in the synchronization signal. The minimum run to be performed is characterized in that the minimum run in all the code strings satisfies the restriction that the repetition is limited to a predetermined number of times.

  The minimum run in all the code strings including the synchronization signal can satisfy the restriction that the repetition is limited to a predetermined number of times.

  The synchronization signal may have two or more types of mutually distinguishable patterns.

A modulation method according to a first aspect of the present invention is a modulation method for modulating data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits, The code sequence includes a synchronization signal adding step of adding a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run, and the synchronization signal is a pattern other than the pattern that breaks the maximum run, For the DSV control, even if there is one uncertain bit that can be replaced with “0” and “1”, and the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal is It is characterized by satisfying the restriction that the repetition is limited to a predetermined number together with the minimum run in all code strings .

  The minimum run in all the code strings including the synchronization signal can satisfy the restriction that the repetition is limited to a predetermined number of times.

The recording medium according to the second aspect of the present invention is produced by a modulation method that modulates data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits. A synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run is added to the code string, and the synchronization signal is used for DSV control in patterns other than the pattern that breaks the maximum run. Even when one uncertain bit that can replace “0” and “1” is included and the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal is the minimum in all code sequences. Along with the run, a code string having a data structure that satisfies the restriction that the repetition is limited to a predetermined number of times is recorded.

  The minimum run in all the code strings including the synchronization signal can satisfy the restriction that the repetition is limited to a predetermined number of times.

  The synchronization signal may have two or more types of mutually distinguishable patterns.

A demodulator according to a third aspect of the present invention is a demodulator that demodulates a code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits, From the code string, comprising a synchronization signal detection means for detecting a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run, the synchronization signal is a pattern other than the pattern that breaks the maximum run, For the DSV control, even if there is one uncertain bit that can be replaced with “0” and “1”, and the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal is It is characterized by satisfying the restriction that the repetition is limited to a predetermined number together with the minimum run in all code strings .

  The minimum run in all the code strings including the synchronization signal can satisfy the restriction that the repetition is limited to a predetermined number of times.

  The synchronization signal may have two or more types of mutually distinguishable patterns.

A demodulation method according to a third aspect of the present invention is a demodulation method for demodulating a code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits, A synchronization signal detecting step of detecting a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run from the code string, wherein the synchronization signal is a pattern other than the pattern that breaks the maximum run, For the DSV control, even if there is one uncertain bit that can be replaced with “0” and “1”, and the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal is It is characterized by satisfying the restriction that the repetition is limited to a predetermined number together with the minimum run in all code strings .

  The minimum run in all the code strings including the synchronization signal can satisfy the restriction that the repetition is limited to a predetermined number of times.

In the first aspect of the present invention, a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run is added to the code string, and the synchronization signal is a pattern other than the pattern that breaks the maximum run. In this pattern, even if there is one uncertain bit that can be replaced with “0” and “1” for DSV control, and the minimum run is included in the synchronization signal, it is included in the synchronization signal. The minimum run satisfies the restriction that the repetition is repeated a predetermined number of times together with the minimum run in all code strings .

In the second aspect of the present invention, a code string created by a modulation scheme that modulates data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits In addition, a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run is added, and the synchronization signal is “0” for DSV control in a pattern other than the pattern that breaks the maximum run. Even if there is one uncertain bit that can be replaced with “1” and the synchronization signal includes a minimum run, the minimum run included in the synchronization signal is the same as the minimum run in all code sequences. code string of a data structure to satisfy the limitations that repetition that is until a predetermined number of times is recorded.

In the third aspect of the present invention, a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run is detected from the code string, and the synchronization signal is a pattern other than the pattern that breaks the maximum run. In this pattern, even if there is one uncertain bit that can be replaced with “0” and “1” for DSV control, and the minimum run is included in the synchronization signal, it is included in the synchronization signal. The minimum run satisfies the restriction that the repetition is repeated a predetermined number of times together with the minimum run in all code strings .

  As described above, according to the first aspect of the present invention, a more reliable sync signal pattern can be provided.

  According to the second aspect of the present invention, a more reliable synchronization signal pattern can be provided.

  Also, according to the third aspect of the present invention, it is possible to detect the synchronization signal pattern more reliably.

  Embodiments of the present invention will be described below, but in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, in parentheses after each means, The features of the present invention will be described with the corresponding embodiment (however, an example) added. However, of course, this description does not mean that each means is limited to the description.

That is, the modulation device according to the first aspect of the present invention is a modulation device that modulates data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits. Synchronization code adding means (for example, the Sync bit inserting unit 14 in FIG. 1) for adding a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run to the code string. The signal has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run, and the minimum run is included in the synchronization signal. Even in this case, the minimum run included in the synchronization signal satisfies the restriction that the repetition is repeated a predetermined number of times together with the minimum run in all code sequences .

A demodulator according to a third aspect of the present invention is a demodulator that demodulates a code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits, Synchronization signal detection means (for example, the SYNC / SyncID identification unit 33 in FIG. 3) for detecting a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run from the code string is provided. Has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run, and the synchronization signal includes the minimum run However , the minimum run included in the synchronization signal satisfies the restriction that the repetition is repeated a predetermined number of times together with the minimum run in all code strings .

As shown in Table 4, the sync signal pattern in Table 3 is a pattern having the following characteristics.
(1) (Tmax + 1)-(Tmax + 1), that is, 9T-9T is given. Thereby, since the pattern which breaks the maximum run is continued twice, the detection capability can be increased.
(2) Before 9T-9T, 2T is given so that Tmax does not appear no matter what the data modulation sequence is. That is, a short run is sandwiched so that the 8T-9T-9T pattern does not appear in the combination with the immediately preceding data portion of the inserted synchronization signal. If there is 8T-9T-9T, the detection distance from the detection pattern 9T-9T becomes 1 in 8T-9T in the first half, and the detection capability is deteriorated and error is likely to occur. Therefore, 2T is inserted in advance to eliminate this. Although 3T and 4T can be given before 9T-9T, they are rather redundant. 2T is the most efficient.
(3) Two bits are arranged as connection bits before 2T-9T-9T. As a result, the synchronization signal can be inserted at an arbitrary position, and the data can be terminated at the insertion position.

<Table 4> 17PP.RML.32
-----------------------------
Sync & Termination
# 01 010 000 000 010 000 000 010 (23 + 1 channel bits)
# = 0 not terminate case
# = 1 terminate case
Termination table
00 000
0000 010 100
-----------------------------

  By the way, when the synchronization signal is inserted at an arbitrary position in the code word string (channel bit string) generated by the conversion table shown in Table 3, the code generated by the conversion table shown in Table 3 has a variable length structure. In addition, a termination table is provided to terminate at an arbitrary position, and is used as necessary.

In Table 3, when a sync signal is inserted at an arbitrary position, the sync signal pattern is first given a connection pattern to protect the minimum run d and the maximum run k in connection with the codeword string immediately before and after, A pattern for a synchronization signal is given during (the connection pattern can be considered as a part of the pattern for the synchronization signal). The given sync signal pattern is 24 bits, which is the number of bits divisible by 3, from the conversion rates m = 2 and n = 3 in Table 3, and specifically, the following pattern is used.
"# 01 010 000 000 010 000 000 010"
The leading “#” is a bit for connection and gives either 0 or 1. The second channel bit gives “0” to keep the minimum run. 2T is given by the 3rd and 4th channel bits. From the 5th channel bit, 9T where k = 8 is continuously given twice as a synchronization signal pattern. That is, eight “0” s are arranged between “1” and “1”. Continue this twice. The last channel bit “1” in the synchronization signal pattern determines the maximum run. Up to this point, there are 23 channel bits. Further, 1 bit “0” for connection is added at the end. As a result, the minimum run d = 1 can be maintained regardless of the following bits.

Here, the termination table and the sync signal pattern connection bit “#” will be described. As shown in Table 4, the termination table is
00 000
0000 010 100
It becomes. The termination table is required when there are fewer than four conversion codes in each of the constraint lengths r in which there are conversion codes that are not replacement codes for limiting the continuation of the minimum run. That is, in Table 3, since there are three conversion codes for the constraint length i = 1, a termination table is required. Further, since there are three conversion codes for the constraint length i = 2, a termination table is required. There are five conversion codes for the constraint length i = 3, one of which is a replacement code and four of which are conversion codes, and are terminated because they have the required number. Since all the conversion codes at the constraint length i = 4 are replacement codes, the termination need not be considered. Therefore, (00) with constraint length i = 1 and (0000) with i = 2 are given to the termination table.

  The connection bit “#” of the synchronization signal pattern is given to distinguish between the case where the termination table is used and the case where it is not used. That is, “#” of the first channel bit given as a synchronization signal gives “1” when the termination code is used, and gives “0” otherwise. By doing so, it is possible to definitely distinguish between the case where the termination table is used and the case where it is not used at the time of demodulation.

  Now, the sync signal pattern is given by (23 + 1) channel bits with higher detection capability. However, if more than two types of sync signals are required, it is difficult to realize the sync signal with (23 + 1) channel bits. is there.

  Therefore, in addition to the 24 channel bits, 6 bits are added to the rear, and the types of synchronization signals when a total of 30 channel bits are given are shown below.

  Two or more types of synchronization signal patterns in the conversion tables of Tables 3 and 4 are defined as shown in Table 5. The synchronization signal pattern is selected such that the minimum run is observed and the repetition of the minimum run is limited to 6 times as shown in Table 3. Further, the synchronization signal pattern is selected so that the maximum run does not occur other than the synchronization signal detection pattern. The method of connection with the data string is the same as in Table 4.

<Table 5>
17PP.RML.32
-----------------------------
30channel-bit Syncs
# 01 010 000 000 010 000 000 010 000 001
000 010
000 100
001 000
001 001
001 010
010 000
010 001
010 010
010 100
100 001
100 010
100 100
101 000
101 001
# = 0 not terminate case
# = 1 terminate case
Termination table
00 000
0000 010 100
-----------------------------

  As shown in Table 5, when 30 bits are given to the synchronization signal bits, 15 kinds of synchronization signal patterns can be obtained by choosing to follow the rules. From these, the sync signal pattern can be determined in each of the following cases.

  In other words, if one having a distance of 2 or more between the respective synchronization signal patterns is selected, the following seven patterns can be selected.

<Table 6>
17PP.RML.32
-----------------------------
30channel-bit Syncs
# 01 010 000 000 010 000 000 010 000 001
000 100
001 001
010 000
010 010
100 001
101 000
# = 0 not terminate case
# = 1 terminate case
Termination table
00 000
0000 010 100
-----------------------------

  That the distance is 2 or more means that when each sync signal pattern is detected (reproduced data is a level code), at least 2 locations in 30 channel bits of the sync signal are different. The synchronization signal pattern shown in Table 6 is selected so as to satisfy such a condition in the last 6 bits. Table 6 is effective when many types of synchronization signals are required.

  The following three types of sync signal patterns can be selected as DC-free sync signal patterns.

<Table 7>
17PP.RML.32
-----------------------------
30channel-bit Syncs
# 01 010 000 000 010 000 000 010 001 000
010 001
100 010
# = 0 not terminate case
# = 1 terminate case
Termination table
00 000
0000 010 100
-----------------------------

  DC free means that the DSV value of 30 channel bits of each synchronization signal pattern is zero. The synchronization signal patterns in Table 7 are DC-free, and the distance between the synchronization signal patterns is 2 or more.

  If the last bit of each sync signal pattern is selected to be a set in which 0 and 1 can be replaced, the following three sync signal patterns can be selected.

<Table 8>
17PP.RML.32
-----------------------------
30channel-bit Syncs
# 01 010 000 000 010 000 000 010 001 00x
010 00x
101 00x
x: 0 or 1
# = 0 not terminate case
# = 1 terminate case
Termination table
00 000
0000 010 100
-----------------------------

  The set of replaceable sync signal patterns can be subjected to DC control of the subsequent data conversion sequence by the last one channel bit, and efficient DSV control can be realized in the sync signal portion. The modulation device performs DSV control by selecting “1” and “0” of the last bit corresponding to the result of the DSV value of the following data string in the synchronization signal pattern of Table 8. The three types of sync signal patterns are determined without looking at the last 1 bit.

  An embodiment of a modulation device according to the present invention will be described with reference to the drawings. This embodiment is applied to a modulation device that converts a data string into the variable length codes (d, k; m, n; r) = (1, 7; 2, 3; 4) in Table 3. .

  FIG. 1 is a block diagram showing a configuration of an embodiment of a modulation apparatus that inserts synchronization signals at predetermined intervals. The DSV bit determination / insertion unit 11 first performs DSV control at an arbitrary interval from the data string, determines the DSV control bit “1” or “0”, inserts it at an arbitrary interval, and inserts the data string. Is supplied to the modulation unit 12 and the SYNC / SyncID determination unit 13. The modulation unit 12 modulates the data sequence in which the DSV control bits are inserted, and outputs the obtained code sequence to the Sync bit insertion unit 14. The SYNC / SyncID determination unit 13 determines the pattern of the synchronization signal (Sync) inserted into the data string at a predetermined interval, and supplies the result to the Sync bit insertion unit 14.

  The Sync bit insertion unit 14 inserts the synchronization signal determined by the SYNC / SyncID determination unit 13 into the code string input from the modulation unit 12 and supplies the synchronization signal to the NRZI conversion unit 15. The NRZI conversion unit 15 performs NRZI modulation on the code string input from the Sync bit insertion unit 14 to convert it into a recording waveform string, and outputs a recording waveform string. The timing management unit 16 generates a timing signal and supplies the timing signal to the DSV bit determination / insertion unit 11, the modulation unit 12, the SYNC / SyncID determination unit 13, the Sync bit insertion unit 14, and the NRZI conversion unit 15 to manage timing. .

When the SYNC / SyncID determination unit 13 uses the 30 code words that are the synchronization signal patterns of Table 3, the first 24 code words are
"X01 010 000 000 010 000 000 010"
Set to. “X” is determined depending on the immediately preceding conversion codeword string (which may include the DSV control bit) divided by the insertion of the synchronization signal, and when the termination table is used for the immediately preceding data conversion,
"X" = "1"
And if not,
"X" = "0"
Is set. That is, “x” is determined so as to keep the minimum run and the maximum run when the synchronization signal is inserted.

  The Sync bit insertion unit 14 inserts the synchronization signal determined by the SYNC / SyncID determination unit 13 as described above into the code string. After the synchronization signal is inserted, the process starts from the beginning of the conversion table.

  Next, the operation of this embodiment will be described.

  The data string is subjected to DSV control at a predetermined interval, and a synchronization signal is inserted at a predetermined interval. The DSV bit determination / insertion unit 11 calculates the integrated DSV up to a certain position and the next DSV interval at a predetermined interval, and the DSV control bit (1) or (0 ) And insert it into the data string. Since the DSV value cannot be determined only by the data string, the DSV bit determination / insertion unit 11 generates a code word string from the data string using the conversion table, and obtains the DSV value based on this.

  The bit string in which the DSV value is inserted is modulated based on the conversion table by the modulation unit 12, and the result is sent to the SYNC bit insertion unit 14. The modulation unit 12 stores the interval of the synchronization signal, performs modulation up to the vicinity of the synchronization signal, and when the conversion cannot be performed with a normal conversion table, that is, when it is necessary to use the termination table shown in Table 4, the information is Output to the SyncID determination unit 13.

  Similarly, the SYNC / SyncID determination unit 13 stores the interval of the synchronization signal and determines the value of the first connection bit of the synchronization signal corresponding to the state immediately before the synchronization signal is inserted. When data conversion is performed using a normal conversion table, “0” is set in the first connection bit. In addition, when it is necessary to use a termination table that cannot be performed with a normal conversion table, the SYNC / SyncID determination unit 13 refers to the built-in termination table and sets “1” to the first connection bit of the synchronization signal. Set.

  Thus, the previous 24 bits of the SYNC bit are determined. In addition, the value of the SyncID bit of the synchronization signal is set in the subsequent 6 bits. As the SyncID bit, for example, as shown in Table 6, one of seven types of synchronization signal patterns, each having a distance 2 from each other, is set.

  As described above, the synchronization signal is determined, and the SYNC bit insertion unit 14 inserts the determined synchronization signal into the code string. When the synchronization signal is determined using the termination table built in the SYNC / SyncID determination unit 13, the synchronization signal including the value obtained from the termination table is inserted in the SYNC bit insertion unit 14.

  Finally, the NRZI conversion unit 15 performs the DSV control, and further converts the channel bit string into which the synchronization signal is inserted into a recording code.

  FIG. 2 is a block diagram showing a configuration of another embodiment of the modulation device. As described in the example of FIG. 1, it is necessary to perform modulation and NRZI conversion for DSV value calculation. Furthermore, since the SYNC part also performs DSV control, it is necessary to use NRZI. Thus, the modulation device can be configured in the order as shown in FIG.

  In the modulation device of FIG. 2, the control bit insertion unit 21 inserts a bit for performing DSV control in units of a predetermined number of bits and outputs the bit to the modulation unit 12. Since this bit number unit is also considered including the SYNC bit, the control bit insertion unit 21 does not necessarily need to give only one type of bit number (may give a plurality of types of bits). The modulation unit 12 converts the data string obtained from the control bit insertion unit 21 to create a channel bit string. When the modulation unit 12 cannot convert the data immediately before SYNC, a signal is output to the SYNC / SyncID insertion unit 22 so as to use the termination table.

  The SYNC / SyncID insertion unit 22 inserts a synchronization signal at a predetermined interval of the modulated codeword. The SYNC / SyncID insertion unit 22 has a termination table, performs modulation using the termination table as necessary, and inserts 30 bits of the synchronization signal pattern into the channel bit string. The codeword string including the synchronization signal and the DSV control bit is level-encoded by the NRZI converting unit 15. Then, the DSV control bit / SYNC determination unit 23 calculates a DSV value based on the transmitted level coded sequence, finally determines the value of the DSV control bit, and simultaneously determines the pattern of the synchronization signal. . The output value of the DSV control bit / SYNC determination unit 23 is a recording code string, which is the same as the final output value of the modulation device in FIG. The timing management unit 16 generates a timing signal and supplies the timing signal to the control bit insertion unit 21, the modulation unit 12, the SYNC / SyncID insertion unit 23, the NRZI conversion unit 15, and the DSV control bit / SYNC determination unit 23 to manage timing. Prepare to do.

  Next, the operation will be described. The control bit insertion unit 21 creates a bit string in which “1” is set in a DSV control bit inserted at a predetermined interval and a bit string in which a DSV control bit “0” is set, from the input data string. The modulation of these two types of data strings is performed by the next modulation unit 12. The modulation unit 12 includes a conversion table. Further, the SYNC / SyncID insertion unit 22 puts a synchronization signal between the modulated signals at a predetermined interval. The SYNC / SyncID insertion unit 22 has a built-in termination table, and converts a data string terminated to sandwich a synchronization signal into a codeword string. The codeword string is level-encoded by the NRZI converting unit 15. At this point, the DSV control bit has not yet been determined for the channel bit string, and there are two types of level code strings. Then, the DSV bit SYNC determination unit 23 calculates the DSV value, selects one of the channel bit strings in which the integrated DSV is suppressed, and determines this. At the same time, the pattern of the synchronization signal is determined. The determined code word string (channel bit string) is output as a data string subjected to DSV control.

  Next, an embodiment of a demodulator according to the present invention will be described with reference to the drawings. In this embodiment, demodulation is performed to demodulate a modulation codeword string obtained by converting a data string into variable length codes (d, k; m, n; r) = (1, 7; 2, 3; 4) in Table 3. It is applied to the device.

  FIG. 3 is a block diagram illustrating a configuration of a demodulating device that demodulates reproduction data including a synchronization signal. The comparator / inverse NRZI unit 31 compares the signal transmitted from the transmission path or the signal reproduced from the recording medium, converts the signal into an inverse NRZI (to an edge code), and outputs the result to the demodulator 32 and Supplied to the SYNC / SyncID identification unit 33. The demodulator 32 demodulates the edge-coded digital signal based on the demodulation table (inverse conversion table) and outputs the demodulated signal to the SYNC bit extraction unit 34. The SYNC / SyncID identifying unit 33 identifies the synchronization signal (Sync) inserted at a predetermined interval, and when the inverse conversion termination table of the termination table is used immediately before the synchronization signal portion, this information is demodulated. 32, and the SyncID is identified from the last 6 bits of the synchronization signal. The SYNC bit extraction unit 34 extracts a synchronization signal. The DSV bit extraction unit 35 removes the DSV control bits in the data string inserted at an arbitrary interval from the demodulated data string, and outputs the original data string. The buffer 36 temporarily stores the serial data input from the DSV bit extraction unit 35, and reads and outputs it at a predetermined transfer rate. The timing management unit 37 generates a timing signal, and supplies the timing signal to the comparator / inverse NRZI conversion unit 31, the demodulation unit 32, the SYNC / SyncID identification unit 33, the SYNC bit extraction unit 34, the DSV bit extraction unit 35, and the buffer 36. , Manage timing.

  The SYNC / SyncID identification unit 33 can determine the position of the synchronization signal by a unique pattern, and can also determine the position by counting the presence of the synchronization signal at a predetermined interval. When the position of the synchronization signal is found, demodulation in the vicinity immediately before it is performed including the termination table. On the other hand, the termination table is not required immediately after the synchronization signal, and demodulation can be performed using the normal table in Table 3.

  The SYNC bit extraction unit 34 removes only the number of bits of a predetermined synchronization signal after the previous demodulation is performed as described above, and maintains consistency with the demodulation unit 32.

  Next, the operation of the demodulator will be described.

  A signal transmitted from the transmission line or a signal reproduced from the storage medium is input to the comparator / inverse NRZI conversion unit 31 and is compared, and an inverse NRZI code ("1" indicates an edge). And is supplied to the demodulator 32 and the SYNC / SyncID identifier 33.

  This digital signal is demodulated in the demodulator 32 based on the inverse conversion table in Table 3. The demodulator 32 has the inverse conversion table of Table 3, but does not necessarily have the inverse conversion table for termination. In that case, there is a case where reverse conversion is impossible immediately before the synchronization signal is inserted. In this case, the SYNC / SyncID identifying unit 33 compensates for this. The SYNC / SyncID identification unit 33 sends detection information of the synchronization signal, and the demodulation unit 32 starts demodulation in synchronization with this.

  The SYNC / SyncID identifying unit 33 detects “x01 010 000 000 010 000 000 010” indicating the 2T-9T-9T part of the part given as the pattern of the synchronization signal. Since the synchronization signal pattern includes 9T, which is a unique pattern, it is not detected from other information codeword strings. Also, once the sync signal pattern is detected, the SYNC / SyncID identifying unit 33 can detect the sync signal pattern at a predetermined interval by using an internal counter or the like.

  The SYNC / SyncID identifying unit 33 also has an inverse conversion table of a termination table. The SYNC / SyncID identification unit 33 demodulates the codeword created by the termination table used for termination immediately before the synchronization signal and demodulates the result. Send to part 32. Eventually, either the demodulation unit 32 or the SYNC / SyncID identification unit 33 may have the terminal inverse conversion table.

  The SYNC / SyncID identifying unit 33 further identifies two or more types of synchronization signals that follow the 2T-9T-9T that is the pattern of the synchronization signal. For each synchronization signal, for example, a pattern with enhanced detection capability is selected.

  The 30 bits of the synchronization signal are removed by the SYNC bit extracting unit 34, and the DSV bit extracting unit 35 further removes the DSV control bits inserted at a predetermined interval.

  The reverse conversion table is as shown in Table 9 below, for example. Further, the terminal inverse conversion table is as shown in Table 10 below, for example.

<Table 9>
Reverse conversion table
PP17- (d, k; m, n; r) = (1,7; 2,3; 4) r = 4,
Codeword sequence Demodulated data sequence
i = 1 101 11
000 11
001 10
010 01
i = 2 010 100 0011
010 000 (not 100) 0010
000 100 0001
i = 3 000 100 100 000011
000 100 000 (not 100) 000010
010 100 100 000001
010 100 000 (not 100) 000000
i = 3: Prohibit Repeated Minimum Transition Runlength
001 000 000 (not 100) 110111
i = 4: limits k to 7
000 100 100 100 00001000
010 100 100 100 00000000

<Table 10>
Reverse conversion table
-----------------------------
Termination table
000 00
010 100 0000
-----------------------------

  As described above, the minimum run d = 1 is protected by determining and inserting the synchronization signal. The repeat of the minimum run remains limited to a maximum of 6 times. The maximum run k = 7 does not occur except within the synchronization signal. In the synchronization signal, 9T with k = 8 is continued twice, and the detection capability is enhanced. When the synchronization signal according to Table 6 is given, the synchronization signal has seven kinds of synchronization signal IDs, each having a detection capability of 2 distances, and the detection capability of the synchronization signal ID is enhanced. While having the above properties, DSV control within a data bit is possible, and efficient DSV control can be performed.

  Therefore, it has a variable length of minimum run d = 1, maximum run k = 7, conversion rate m / n = 2/3, has a replacement code for limiting the number of repetitions of the minimum run length, and is an element of the conversion table In the conversion table, the remainder when the number of “1” in the number and the number of “0” in the element of the codeword string to be converted divide by 2 is equal to 1 or 0. When the sync signal is inserted at the position of, the minimum run and the repeat limit of the minimum run are not changed, and the sync signal is selected with a unique signal pattern and strong detection capability. Thus, the synchronization signal can be detected more stably and reliably. Further, since the data string can always be terminated at the break where the synchronization signal enters, the data management before and after the synchronization signal at the time of demodulation is facilitated, and more stable demodulation is possible.

  In the present specification, the term “system” represents the entire apparatus including a plurality of apparatuses.

  As a providing medium for providing a user with a computer program for performing the processing as described above, a communication medium such as a network or a satellite can be used in addition to a recording medium such as a magnetic disk, a CD-ROM, or a solid memory. .

It is a block diagram which shows the structure of one Embodiment of a modulation apparatus. It is a block diagram which shows the structure of other embodiment of a modulation apparatus. It is a block diagram which shows the structure of one Embodiment of a demodulation apparatus.

Explanation of symbols

  11 DSV bit determination / insertion unit, 12 modulation unit, 13 SYNC / SyncID determination unit, 14 SYNC bit insertion unit, 15 NRZI conversion unit, 21 control bit insertion unit, 22 SYNC / SyncID insertion unit, 23 DSV bit SYNC determination unit, 31 Comparator / Inverse NRZI conversion unit, 32 Demodulation unit, 33 SYNC / SyncID identification unit, 34 SYNC bit extraction unit, 35 DSV bit extraction unit

Claims (8)

In a modulation device that modulates data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits,
A synchronization signal adding means for adding a synchronization signal having a pattern for breaking the maximum run and a pattern for protecting the minimum run and the maximum run to the code string;
The synchronization signal has one uncertain bit that can be replaced with “0” and “1” for DSV (Digital Sum Value) control in a pattern other than the pattern that breaks the maximum run,
Even if the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal satisfies the restriction that the repetition can be repeated a predetermined number of times together with the minimum run in all code sequences. Modulation device. The modulation device according to claim 1 , wherein the synchronization signal has two or more types of mutually distinguishable patterns. In a modulation method for modulating data having a basic data length of m bits into a code (d, k; m, n; r) having a basic code length of n bits,
A synchronization signal adding step of adding a synchronization signal having a pattern for breaking the maximum run and a pattern for protecting the minimum run and the maximum run to the code string;
The synchronization signal has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run.
Even if the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal satisfies the restriction that the repetition can be repeated a predetermined number of times together with the minimum run in all code sequences. Modulation method. A code sequence created by a modulation method that modulates data with a basic data length of m bits into a code (d, k; m, n; r) with a basic code length of n bits, a pattern that breaks the maximum run, and a minimum A sync signal having a pattern that protects the run and the maximum run is added,
The synchronization signal has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run.
Even if the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal has a data structure that satisfies the restriction that the repetition is repeated up to a predetermined number of times together with the minimum run in all code sequences. A recording medium on which a code string is recorded. The recording medium according to claim 4 , wherein the synchronization signal has two or more types of mutually distinguishable patterns. In a demodulator that demodulates a code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits,
A synchronization signal detection means for detecting a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run from the code string,
The synchronization signal has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run.
Even if the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal satisfies the restriction that the repetition can be repeated a predetermined number of times together with the minimum run in all code sequences. Demodulator. The demodulator according to claim 6 , wherein the synchronization signal has two or more types of mutually distinguishable patterns. In a demodulation method for demodulating a code (d, k; m, n; r) having a basic code length of n bits into data having a basic data length of m bits,
A synchronization signal detection step of detecting a synchronization signal having a pattern that breaks the maximum run and a pattern that protects the minimum run and the maximum run from the code string;
The synchronization signal has one uncertain bit that can be replaced with “0” and “1” for DSV control in a pattern other than the pattern that breaks the maximum run.
Even if the minimum run is included in the synchronization signal, the minimum run included in the synchronization signal satisfies the restriction that the repetition can be repeated a predetermined number of times together with the minimum run in all code sequences. Demodulation method.

Images