JP2714129B2 - Code transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code transmission method, and more particularly, to a code transmission method for performing transmission by adding an error detection and correction code to a main information code.

2. Description of the Related Art Generally, in a system in which an information signal such as an image signal is digitized and transmitted to a transmission path such as a recording medium, information data is converted into a transmission code suitable for the transmission path before transmission.

Hereinafter, in this specification, a magnetic recording device such as a digital VTR will be described as a typical example of such a transmission device.

Normally, in this type of magnetic recording device, it is difficult to record and reproduce very low frequency and DC components due to the transmission characteristics of the magnetic recording system. Therefore, after converting the digital data to be recorded into a recording code with few low frequency components,
An operation of recording is generally performed.

As a conversion coding method for suppressing the low-frequency component, a conversion coding method having a redundancy such as a method of converting 8-bit data into 9-bit data (8-9 conversion) is conventionally used. Have been. However, this method has a disadvantage that the redundancy is increased. With the increase in the data amount and the high-density recording, a coding method that does not increase the redundancy even from the background where recording and reproduction with a smaller number of codes is desired. Is desired.

Therefore, as a method that does not increase the redundancy, for example, nn which converts n-bit data into the same n-bit data is used.
A mapping coding scheme was considered. The nn mapping coding suppresses low-frequency components of a code sequence to be recorded by using a statistical property of an input code string, for example, a property that a correlation between adjacent codes is high in image information. Things.

As an example of this method, the input signal is differentially encoded, and the CDS is applied to a differential code having a high frequency of occurrence by utilizing the fact that the differential code has a positive distribution concentrated near zero of the positive / negative quantization level. A code with a small (Code word Digital Sum) is assigned, thereby reducing the DSV (Digital Sum Value) of the converted and coded code sequence. The low-frequency component of the code sequence to be recorded in this way is suppressed, and for example, a 4-4 mapping coding system that converts a 4-bit differential code into a 4-bit code can be used.

[Problems to be Solved by the Invention] By the way, in the mapping coding, as described above, for information codes such as image information having correlation between adjacent codes, it is possible to suppress a low frequency component of a coded code sequence. However, low-frequency components of codes having no correlation between codes cannot be suppressed.

For example, when an error detection / correction code for detecting or correcting a code error or a code sequence for recording additional information having no correlation is additionally inserted, the effect of suppressing low-frequency components of the code sequence is sufficient. I can't get it. As a result, the bit error rate at the time of decoding increases.

Hereinafter, this point will be further described with reference to FIGS. 2 and 3. FIG. FIG. 2 is a schematic diagram showing an example of the configuration of a general data frame in a code sequence to be recorded. In the portion shown as information data, the above-described mapping-encoded information code sequence is arranged and shown as parity. In the part, a parity such as an error detection and correction code, for example, a Hamming code or a Reed-Solomon code is arranged. Further, a synchronization pattern is arranged in a portion indicated as the synchronization data.

FIG. 3 shows an inner code (row check code) in the data frame of FIG. 2, a plurality of such data frames arranged vertically, and an outer code (column check code) vertically. It is a figure which shows the data matrix which comprised so that the product code may be comprised as a whole. In particular, in the case of such a configuration, since the main information code and the parity are two-dimensionally arranged, the code configuration is suitable for a device that records a code sequence obtained by performing two-dimensional encoding of image data and the like. I can say. This data matrix is recorded sequentially for each data frame.

However, when a data matrix as shown in FIG. 3 is formed, since there is no correlation between codes for the inner code and the outer code, the effect of suppressing low frequency components by mapping coding cannot be expected, and the same code is not consecutive. It can be said that the situation is likely to occur. In particular, in a data frame composed of only the parity of the code and the inner code, the parity is continuous for a long time, and there is a disadvantage that the low-frequency suppression effect of the code sequence in the vicinity is significantly reduced. .

As one method for solving such a problem, the present applicant has proposed a technique of distributing additional information codes such as error detection and correction codes in a code sequence to be recorded (Japanese Patent Laid-Open No. Sho 62-30).
No. 436). In this method, the codes causing low frequency components are dispersed in the code sequence, so that the code error rate at the time of decoding can be significantly reduced. By the way, in this method, the low frequency component itself of the error detection and correction code itself is not changed.

In this background, the present invention suppresses the low frequency components of the error detection and correction code itself as a whole,
An object of the present invention is to provide a novel encoding method capable of suppressing the entire low-frequency component of an encoded sequence.

[Means for Solving the Problems] Under such a purpose, according to the present invention, there is provided a method of adding an error detection / correction check code to each data group including a main information code and a control code and transmitting the same. A method of detecting a low-frequency component of the error detection / correction check code and determining the value of the control code according to the detection result.

In a preferred embodiment of the present invention, the value of the control code is determined so as to sequentially cancel low-frequency components of the error detection and correction check code.

[Operation] By configuring as described above, even when a continuous portion of the error detection and correction code exists in the code sequence used for transmission, the low frequency component of the code sequence can be sufficiently suppressed, and Code transmission can be performed.

Further, as shown as a preferred embodiment of the present invention, the low-frequency component of the error detection / correction check code is sequentially cancelled, so that the low-frequency component of the entire code sequence can be reduced without increasing the circuit scale. Can be suppressed. This control operation can be performed at high speed.

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a diagram showing a waist structure of a recording apparatus to which the code transmission method of the present invention is applied, and shows a generation unit of a code sequence to be recorded, particularly a generation unit of an outer code. FIG. 4 is a diagram showing a data matrix of a code sequence recorded by the apparatus of this embodiment.

In FIG. 4, I _ab is a main information code, and a = 1 to
k, b = 1 to i. Ib _ab is the parity of the inner code, and a = 0 to 2, b = 0 to m. OP _ab is the parity of the outer hit code, and a = 0 to 2, b = 1 to i. Further, D _ab is dummy data as a control code, and a =
1, b = 1 to i.

Fourth in the data matrix as shown in FIG. The first line on which is disposed the dummy data D ₁₁ to D _1i, as post-operative by the dummy data, the outer code parity OP ₀₁ ~
The value of OP _2i will be manipulated. Each of the inner code and the outer code has a 3-word parity added thereto, thereby forming a product code.

The circuit configuration in FIG. 1 mainly includes a circuit 106 for processing a main information code and circuits 213, 313, 413 for generating parities OP _0b , OP _1b , and OP _2b of outer codes. Each circuit 213,313,4
13 has the same circuit configuration, and parity calculation circuits 201, 301,
Only the internal counts of 401, data ROMs 205, 305, 405 and counters 209, 309, 409 are different.

It is assumed that the main information code in the input code Di has its low-frequency component suppressed by a mapping coding circuit (not shown). Further, it is assumed that all the dummy data in the code Di are preliminarily set to 0. This code Di is simultaneously input to the delay circuit 101 and the parity calculation circuits 201, 301, 401.

The parity calculation circuits 201, 301, and 401 are configured to perform calculations in the vertical direction of the data matrix, and the calculation of the main information code of k lines and the calculation of the outer code generation matrix by one line of dummy data in FIG. At the time of completion, the outer code parity for three lines is continuously output. In the following processing, only the circuit 213 that generates the outer code OP _0b of the 0th line will be described.

The parity generated by the parity calculation circuit 201 is OP ₀₁ ,
OP ₀₂ ... OP _{0n in} the order of delay circuit 203 and DSV (Digital Su
m Value) input to the arithmetic circuit 204. DSV operation circuit 204
_Does not operate when the parity is being calculated by the parity calculation circuit 201, and starts the operation at the same time as each outer code OP _0b is input. The DSV operation circuit 204 determines the number of 0s and 1s for each symbol (word) and calculates and holds the integrated value. From the circuit 204, the next parity CDS (Code word)
Digital Sum) is output as reference data. This data is the CDS value of the next parity according to the held DSV value. −8, −6, −4, −2,0,2,4,6,8
Output 4-bit data corresponding to 9 types of
It becomes an address control signal of the ROM 205.

The data ROM 205 is supplied with 4 bits from the DSV operation circuit 204 as an upper address and 8-bit parity generated by setting dummy data to 0 as a lower address. The data ROM 205 contains the CDS of the current parity with the DSV arithmetic circuit.
Data values to be inserted as dummy data in order to change to the CDS designated at 204 are stored as a table. However, as the data stored in the data ROM 205, a large value of CDS is excluded because the low frequency component of the dummy data itself needs to be suppressed.

The dummy data output from the data ROM 205 is output to the internal path 104 used in each of the parity generation circuits 213, 313, and 413, and the timing is adjusted by the delay circuit 202. Then, the new dummy data is inserted into the dummy data portion of the code string Di whose timing is similarly adjusted by the delay circuit 101 via the buffer 211 on the output bus 105.

The dummy data output to the internal bus 104 is multiplied by the coefficient from the coefficient unit 209 by the multiplier 207. The result of this multiplication is added to the parity generated with the dummy data as 0,
By adding at 8, a parity having a desired CDS is obtained. The value of the parity with this desired CDS is DSV
The value of the DSV which is fed back to the arithmetic circuit 204 and held by the parity is corrected.

By a series of operations as described above, in the parity of the outer code shown in FIG. 4, OP ₀₁ , OP ₁₂ , OP ₂₃ , OP ₀₄ , OP _15.
Set each parity to a desired CDS value in the order of. As a result, DSV control is performed in units of three words in the code transmission direction (line direction), and in all two data frames in which parity words are continuous, a code sequence in which low-frequency components are sufficiently suppressed is generated. This is output from the outer code parity generator. Thereafter, the parity IP _{ab of the} inner code is further added by a circuit (not shown), and is supplied to a recording system circuit at a subsequent stage.

With the above configuration, all three data frames consisting of only parity can be recorded as a code sequence in which low-frequency components are suppressed, and the occurrence of errors in the recording / reproducing system can be greatly reduced. Further, since each parity can be determined by only one operation, it can be realized with a relatively simple circuit configuration, and high-speed processing is also possible.

Incidentally, the parity of the inner code added in the subsequent stage is recorded continuously for three words.
According to the technique disclosed in Japanese Patent Publication No. 436, this inner code can be easily dispersed and left in each line, and there is almost no problem.

Next, another embodiment of the present invention will be described with reference to FIG.

FIG. 5 also shows only the configuration of the outer code generation unit, and records a code sequence represented by the data matrix of FIG. 4 as in the above-described embodiment.

In the figure, 1212 is a circuit for generating an outer code parity OP _0b ,
Reference numeral 1312 denotes a circuit for generating an outer code parity OP _1b, and reference numeral 1412 denotes a circuit for generating an outer code parity OP _2b . Since these circuits have the same configuration, FIG.
Only 12 discloses the internal configuration. These parity generation circuits 1212, 1312, and 1412 are different from the parity generation circuits 213, 313, and 413 of the embodiment of FIG. 1 in that a common dummy data generation unit 1008 is separately provided.

As in the embodiment of FIG. 1, the circuits 1212, 1312, and 1412 respectively perform parity calculation and DSV calculation. Taking the circuit 1212 as an example, the parity operation is performed by the parity operation circuit 1201.
The DSV calculation is performed by the DSV calculation circuit 1203. The data from these circuits 1212, 1312, and 1412 are sent to a common bus 1009 for parity, and data related to a desired CDS value is sent to a control bus 1010 via a common dummy data operation circuit 1008.
Supplied to

First, the parity and CDS designation data calculated by the circuit 1212 are input to the data ROM 1001 and the data ROM 1002 via the buses 1009 and 1010 as upper addresses. Data ROM
In 1001 and 1002, D in the parity continuation part of OP _0b
In order to generate a parity having a CDS necessary for causing SV to converge to 0, each table has data to be inserted into a dummy line.

In the data ROMs 1001 and 1002, dummy data for generating parity having the same CDS value and different values is output. The value output here is a value multiplied by the coefficient of the generator matrix so that a common table can be used for each parity.

The two types of dummy data output from the data ROMs 1001 and 1002 are input to coefficient units 1003 and 1004, respectively, where the data is divided by the coefficient of the generation matrix of the parity OP _0b selected by a control signal described later, and the dummy data is output. Is supplied to the decision circuit 1005 in the form of data inserted as At this time, data from the circuit 1312 for the parity OP _1b has been output to the buses 1009 and 1010, and are simultaneously supplied to the discrimination circuit 1005.

The discrimination circuit 1005, coefficients of the generator matrix of the parity OP _1b is multiplied to the input two kinds of dummy data, further, is added with parity from the parity OP _1b circuit 1312, a parity OP _1b are two types to be inserted Generated. Further judgment circuit
In 1005, the CDS of the two kinds of parity respectively determined, based on the DSV values of the parity OP _1b being input, the direction which can generate high parity of the effect of suppressing the low-frequency component with respect to the parity OP _1b The switching circuit 1006 is controlled to select dummy data.

Thereafter, the coefficient of the generator matrix of the parity OP _0b is multiplied by the coefficient unit 1007 in the same manner as in the above-described embodiment, and is output to the internal bus 1011 as in the embodiment of FIG. The operation after this is exactly the same as that of the embodiment of FIG. 1 described above. Insertion of dummy data and update of parity are sequentially performed, and parity with reduced low frequency components is output from this outer code generation unit. Will be.

Although the detailed configuration of the discrimination circuit 1005 is not particularly disclosed, it will be apparent that the configuration can be easily configured from the configuration of the parity generation circuit shown in FIGS.

Further, the control signals are parity OP _0b , OP _1b , OP
_{In 2b} , this data indicates which parity column is currently being operated to reduce the DSV, and can be easily obtained in synchronization with the input timing of the code Di. That is, the above-described processing is about the process of performing the DSV control of the parity column based on the data output from the circuit 1212 for the parity OP _0b , but at the next timing, the data from the circuit 1312 for the parity OP _1b is The processing is performed based on this, and the determination circuit 1005 switches the switching circuit 1006 to reduce the DSV of the parity column parity OP _2b as much as possible. Similarly, parity
Processing is performed based on data from the circuit 1412 for OP _2b ,
The determination circuit 1005 repeats the process of switching the switching circuit 1006 in order to reduce the DSV of the parity row _OP0b as much as possible.

According to the configuration shown in FIG. 5 as described above, the DSV of each parity can be performed more frequently than the configuration of FIG. 1, and the suppression of low frequency components in a portion where the parity is continuous is more effective. It can be done in a typical way. According to the present embodiment, two types of dummy data are generated and selected. However, by increasing the types of the dummy data, it is possible to further enhance the effect of suppressing low frequency components. It is. Also refer to the DS to make this selection
It will also be apparent that low frequency components can be more effectively suppressed by obtaining V from more parity strings.

In the present invention, the number of parities of each check code is 3
Although the word is used, the present invention is applicable regardless of the number.

[Effect of the Invention] In this background, the present invention suppresses the low-frequency component of the error detection and correction code itself as a whole,
An object of the present invention is to provide a novel encoding method capable of suppressing the entire low-frequency component of an encoded sequence.

As described above, according to the code transmission method of the present invention,
By suppressing the low frequency component of the error detection and correction code itself, the entire low frequency component of the coded sequence can be suppressed, and good code transmission can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of a recording apparatus as an embodiment of a code transmission method according to the present invention, FIG. 2 is a schematic diagram showing a configuration of a general data frame, and FIG. FIG. 4 is a diagram showing the configuration of a data matrix when a product code is formed using the data frame of FIG. 4, FIG. 4 is a diagram showing the configuration of a data matrix handled by the configuration of FIG. 1, and FIG. FIG. 11 is a diagram illustrating a main configuration of a recording apparatus as another embodiment of the method. In the figure, 101 is a mapping coding circuit, 213, 313, 413, 1212, 1312, 1412 are parity generation circuits, 201, 301, 401, 1201 are parity operation circuits, 204, 304, 404, 1203 are DSV operation circuits, 205, 305, 405, 1001, 1002 are data ROMs, respectively. , 209, 309, 409, 1004, 1005, 1007, and 1208 are coefficient units, 1005 is a discrimination circuit, and 1006 is a switching circuit.

Continued on the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location H04N 7/24 H04N 7/13 A

Claims (2)

(57) [Claims] 1. A method of adding an error detection / correction check code to each data group including a main information code and a control code and transmitting the data, wherein a low-frequency component of a past error detection / correction check code is detected and detected. A code transmission method, wherein a value of the control code is determined according to a result. 2. The code transmission method according to claim 1, wherein the value of the control code is determined so as to sequentially cancel low-frequency components of the error detection / correction check code.