JP2945539B2 - Error correction result check circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding apparatus used for recording and reproducing digital data and the like, and more particularly to an error correction result checking circuit.

[0002]

2. Description of the Related Art Generally, data errors are corrected by various methods as digital data is recorded at higher density.

[0003] For example, in a digital video tape recorder (VTR), it is known that erroneous correction causes a serious problem to the image quality rather than performing uncorrectable processing such as complementation. I have.

[0004] As a method for preventing erroneous correction, when there is a margin in the distance and there is a syndrome that is not used in obtaining the position and size of the error, a check based on the syndrome is generally performed.

In the conventional error correction prevention method, when input data is D _n−1 , D _n−2 , D _n−3 ,..., D ₂ , D ₁ , D ₀ , one of the syndromes S _x is , Input data D
_{n-1, D n-2} , D n-3, ..., sequentially _{D 2, D 1, D 0} ,
By going input to the syndrome calculation circuit shown in FIG. 2, when the input data D ₀ of the final was incorporated into the flip-flop, it is obtained as follows as its output.

[0006]

(Equation 1)

Where n is the code length and α is the Galois field GF
The primitive element of (q ^m )｝ where, if there is no error in the data sequence, the syndrome becomes zero, and the resulting value is as shown in the following equation.

[0008]

(Equation 2)

[0009] However, D _i 'is input data - is the magnitude of the errors in the data D _i, represents the magnitude when there is an error, and 0 if no error.

Further, it is possible to uniquely represent the position of the error D _i 'in the code by alpha ^i, the alpha ⁱ is referred to as an error position.

Therefore, the error magnitudes D _n-1 'to D ₀ ' of each data obtained by the operation are sequentially input to the syndrome operation circuit shown in FIG.
_If it matches _X , it can be determined that the correction has been completed.

Further, as a method of obtaining the position and size of an error, a method using an error position polynomial and an error numerical polynomial is known.

This is because α ⁻ⁱ (i = 0,1,2
…, N-1) are sequentially substituted to perform a Chien search for a value.
This is a method of calculating the error position and the size of the error in synchronization with the error position.

[0014]

However, in the above-mentioned conventional method for preventing erroneous correction, a data string is calculated from the input data D _n-1 at the time of syndrome generation and verification, and the input data is calculated at the time of chain search. - for sequentially calculated from data D ₀ side is performed, until the Chien search is completed it is necessary to wait for verification, resulting in a problem of increasing the processing time of the error correction.

The present invention has been made in view of the above-mentioned problems in the conventional method for preventing erroneous correction, and provides an error correction result check circuit capable of efficiently processing error correction.

[0016]

According to the present invention, there is provided a syndrome including a Galois field addition of a data string and an error position inputted to an error correction circuit, and a first sequence outputted from a Chien search circuit.
Adds error size data, and adds the result
Calculating means for calculating error magnitude data sequentially output from the search circuit based on a predetermined relational expression; and determining whether or not the calculation result is a specific value which is connected to the calculating means. This is achieved by an error correction result checking circuit having means.

[0017]

[Action] In verification circuit of the error correction result of the present invention, computing means from the syndrome and Chien search circuit including a Galois field addition of the data string and the error position input to the error correction circuit
Add the data of the size of the first error output and add
Calculation result and error magnitude sequentially output from Chien search circuit
Data is calculated based on a predetermined relational expression, and the determination means is connected to the calculation means and determines whether or not the calculation result is a specific value.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a circuit for checking an error correction result according to the present invention; First, before describing an embodiment of the error correction result check circuit according to the present invention, a data string input to the error correction circuit for explaining a method used in the check circuit is represented by D _n−1 , D _{n−. 2} , D _n-3 , ..., D ₂ , D
₁ , D ₀ , and syndrome S used for correction processing
_x ,

[0019]

(Equation 3)

Where n is the code length and α is the Galois field GF
A primitive element of (q ^m ) (q: prime number, m: natural number), where x is 0 or a natural number｝,

[0021]

(Equation 4)

{However, for D _i ′, the calculation shown in the error magnitude at the error position α ⁱ is performed, and the determination is made based on whether the value is zero or non-zero.

The error magnitude data string output from the Chien search circuit after the calculation of the error position and error magnitude is represented by D ₀ ', D ₁ ', D ₂ ', ..., D _n-3 ',
D _n−2 ′, D _n−1 ′ (where D _i ′ is the size of the error of D _i ) and the order is reverse to that of the input data sequence, so the syndrome shown in FIG. The arithmetic circuit cannot calculate the syndrome. If this is calculated by the check circuit of FIG.

[0024]

(Equation 5)

Is as follows. Here, if the correction is correct, the following equation is established.

[0026]

(Equation 6)

Therefore, if only the data D ₀ 'of the magnitude of the first error output from the Chien search is added to the syndrome _Sx , the final error can be obtained by inputting the data to the verification circuit shown in FIG. When the magnitude data D _n-1 'is taken into the flip-flop 20, the correction can be checked without delay depending on whether the output value is zero or not.

3 includes an adder 19, a flip-flop 20 connected to the adder 19, and multipliers 21 connected to the adder 19 and the flip-flop 20, respectively.

Next, an embodiment of the error correction result check circuit according to the present invention will be described.

FIG. 1 shows the configuration of an embodiment of an error correction result check circuit (hereinafter, referred to as a check circuit) according to the present invention, which is a more specific example of the structure shown in FIG.

The checking circuit shown in FIG. 1 includes a selecting circuit 10 and a selecting circuit.
A first adder connected to 10 and constituting an operation means
11, the second adder 12 connected to the first adder 11, the flip-flop 13 and the multiplier 14 connected to the second adder 12, the selection circuit 10 and the second adder 12 and the multiplier 14, respectively. It is constituted by an AND circuit 15 of a logic circuit element that is the determined means.

Next, the operation of the verification circuit shown in FIG. 1 will be described.

The selection circuit 10 inputs the syndrome _Sx used for the check as an input signal to an input terminal, and keeps low (D) during the first data D ₀ ′ of the data string output from the Chien search circuit (not shown). A reset signal synchronized to a Low level is input to the control terminal, and the control terminal is driven low (Low).
w) level, the input signal is output as it is, and high (H)
i) 0 is output at the time of level.

Next, the operation process of the verification circuit shown in FIG. 1 will be described in detail.

The first adder 11 receives the output from the selection circuit 10 and the data strings D ₀ 'to D _n-1 ' indicating the magnitude of the error output from the Chien search circuit. Thus, the output from the first adder 11 is

[0036]

(Equation 7)

Is as follows.

The output from the first adder 11 is input to a circuit consisting of a second adder 12, a flip-flop 13, and a Galois field α- ^x multiplier 14 to determine the magnitude of the final error. When the data D _n-1 'shown in FIG.

[0039]

(Equation 8)

Is output. Whether the correction result is correct can be determined based on whether the value of this equation is 0 or not.

The reset signal is input to the AND circuit 15 to initialize the flip-flop 13.

That is, the error correction result checking circuit of the present invention comprises a data sequence D _n−1 ,
D _n-2 , D _n-3 , ..., D ₂ , D ₁ , D ₀ and the error position α ⁱ
By the Galois field operation of the syndrome S _x

[0043]

(Equation 9)

The error magnitude D _i ′ at the error position α ⁱ obtained as a correction result and the syndrome
Relational expression of the check result r _i indicating addition with the sum S _x

[0045]

(Equation 10)

[0046] and, Galois alpha ^-x and input data of the error position alpha ⁱ - the multiplication of the error magnitude D _i 'of data D _i verification result r
Relational expression of check result r _i indicating addition with _i-1

[0047]

[Equation 11]

Is performed, and when the last data D _n-1 in the Chien search output is input, it is determined whether the verification result r _n-1 is zero or non-zero. It is determined whether the correction result is correct.

The selection circuit 10 can be easily constituted by a gate, a multiplexer and the like.

Embodiments other than those shown in FIG. 1 are shown in FIGS.

In the embodiment shown in FIG. 4, the adder 12 and the AND
The circuit 15 has been deleted, and the AND circuit 15 has been deleted in FIG. The operation is the same as that of the embodiment of FIG.

With the above configuration, a check result can be obtained from the output terminal without consuming extra operation time.

[0053]

The error correction result checking circuit according to the present invention provides a syndrome including a Galois field addition of a data string and an error position input to the error correction circuit and an output from the Chien search circuit.
Is added to the data of the size of the first error
And the error magnitude data sequentially output from the Chien search circuit.
Calculating means for calculating on the basis of the over data in a predetermined relationship,
Since it is connected to the calculating means and includes a determining means for determining whether or not the calculation result is a specific value, it is possible to execute the checking process simultaneously with the calculation of the error position and the error magnitude by the Chien search, As a result, no extra standby time is required, and the correction process can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an error correction result check circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a syndrome operation circuit.

FIG. 3 is a block diagram showing an example of a configuration of a part of an error correction result check circuit of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a second embodiment of an error correction result check circuit according to the present invention;

FIG. 5 is a block diagram showing a configuration of a third embodiment of an error correction result check circuit according to the present invention.

[Explanation of symbols]

10 Selection circuit 11, 12 Galois field adder 13 Flip-flop 14 Galois field α- ^x multiplier 15 AND circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-43419 (JP, A) JP-A-63-97018 (JP, A) JP-A-2-21723 (JP, A) JP-A-1- 260930 (JP, A) JP-A-4-156621 (JP, A) JP-A-62-122333 (JP, A) JP-A-62-137924 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 13/00-13/22

Claims (1)

(57) [Claims] 1. A recording such as digital data, a verification circuit of the error correction results to verification using the syndrome correction result of the error correction apparatus used for reproduction, the data sequence and the error position input to the error correction circuit Syndrome with Galois Field Addition and First Error Output from Chien Search Circuit
, And adds the result to the Chien search.
Calculating means for calculating error magnitude data sequentially output from the circuit based on a predetermined relational expression, and connected to the calculating means to determine whether or not the calculation result is a specific value An error correction result check circuit, comprising a determination unit.