JP2578739B2 - Erase correction method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erasure correction method used for an error correction device that can be used for transmitting or recording and reproducing digital data.

Conventional configuration and its problems In recent years, audio signals and the like are digitally recorded and reproduced.
PCM recorders have been developed, but defects and scratches on the recording media
An error correction code is used to correct a code error caused by dust or the like.

Hereinafter, a conventional erasure correction circuit will be described with reference to the drawings. FIG. 1 is a configuration diagram of an error correction code processed by a conventional error correction circuit, where 1 is data W such as an audio signal, 2 is a first check code P, and 3 is a second check code Q. .

First code C ₁ is the 8 co longitudinally data W or the second
It is composed of a check code Q and one first check code P, which is called one block. Second code C ₂ is constituted by a second check code Q data W and 2 U-6 U per interleave distance D 'in the direction toward the lower right in FIG. (= 16 blocks). First code C ₁ is a cyclic redundancy check code (abbreviated as CRCC), performed only detection of an error. Second code C ₂ is b adjacent codes, performs error correction by the decoding information of the first code (i.e. information on whether an error is detected.).

FIG. 2 is a block diagram of an error correction device using a conventional erasure correction circuit, where 10 is an encoder, 11 is a second encoder, 12 is a first encoder, and 20 is a transmission or recording medium. , 30 is a decoder, 31 is a first decoder, and 32 is an erasure correction circuit.

The operation of the error correction device configured as described above will be described below.

A data string such as a digitized audio signal is input from an input terminal of an encoder 10 and firstly a second encoder
11 together with the second check code Q generated by C
It is arranged every _two D 'blocks in _two directions. When C in _two directions the second check code 6 U data and 2 co is arranged, the following 6
U data and 2 co set of check code from the position shifted one block right, it is placed in the C ₂ direction. It is arranged in the following order. Next, the first encoder 12 takes out the data and the second check code arranged as described above, eight at a time, in the C1 direction in FIG. ₁ and adds the first check code P to the transmission or recording medium. Send out to 20. When the first row has been sent out, the second
The data and the check code string form an error correction code in which 245 blocks are referred to as one segment unit.

The data and the check code string received or reproduced from the transmission or the recording medium 20 are input to the decoder 30, and first, the first decoder 31 detects the presence or absence of an error. The decoded information as 1 bit pointers to each row in the C ₁ direction of FIG. 1, are sent to the erasure correcting circuit 32 is a second decoder with the data W and the second check code Q. Erasure correction circuit 32, the data in the C ₂ direction W and the second
The number of pointers to which the check code Q belongs is checked. If 0, there is no error. If 1 or 2, error correction is performed.
Reading data W in the C ₂ direction while adding the outputs through the output terminal of the decoder 30. The output data is returned to the original audio signal or the like after being converted to analog again. Error correction in the erasure correction circuit is executed in the following procedure.

Assuming now that the number of pointers is two, the number of errors is two, and the location can be obtained by examining at what data the pointer is standing. Assuming that the pointers are set at the i-th and j-th data, the location is Given by Therefore, the error location is determined by reading the pointer and checking whether the value is 0 or 1.

 Next, the syndrome is calculated according to the following equation.

Here, _Ri is a received word. In this conventional example, n = 8, k =
6.

The second check code Q is attached so as to satisfy the following equation. The received words R _i , R _j containing an error are represented as follows, where the error pattern at that location is Y ₁ , Y ₂ : Therefore, the value of the syndrome obtained by equation (2) is Becomes From this, when the error patterns Y ₁ and Y ₂ are obtained, Is required. If an error pattern is found, the correction is (4)
This is performed as follows according to the equation.

However, in such the above configuration, the error had serious problem called can not be corrected if the number of errors in the C ₂ direction exceeds 3. Further, when the number of the second check codes is increased by extending the code to make it possible to correct three or more errors, the amount of calculation of the equation (6) is calculated by solving the equation (5) to obtain the error pattern Y _i. Has a problem that it increases sharply as the number i increases, making it impractical for practical use.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an erasure correction method for realizing correction of more than three errors with a very small amount of calculation.

The erasure correction method of the present invention is an erasure correction method when the locations of all errors are known,
An element on the Galois field GF (2 ^b ) defined by any positive integer b, W
_{Using i} (i = 1, 2,..., k) (k: positive integer) as an information point, and using the primitive element α of the Galois field, An element on the Galois field that satisfies W _j (j = k + 1, k + 2,...)
.., N−k−1) are used as check points in a code having l known error locations (l: positive integer, l ≦ n−).
k), the signal R _i (i = 1,2,..., n) in which the error has occurred is received, and the location of the error is determined by X ₁ (i = 1,2,.
... l), and the error pattern at each location is Y
₁ (i = 1, 2,... L), and the variable is Z, A location operation step for obtaining an error location polynomial Λ by A syndrome calculation step of determining a syndrome S _i, the recurrence formula By, which is characterized in that is constituted by an error pattern calculation step of determining an error pattern Y _i, by using the above recurrence formula, the number of test points _{W j (n-k-1} ) is increased Even so, many errors can be corrected with a small number of arithmetic circuits. Further, the location operation circuit is expressed by the following recurrence formula: C (1,0) = 1 C (1,1) = X ₁ C (1, −1) = C (i, i + 1) = 0 (i = 1,2,... L) The configuration that expands the location polynomial Λ enables multiple error correction with a smaller amount of computation.

DESCRIPTION OF THE EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows a configuration diagram of an error correction code used in an error correction device using an erasure correction circuit in one embodiment of the present invention. In FIG. 3, 1 is data W, 2 is a first check code P, 3 is a second check code Q, and 1st code C ₁ is a (n, k) Reed-Solomon code (the present embodiment) , N = 32, k = 29), the second code C ₂ is an array orthogonal to the first code C ₁ in the horizontal direction of the figure, and the interleave distance D (D = 4 in this embodiment) For each m data W or second check code Q, (m, h)
Reed-Solomon code (m = 32, h = 25 in this embodiment)
It constitutes.

FIG. 4 is a block diagram of an error correction device using an erasure correction circuit according to one embodiment of the present invention, wherein 10 is an encoder, 11 is a second encoder, 12 is a first encoder, 20 Is a transmission or recording medium, 30 is a decoder, 31 is a first decoder, and 32 is a second decoder using an erasure correction circuit.

The operation of the error correction device of the present embodiment configured as described above will be described below. Since the signal flow is the same as in the conventional example, the difference from the conventional example will be described here. In this embodiment, the first code is (32,2) on GF (2 ⁸ ).
9) It is a Reed-Solomon code, and its generator polynomial is given by the following equation.

G (x) = (x−1) (x−α) (X−α ² ) G
^F (2 ⁸ ) (13) where α is the root of GF (2 ⁸ ) on the GF (2 ⁸ ) of the polynomial g (X). For example, the following equation is used as the modal polynomial g (X).

g (X) = X ⁸ + X ⁴ + X ³ + X ² + 1GF (2) (14) The 29 data are represented by W ₁ , W ₂ ... W ₂₉ , 32-29 = the first of 3 data
Assuming that the check codes are P ₁ , P ₂ , and P ₃ , the check determinant to be satisfied by the first code is given by the following equation.

It is expressed as The first encoder has 29 data _Wi (i
= 1,2... 29), A, B, and C are calculated, and P _i (i = 1, 2)
2,3). Those skilled in the art know that the first encoder that performs this calculation can be realized as software by a computer program, or can also be realized as hardware by a theoretical circuit, and detailed description is omitted. . For example, as shown in FIG. 4 of Japanese Patent Application No. 58-66159, α
Can be used as a circuit for calculating the values of A, B, and C in equation (16). The arithmetic circuit for dividing A, B, and C in the expression (18) by the expression α can be realized by using a similar multiplication ROM table and a ROM table for storing the division result.

Since the first code has three check codes, the inter-code distance is 4, and single error detection and correction and double or more error detection are possible. In general, if the number of errors for which the inter-code distance can be corrected by d is t, 2t + 1d is established.

Therefore, the first decoder performs single error correction and raises a pointer when double or more errors are detected. The error detection / correction process is as follows.

The received or reproduced first code is represented by W _i (i = 1, 2,..., 32)
Expressed by No distinction is made between data and check codes for convenience.

First, a syndrome S _i (i = 0, 1, 2) is obtained.

The circuit for performing this calculation can be realized by the same circuit as the circuit for calculating the above equation (16). Now, the i-th word W _i
Assuming that an error has occurred above, the error pattern is represented by Y _i and the location. When α ^i-1 is represented by X _i ,
Received word R _i is expressed by the following equation.

R _i = W _i + Y _i (20) Also, since the value of the syndrome satisfies equation (3), It is expressed as Therefore, the first decoder calculates S ₀ , S ₁ , and S ₂ , detects the occurrence of an error because each value is not 0, and To determine if it is a single error. The operation circuit of the expression (22) can be realized by using a ROM table for storing the division result in the same manner as the expression (18). (2
If there is an i that satisfies the expression (2), it is determined as a single error, and (2)
1) The error correction is completed by adding the error pattern obtained by the first equation to the i-th received word R _i .

W _i = R _i + Y _i (23) The arithmetic circuit of Expression (23) can be easily realized by using an adder. If there is no i satisfying the expression (22),
It is determined that there is a double error or more, a pointer is generated, and the pointer is sent to the memory in the second decoder.

The configuration of the first decoder for realizing the above error detection / correction process may be a configuration in which the individual arithmetic circuits are connected in cascade, or a set of a multiplication ROM table, an adder, and a division ROM table And a combination with a control circuit for sequentially inputting necessary values for each of them to obtain an operation result may be used. However, as in the case of the first encoder, a person skilled in the art knows, and a detailed description will be given. Is omitted. The details are described in, for example, "Code Logic" by Imai et al., Shokodo, 1975.

The second code is (32,2) on GF (2 ⁸ ) in this embodiment.
5) Since it is an RS code and the distance between the codes is 8, it is possible to detect and correct triple errors by itself. If the position of the error, that is, the location is known by a pointer or the like, up to 7-fold correction It is possible. In general, error correction when the location is known is called erasure correction, and if the inter-code distance is d and the number of erasure-correctable errors is e, then e + 1d holds.

It is also possible to combine erasure correction and single error detection and correction (abbreviated as error correction), in which case 2t + e + 1d (24) is established.

The second encoder generates a second check code Q _i (i = 1, 2,..., 7) satisfying the following equation in the same manner as the first encoder.

The second encoder can be realized by the same circuit as the first encoder described above. FIG. 5 is a block diagram of a second decoder using an erasure correction circuit according to one embodiment of the present invention, wherein 321 is an erasure correction circuit according to one embodiment of the present invention, 322 is an erasure error correction circuit, 323 is an error correction circuit.

The operation of the second decoder configured as described above according to the present embodiment will be described below.

In the case of the present embodiment, the second decoder 32 calculates the number p of pointers.
Make the following corrections:

(1) When p = 0 or ≧ 8 Two error correction is performed.

(2) When 1p = 6 Perform 5 erasures + 1 error correction.

(3) When p = 7 Seven erasure corrections are performed.

The pointer is one for each column in FIG. 3, and when viewed from the second code orthogonal to the first code, the pointer is common to the second code for each row. If is obtained once, it can be used in common for each row, so that the number of operations can be reduced.

(1) Two-Error Correction When the second decoder 32 determines that the number of pointers is 0 or 8 or more, it sends data to the error correction circuit 323 and performs correction in the following procedure.

First, the operation for finding the syndrome of the first decoder (19)
Using the same circuit as that used in the equation, the syndrome S _j (j = 0,
1, ... 6).

The two error patterns Y ₁ , Y ₂ and the location are each X
When _1, X _2, syndrome is expressed by the following equation.

The location polynomial with the error location as the root is Then, between the coefficients σ ₁ and σ ₂ and the syndrome S _j , Holds, if the value of the denominator in equation (29) is not 0, σ ₁ and σ ₂ are obtained. If 0, it is determined that there are three or more errors, a flag is set, and the correction operation is completed. Once σ ₁ and σ ₂ have been determined, the root of equation (28) = 0 is determined in order to determine the location.

Z = σ ₁ A (30) Since A that satisfies equation (31) is uniquely determined, By obtaining the value of A in advance in accordance with the value of, and having this as a root table, it is possible to obtain A and obtain the root from equation (30).

If the location is found, the error pattern is And the correction is performed by the same circuit that realizes the expression (23). The arithmetic circuits of the above equations (29) and (32) are realized by a multiplication ROM table, an adder, and a division ROM table, as in the first decoder.

(2) 5 erasures + 1 error correction When the number of pointers is 1 or more and 6 or less, the second decoder 32 sends data to the erasure / error correction circuit 322 and performs error correction according to the following procedure.

First, the erasure location polynomial Λ is determined.
The position of the error is determined by the word at which the pointer is set. For example, if the pointer is set at the k-th position, the location is obtained as X = α ^k−1 .

Now, assuming that five pointers are standing, if five locations X _i (i = 1, 2,... 5) are obtained, the erasure location polynomial Λ becomes Is obtained. On the other hand, the error pattern at each location is Y _i (i = 1, 2,... 5).

Since equation (33) is a quintic equation of Z, it is expanded as follows and each coefficient C (i, j) (i = 1, 2,... L, J = 0, 1,... I) Ask for.

Let C (i, -1) = C (i, i + 1) = 0 (i = 1,2... L).

Then, equation (33) becomes Becomes Next, calculating C (2, j) = C (1, j-1) X ₂ + C (1, j) (0 ≦ j ≦ 2) (36) Becomes Next, when C (3, j) = C (2, j−1) X ₃ + C (2, j) (0 ≦ j ≦ 3) (38) is calculated, the equation (37) becomes: Becomes Similarly, C (i, j) = C (i−1, j−1) X _i + C (i−1, j)
(40) (i = 1,2 ... l, j = 0,1 ... j) And Λ can be calculated. The arithmetic circuit of C (i, j) is a multiplication ROM
This is realized by a table and an adder.

Next, if the location of the error to be detected / corrected by a single error is X ₆ and the pattern is ₆ , the syndrome S _j (j =
0,1 …… 6) So, taking this, the location is Because represented as the location polynomial in a similar manner using coefficients obtained in the deployment C and (5, j) the syndrome S _i multiply ROM table, adders, can be easily obtained by dividing the ROM table.

When the denominator of equation (43) = 0, X ₆ = 0 from equation (42).
Y ₆ = 0, and a quintuple error is determined.

When the denominator ≠ 0, X ₆ = α _k (0 ≦ k ≦
If (31) is present, it is the sixth location to be sought, otherwise, it is determined that correction is not possible and a flag is set.

If the number of pointers is 6, the value obtained by equation (43) is
By checking whether or not the location matches the location obtained from the sixth pointer, it is possible to determine whether or not correction is possible. If they do not match, it cannot be corrected.

When the number of pointers is 4 or less, with (33) and later, the value of X _i exceeds the number of pointers may be set to 0.

If the location is found, the value of the error pattern is (42)
Solve the equation Is calculated. Next, with S _i = S _{i, 0} , By obtaining, Y ₅ becomes Is obtained by calculating. Sequentially _{below, S i, 7-l =} S i, 6-l + Y l X l i (i = 0,1 ...... l-1) (l = 6,5 ...... 2) seek (47) Is repeated, and finally Y ₁ is obtained from Y ₁ = S _0,4 + Y ₂ (49), whereby all Y _i are obtained.

If the number of the pointer is 4 or less, the value of the number or more of Y _i of the pointer may be set to 0.

Thus, if Motomare error patterns, _{correction, W i = R i + Y} i (i = 1,2 ...... 6) (50) takes place. Similarly, the arithmetic circuits of the above formulas (44) to (50) are realized by a multiplication ROM table, an adder, and a division ROM table.

(3) Seven Erasure Correction When the number of pointers is seven, the second decoder 32 sends data to the erasure correction circuit 321 and performs correction in the following procedure.

FIG. 6 is a block diagram of an erasure correction circuit according to one embodiment of the present invention, wherein 3211 is a location operation circuit, 3212 is a syndrome operation circuit, and 3213 is an error pattern operation circuit.

The operation of the erasure correction circuit configured as described above in one embodiment of the present invention will be described below.

First, in the location calculation circuit 3211, the coefficient C (i, j) of the location polynomial Λ is obtained.

The expansion of the above equation is performed in the same manner as in the case of (2) to obtain the following equation.

Further calculate the C (6, i) = C (5, i-1) X 6 + C (5, i-1) (53), And the coefficient C (i, j) are obtained, and Λ can be expanded. The location calculation circuit for obtaining the coefficient C (i, j) is realized by a multiplication ROM table and an adder. Next, the syndrome operation circuit 3212 is realized with the same circuit configuration as the second encoder, but calculates the expression (26) and calculates the syndrome S _j (j = 0, 1,...).
... 6).

On the other hand, the syndrome is erasure location X
_i and the pattern Y _i can be expressed as follows.

Above which seek error pattern Y _7, the following equation.

Error pattern calculation circuit 3213 multiplies ROM table, adders are constituted by divided ROM table, obtains the Y ₇ by calculating the (56) equation. When Y ₇ is obtained, by obtaining a S _{i, 0} through S _i, as in the case of _{(2) 0 = S i +} Y 7 X i 7 (i = 0,1, ...... 5) (57), Y ₆ is obtained from equation (44). Similarly, by calculating equations (45) to (49) in the same manner, all Y _i (i = 1, 2,..., 7) are obtained, and (50)
The correction is performed in the same manner as in the equation.

The configuration of the second decoder may be such that the above-mentioned individual arithmetic circuits are connected in cascade, or a set of a multiplication ROM table, an adder, and a division ROM table are provided, and necessary values for each of these are provided. A combination with a control circuit for sequentially inputting and calculating an operation result may be used, but needless to say, it can be realized by software or hardware, like the first decoder.

As described above, according to the present embodiment, the correction of the erasure is realized by calculating the recurrence formula, so that it is possible to correct triple or more errors with very few arithmetic circuits.

In the above embodiment, when obtaining the error pattern Y _j , However, if this value is calculated in advance when checking the pointer, it can be used in common for each row in FIG. 3, so that the total number of calculations can be further reduced.

As is apparent from the above description, the present invention configures the location calculation step to calculate a recurrence formula of a location obtained by a pointer, and further includes the error pattern calculation step as a coefficient of a location polynomial. Since the syndrome recurrence formula is calculated, an excellent effect that multiple errors can be corrected with a very small number of operations can be obtained. Also, a set of multiplication ROM tables,
When realized by software using a combination of an adder, a division ROM table and its control circuit, an excellent effect is obtained in that error correction can be executed at a high speed with a very short operation time. Due to this effect, when this error correction method is used for an inexpensive PCM recorder, an excellent effect is obtained in that the signal after correction does not deteriorate semipermanently in normal use.

[Brief description of the drawings]

1 is a block diagram of an error correction code used in a conventional erasure correction circuit, FIG. 2 is a block diagram of an error correction device using the conventional erasure correction circuit, and FIG. 3 is an embodiment of the present invention. Configuration diagram of an error correction code in an example, FIG.
FIG. 5 is a block diagram of an error correction device using an erasure correction circuit in one embodiment of the present invention. FIG. 5 is a block diagram of a second decoder using the erasure correction circuit in one embodiment of the present invention. FIG. 6 is a block diagram of an erasure correction circuit according to one embodiment of the present invention. 1 ... Data W, 2 ... First check code P, 3 ... Second check code Q, 10 ... Encoder, 11 ... Second encoder, 12 ...
... First encoder, 30 ... Decoder, 31 ... First decoder, 32 ... Second decoder, 321 ... Erasure correction circuit, 3211 ... Location operation circuit, 3212 ... Syndrome Arithmetic circuit, 3213 ... Error pattern arithmetic circuit.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Toshihide Akiyama 1006 Kadoma Kadoma Matsushita Electric Industrial Co., Ltd. (56) References JP-A-58-66159 (JP, A)

Claims (2)

(57) [Claims] An erasure correction method in which the locations of all errors are known, wherein an element on a Galois field GF (2 ^b ) defined by an arbitrary positive integer b, W _i (i = 1,2 , ……, k)
(K: a positive integer) as an information point, and using the primitive element α of the Galois field, An element on the Galois field that satisfies W _j (j = k + 1, k + 2,...)
.., N−k−1) are used as check points in a code having l known error locations (l: positive integer, l ≦ n−).
k), the signal R _i (i = 1,2,..., n) in which the error has occurred is received, and the above-mentioned error is determined by the location X _i (i = 1,2,.
…, L) and the error pattern at each location is Y
_i (i = 1, 2,..., l), and the variable is Z, A location operation step for obtaining an error location polynomial Λ by A syndrome calculation step of determining a syndrome S _i, the recurrence formula An erasure correction method comprising: an error pattern calculation step for obtaining an error pattern Y _i . 2. The location calculation step includes the following recurrence formula: C (1,0) = 1 C (1,1) = X ₁ C (1, −1) = C (i, i + 1) = 0 (i = 1,2,...,
l), C (2, j) = C (1, j−1) X ₂ + C (1, j) (0 ≦ j
≦ 2) C (3, j) = C (2, j−1) X ₃ + C (2, j) (0 ≦ j
≤3) C (l-1, j) = C (l-2, j-1) _Xl-1 + C (l-2, j)
j) (0≤j≤l-1) C (l, j) = C (l-1, j-1) _Xl + C (l-1, j)
(0 ≦ j ≦ l) 2. The erasure correction method according to claim 1, wherein the error location polynomial Λ is expanded by the following formula.