JPS60114036A - Erasure correction circuit - Google Patents

Abstract

PURPOSE:To attain multiplex error correction with less operating amount by constituting a location operating circuit that a location polynomial LAMBDA is expanded. CONSTITUTION:In an error correcting device using a coder 10, th 2nd coder 11, the 1st coder 12, a transmission or recording medium 20, a decoder 30, the 1st decoder 31 and the 2nd decoder using the titled circuit, the 1st code is a (32, 39) read Solomon code on a GF(2<8>) and its generation polynomial is expressed in Equation I . In taking 29 data as W1, W2-W29 and taking ''3'' (32-29=3) of the 1st check code as P1, P2, P3, then they are expressed as Equations I , IIand III. The 1st coder uses the 29 data Wi(i=1, 2...29) so as to calculate A, B, C thereby obtaining Pi(i=1, 2, 3). Since the three check codes are used, the interval between the 1st codes is ''4'' and single error detection correction and >=duplex error detection are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an erasure correction circuit used in an error correction device that can be used for digital data transmission or recording/reproduction.

Conventional configuration and its problems In recent years, P
GM recorders have been developed, but defects and scratches on the recording medium,
Error correction codes are used to correct code errors caused by dust or the like.

A conventional erasure correction circuit will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an error correction code processed by a conventional error correction circuit, where 1 is data W such as an audio signal, 2 is a first check code P, and 3 is a second check code Q. 'l・vortex The first code C1 is 8 pieces of data W in the vertical direction
Alternatively, it is composed of a second check code Q and one first check code P, and this is called one block. The second code C2 is the interleague distance D' in the diagonally lower right direction of the figure.
(=16 blocks), 6 pieces of data W and 2 pieces of data W
It is composed of a check code Q. The first code C1 is a cyclop redundancy check code (aRaa
(abbreviated as ) only performs error detection. The second code C2 is a b-adjacent code, and performs error correction based on the decoding information of the first code (that is, information on whether an error has been detected). 10 is an encoder, 11 is a second encoder, 12 is a first encoder, 20 is a transmission or recording medium, 3o is a decoder, and 31 is a first encoder. a decoder; 32 is an erasure correction circuit;

The operation of the error correction device configured as described above will be described below.

A data string such as a digitized audio signal is inputted to the input terminal of the encoder 10, and is first inputted to the second encoder 11 along with the second check code Q generated by the second encoder 11. They are arranged every D' block in the direction. When 6 data and 2 second check codes are placed in the C2 direction, the next set of 6 data and 2 check codes is placed in the C2 direction from a position shifted one block to the right. Ru. They are arranged in the following categories. Next, the first encoder 11 outputs the data arranged above and the second check code eight by one in the 01 direction of FIG. 1, adds the first check code P, and transmits or records the data and the second check code. Send to medium 2o. When the transmission of the first column is completed, the second and third columns are sequentially transmitted, and this data and check code string form an error correction code in which 246 blocks are called one segment unit.

The data and check code string transmitted or received or reproduced from the recording medium 20 are input to the decoder 3°, and first, the first decoder 31 detects the presence or absence of errors.

This decoded information is sent to the erasure correction circuit 32 together with the data W and the second check code Q as a 1-bit pointer for each column in the 01 direction in FIG. The erasure correction circuit 32 checks the number of pointers to which each data W in the C2 direction and the second check code Q belong, and if it is 0, there is no error, if it is 1 or 2, it performs error correction, and if it is 3 or more, it performs error correction. If so, a flag indicating that correction is not possible is added to each data W, and then the data W is read out in the C2 direction and output through the output terminal of the decoder 30. The output data is again converted into analog data and returned to the original audio signal. Error correction in the erasure correction circuit is performed by the procedure described below.

Now, assuming that the number of pointers is 2, the number of errors is 2, and the location can be obtained by checking at what data point the pointer is set.

Assuming that pointers are now placed on the first and first data, their locations are given by. Therefore, the error location can be requested by reading the pointer and checking whether its value is 0 or 1.

Next, the syndrome is calculated according to the following formula.

Si-Σ C1 (j-+) R.

j==,t (i=ot 1.?+++n-k') (2) However, R4 is the received word. In this conventional example, the n-8°k=6° second check code Q is set so as to satisfy the following equation: Σ tti (j −1) yi=.

j=+ (i=ot 1,2...-n-to-1) (3)
A received word R1, R1 containing an error causes an error slam at that location! , Y2, then the value of the syndrome obtained from equation (b) is (i=0.1-.-n-1) (6). This is it, error slam! ,,If you set Y2, it will stop. Once the error bump is cleared, correction is performed according to equation (4) as follows.

However, the above configuration has a serious problem in that if the number of errors in the C2 direction exceeds three, the errors cannot be corrected.

Furthermore, the code is extended to increase the number of second check codes, and 3
If it is possible to correct more than 1 errors, the amount of calculation in equation (6) to solve equation (6) and find the error stamp Yl increases rapidly as the number of errors i increases, making it practically unfeasible. It also had the problem of becoming.

OBJECTS OF THE INVENTION An object of the present invention is to provide an erasure correction circuit that can correct more than three errors with a very small amount of calculation.

4. Structure of the Invention The erasure correction circuit of the present invention is based on an element Wi (i=1.2
...k) (k: positive integer) is an information point, and using the primitive element α of the Galois field above, calculate the element Wj on the Galois field that satisfies (n: a positive integer, n>k) (] := k +1
+k+2......N-1) is the check point for a code configured to have a known error location of 1.
A signal Ji in which (l: positive integer, 1<n-k) errors have occurred
Receive jR4 (i = 1 + 2 . . group - n ),
” Xi is the location of the error mentioned above (i = 1.2, old...
A location arithmetic circuit that calculates the Scherrer location polynomial A as (i=1.2...l), and (1=0,1,2...n-1) ( 1o) and the following recurrence formula, Si2. = S + Y, X branch (i = Q, 1.2- = -n- to -2) (Xi
-+) Si, 2"sl, + +"t-+"t-1
(i=:0.112−−−−−・n−−3) It is constructed with an error button operator X circuit that generates the error button Y1. Point W
Even if the number of j's (-1 to n-) increases, many errors can be corrected with a small number of arithmetic circuits. Furthermore, the location calculation circuit is defined by the following recurrence formula, /(:/7 (1+X1Z) 1=1 2,...l), and C(21j)=c (1t j-1 ) X20G (1
,j) (0≦ko≦2) C(3,j) =C(2,j-1) X3+O(2,j
) (0≦j≦3) Ci (A-L j) = C (7I-2, j 1) x
t-+ 10C(4+-2,j)(o≦ko≦l-1)C(
7! , co)=C(A-1, co1) x,, -1-c
(A-1+j) (o≦ko≦7, A=Σ C (island j), zj co0) By using a configuration that expands the location polynomial A, multiple error correction is possible with a much smaller amount of calculations. It is something.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a configuration diagram of an error correction code used in an error correction device using an erasure correction circuit in an embodiment of the present invention. In FIG. 3, 1 is the theta W12 is the first check code P, 3 is the second check code Q, and the first code C1 is a Reed-Solomon code (in the case of this embodiment, n = 32, k: 29), in an array perpendicular to the first code C1 in the horizontal direction of the second code 0214, and m pieces of data for each interleaving distance D (D-4 in the case of this example). W or second check code Q
This constitutes a (m+h) Reed-Solomon code (in the case of this embodiment, m:32.n=2s).

FIG. 4 is a block diagram of an error correction device using an erasure correction circuit according to an embodiment of the present invention, in which 1o is an encoder, 11 is a second encoder, 12 is a first encoder, 2
o is a transmission or recording medium, 30 is a decoder, 31 is a first decoder, 32 is a second decoder using an erasure correction circuit, and the error correction unit of this embodiment is configured as above in item 9. The operation of the device will be explained below. Since the signal flow is the same as in the conventional example, the differences from the conventional example will be explained here. In the case of this example, the first code is CF'(28
) is the above (32,29) Reed-Solomon code, and its generating polynomial is given by the following equation.

G(X)=(X-1XX-aXl-α2)GF (28
M(13) Here α is the modulus polynomial q (X)oGF(
28) It is the upper root. For example, the following equation may be used as the modulus polynomial q(X).

q (X) =X8+X4+X3+X2+1GF (2
) (14) 29 pieces of data W,, W2 = W22
．． 32-29 = 3 first check codes “lP2 P3
Then, the parity check determinant that the first code should satisfy is given by the following equation ("-iA+a58(1+α)(1+a')).The first encoder generates 29 pieces of data Wi(i= 1
, 2...29) to calculate Mu, B, and C.
Set Pl (i=1.2.3). It is well known to those skilled in the art that the first encoder that performs this calculation can be implemented as software using a computer program, or as hardware using a logic circuit, so a detailed explanation will be omitted.

The first code has 3 check codes, so the inter-code distance is 4.
Therefore, single error detection and correction and double or more error detection are possible. Generally, the intersymbol distance is d.

When the number of correctable errors is t, 2t+1≦d holds true.

Therefore, the first decoder performs one true/false correction, and sets a pointer when detecting two or more errors. This error detection/correction process is as follows.

The received or reproduced first code is processed by W(i:= 1 +2
...32). For convenience, no distinction is made between data and check codes.

First, let's look at syndrome 51 (i20, 1.2).

2 An error has now occurred on the word Wi on the first day. !
:l'L, its error pattern Yl s If αi-+, which represents the location, is represented by xi, then the received word Ri
is expressed by the following equation.

R1= Wi + Yi (20) Also, since the value of the syndrome satisfies equation (3), (S2
It is expressed as =Y1x, lolQ'. Therefore, the first decoding fixture C, So, S,
.

S2 is calculated, the occurrence of an error is detected from the fact that each value is not 0, and is checked to determine whether it is a single error. (22)
If there is an i that satisfies the formula, it is determined that there is a − double error, and (21)
The i-th error obtained by the first equation? Error correction is completed by adding 1=I-1 to the received word R4.

Wl=R1+YL (23) If l that satisfies equation (22) does not exist, it is determined that there is a double or more error, a pointer is generated, and it is sent to the memory in the second decoding fixture.

The configuration of the first decoder that implements the above-described error detection and correction process is well known to those skilled in the art, as is the case with the first encoder, and detailed description thereof will be omitted. Further, details are described in, for example, "Coding Theory" by Imai et al., Shokodo, 1975.

In this example, the second code is (32
, 25) Since it is an R8 code and its inter-code distance is 8, it is possible to detect and correct triple errors when used alone.
If the position of the error is known using a pointer or the like, sevenfold correction is possible. Generally, error correction when the location is known is called erasure correction, and if the inter-symbol distance is d and the number of errors that can be erased is e, then 6+1 d holds true.

It is also possible to combine erasure correction with single error detection/correction (abbreviated as error correction), and in that case, 2 t -1-6+1 l d (24) holds true.

Similar to the first encoder, the second encoder generates a second check code Qe (i=1.2...7) that satisfies the following equation.

FIG. 6 is a block diagram of a second decoder using an erasure correction circuit according to an embodiment of the present invention, and 321 is an erasure correction circuit according to an embodiment of the present invention;
2 is an erasure error correction circuit, and 323 is an error correction circuit.The operation of the second decoder of this embodiment, which is configured as above, will be described below.

The second decoder 32 performs the following correction based on the 11,1 case of this embodiment and the number p of pointers.

(1) When p=o or ≧8 2. Correct the error.

(2) When 1 l p l-e Performs 5 erasure + 1 error correction.

(3) When p = 7 Perform file correction.

There is one pointer for each column in Figure 3, and the first
From the point of view of the second code, which is orthogonal to the code, the pointer is common to the second code for each row. Therefore, calculations related to the pointer and location can be calculated once and used in common for each row, so the number of calculations can be reduced. is possible.

(1) 2 Error Correction When the second decoder 32 determines that the number of pointers is 0 or 8 or more, it sends data to the error correction circuit 323 and performs correction according to the procedure shown below.

First, syndrome Sj (j ”Or '1...6
).

2 The two error patterns are Y4. When Y2 and location are respectively 'x, , x2, the syndrome is expressed by the following equation.

If the location polynomial with the error location as its root is, then the coefficient σ1. Since the following relationship holds between σ2 and syndrome 3j, if the value of the denominator in equation (29) is not 0, σ and σ2 are equal. If 0, 714 with triple or more
'), a flag is set, and the correction operation ends. σ1. σ
2, then find the root of equation 20 in (13) to find the location.

2=σ,mu (30) Then, A'+A=σ27/sum2(31) Since A that satisfies the formula (31) is uniquely determined, σ2/62
By predetermining the value of mu according to the value of and having this as a root table, it is possible to use a person to find the root using equation (30).

If the location is empty, the error will be canceled.

(b)) 6 erasure + 1 error correction second decoder 3
2, if the number of pointers is 1 or more and less than -16, the data is sent to the erasure error correction circuit 322, and error correction is performed according to the procedure described below.

First, find the erasure location polynomial A. The location of the error can be determined by the number of words where the pointer is placed.For example, if the pointer is placed on the word number, then the location is obtained as X=, -1.

Assuming that there are 6 pointers now, 6 locations X1 (1-1+2+...5)
Then, the location polynomial A of the erasure is divided as follows. On the other hand, it is assumed that the error parity at each location is Y(i, = l, 2. . . . 5).

Since equation (33) is a sixth order equation of 2, it is expanded as follows and each coefficient C(it j) (i==1.2...L
j ``Or''......Fill out i).

0 (i, -1) :=C(i, i+1) =C(i
−1°2...b).

Then, equation (33) becomes (35). Next, C(21j) = C(1+ j-1)X2+G (1,
j) (0≦j≦2) (36) Equation (36) becomes (3η). Next, c (3, j) = C (21j-1) xs + C (2
1j) (O≦j≦3) (38) When calculating, equation (37) becomes. Similarly, C(i, j) = C(i-1, j-1) X knee 4-
Cj (i-1, ko) (40) (i=1.2...
...B, i=o, 1...i), A-Σ C(5,j) Zj (41)j-=.

Then, A can be measured.

Next, if we set the location of the error to be detected and corrected as x6 and the pattern as Y6, we get syndrome 8j.
(j=o, 1...6) is, so by removing this, the location is expressed as (43), so the coefficient 0 (6, 3) obtained by expanding the location polynomial above is It can be easily fixed using the Syndrome S technique.

When the denominator of equation (43) is 20, from equation (42), x6−
The result is OY6-0, and it is determined that there is a 6-fold error.

When the denominator is so, if X6-αk (0≦≦31) that satisfies equation (43) exists, it is the sixth location to be disturbed; if it does not exist, it is determined that it cannot be corrected and the flag is set. stand up

If the number of pointers is 6, it can be determined whether or not correction is possible by checking whether the value determined by equation (43) matches the location requested by the sixth pointer. If they do not match, it cannot be corrected.

If the number of pointers is 4 or less, the value of xl that exceeds the number of pointers may be set to 0 in equations (33) and after.

Once the location is found, the value of the error pattern is calculated by solving equation (42) and calculating (44). Next, “l” si
r.

8j, 1 ”: syu, g 10Y6X4 (i =
By substituting =Q, 1--5) (46), Y5 can be calculated as (46). The following types include Si, y-t
= syu, 6-t + Yt xt' (i=o+1
-・・・4-1) (1=e, 5-2) (47
), and finally calculate JY+ by ``+ = So, a + Y2 (49)
If you fill it out, all Y-works will be circled.

If the number of pointers is 4 or less, the value of Y, which is greater than or equal to the number of pointers, may be set to O.

That's all, once the error pattern is found, the correction is as follows:
Ri + Y (i: 1.2...6) (5
0).

(3) Eraser correction When the number of pointers is 7, the second decoder 32 sends the data to the Earser correction circuit 321 and performs correction according to the procedure described below.

FIG. 6 is a block diagram of an erasure correction circuit according to an embodiment of the present invention, in which 3211 is a location calculation circuit, 3212 is a syndrome calculation circuit, and 3213 is an error pattern calculation circuit.

The operation of the erasure correction circuit in one embodiment of the present invention constructed as described above will be explained below.

First, a location polynomial A is determined in the location calculation circuit 3211.

i=1 The expansion of the above equation is done in the same way as in the case of Kan) to obtain the following equation.

Furthermore, c (6, i) = C(s, 1-1) X6+-C(
By calculating s, =-1) (63), -0 and l can be expanded.

Next, the syndrome 1 drome calculation circuit 3212 calculates the equation (26) and calculates the syndrome Sj (j:o, 1...
・Fill in 6).

On the other hand, the syndrome is the erasure location Xi
and Batan Yi can be expressed as follows.

S] = Σylxfl (j2Q1...6)
(66) Substituting the Sheller pattern Y7, the following equation is obtained.

The error pattern calculation circuit 3213 calculates equation (66) to find Y7. When Y7 is full, S work is done in the same way as in (2). = S, + Y, X17 (i=o, 1.-
---ts) (57) Yo! llS,,. Then, Y6 can be determined from equation (44). By similarly calculating equations (45) to (49), all Yi (i=1,2°...
7) Correction is performed in the same manner as in equation (50).

It goes without saying that the configuration of the second decoder can be realized by software or hardware similarly to the first decoder.

As described above, according to the present embodiment, since erasure correction is realized by calculating a recurrence formula, it is possible to correct triple or more errors with a very small number of calculations.

In the above embodiment, the error pattern Y is used, but if this value is calculated in advance when checking the pointer, it can be used in common for each row in Figure 3, so the overall number of operations can be further reduced. I can do it.

Effects of the Invention As is clear from the above explanation, the present invention configures a location calculation circuit to calculate a recurrence formula of a location obtained by a pointer, and an error button calculation circuit to calculate a recurrence formula of a location obtained by a pointer. Since the system is configured to calculate a syndrome recurrence formula, an excellent effect can be obtained in that multiple errors can be corrected with a very small number of calculations. Due to its effectiveness, this error correction device can be used as a PGM.
When used in a recorder, an excellent effect can be obtained in that the deterioration of the corrected signal does not occur semi-permanently under normal usage conditions.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an error correction code used in a conventional erasure correction circuit, Fig. 2 is a block diagram of an error correction device using the same conventional erasure correction circuit, and Fig. 3 is a block diagram of an error correction device according to the present invention. A configuration diagram of an error correction code in an embodiment of
5 is a block diagram of an error correction device using an erasure correction circuit according to an embodiment of the present invention, FIG. 5 is a block diagram of a second decoder using an erasure correction circuit according to an embodiment of the present invention, and FIG. FIG. 6 is a block diagram of an erasure correction circuit in one embodiment of the present invention. 1... Data W, 2... First check code P, 3... Second check code Q, 10...
Encoder, 11... Second encoding, 12...
. . . first encoder, 30 . . . decoder, 31
...First decoder, 32... Music second decoder, 321... Erasure correction circuit, 3211...
...Location calculation circuit, 3212...
・Syndrome calculation circuit, 3213・Old...Error slam calculation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure No. 51!1 3? No.61!1. 32/

Claims (1)

[Claims] (1) Galois field GF (2b
), Wl (i=1.2...k:) (
k: positive integer) is the information point, and using the primitive element α of the 2-di-Ga1fa field, the element on the above Galois field that satisfies (n: positive integer / n)k), W, (j- +1°k+2
......A signal R in which two errors (l: positive integer, 1≦n-k) with known error locations occur in a code configured to have n- to -1) as the test point. D (i=1
．． 2...n), set the location of the above error as Xi (i:11 2...l), and set the error number at each location as Yl(i=1,2...l).
...β), a location arithmetic circuit that takes the Scheler location polynomial A, a syndrome arithmetic circuit that takes the syndrome Si, and the following recurrence formula, Si, 1= Si + “z xl ”i, 2=Si, + +Yt-+ Xt-1 (1==
Q, 1 t 2+++・++ n- to 3) Y2::
ΣG (1,'l) 5t-i,l-2/ (X+
10X2) Knee O Yi ” S[1, t-2+ Y2 Error group: y Yi This is an erasure correction circuit characterized by being configured with an error slam calculation circuit. As the recurrence formula, 1#2...l), C(2,j) ``C(IF j-1) ''2+c(1+
j) (0≦j≦2) C (31j) =Cj (21co-1) x3+c (
2, j) (0≦j≦3) OCI L ]) = C (J 2+ j 1) xz−
1+0 (1-2+ j) (0≦j≦l-1) C(lt)) = C(J-1t) 1) Xt+
c (jj−1゜j) (0≦j≦l) Δ=Σ CCI, j) Zl j=. 2. The erasure correction circuit according to claim 1, wherein the erasure correction circuit expands a location polynomial A. ′