JPS60176340A - Data processor - Google Patents

Abstract

PURPOSE:To reduce an error due to round-up and round-down and to obtain output data approximating an original signal by rounding up or off fractions of the operation results of an operating circuit in an average value circuit in accordance with secondary differential characteristics of the original analog signal. CONSTITUTION:Binary data 1a-1d are added to 4-bit data from a latch circuit 4 by a full adding circuit 16 and are outputted as 5-bit data including carry. In this case, if an analog signal is projected upward at, for example, a timing t3, the MSB of the output of a full adding circuit 24 is ''1'', and fractions of upper 4 bits of the full adding circuit 16 are rounded up, and upper 4 bits are outputted. If the analog signal is projected downward, the MSB of the output of the full adding circuit 24 is ''0'', and fractions are rounded off, and upper 4 bits are outputted from the full adding circuit 16.

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a data processing device, particularly a data processing device that processes data obtained by sampling a temporally continuous analog signal such as an audio signal or a video signal, after passing it through a transmission system such as a recording/reproducing system. It relates to a processing device.

<Description of Prior Art> Generally, unreliable data may occur in data transmitted through a transmission system. In such cases, it is common to replace the unreliable data with newly generated data.

For example, when unreliable data occurs in data obtained by sampling an audio signal, a method has been used in which the data is replaced with interpolated data obtained using data before and after the data. The methods include the pre-hold method, in which the data immediately before the low reliability data is used as interpolation data, the average value interpolation method, in which the average value of the data immediately before and after the low reliability data is used as the interpolation data, and the low reliability data. A cubic interpolation method that uses interpolated data obtained from data (at least four) in the vicinity of sexual data is known.

In terms of the degree of approximation of such interpolated data to the original signal data, the previous value hold method is the worst, followed by the average value interpolation method and the cubic interpolation method, which are better in that order, but the scale of the hardware has also increased accordingly. Put it away. Therefore, they are used depending on the type of information signal processed by the data processing circuit and the scale of the device.

FIG. 1 is a diagram showing an example of a schematic configuration of a conventional general data processing device that replaces low reliability data using an average value interpolation method. In FIG. 1, 2 and 4 are latch circuits that delay transmitted data by one sampling period.

Reference numeral 6 denotes an average value calculation circuit, which calculates and outputs the input data of the latch circuit 2 and the output data of the latch circuit 4. 8
is a data selector, which selectively outputs the output data of the latch circuit 2 and the output data of the average value calculation circuit 6.

10 is an input terminal for a timing clock, 12 is an input terminal for a well-known error detection signal, and 14 is a latch circuit for delaying the error detection signal by one sampling period. As is well known, the error detection signal is obtained by checking the parity word or CRCC, and for example, the latch circuit 2
When the data being input to is low reliability data, "o" is input from terminal 12; when it is high reliability data, "o" is input from terminal 12. Furthermore, when the output from the latch circuit 14 is 1'', the data selector 8 is connected to the average value calculation circuit 6.
When the output data is 0'', the output data of the latch circuit 2 is output.

Now, if the reliability of the output data of the latch circuit 2 is high, the output of the launch circuit 14 is "0", and the data selector 1
4 outputs the output data of the latch circuit 2 as is. On the other hand, if the reliability of the output data of the latch circuit 2 is low, the output of the latch circuit 14 becomes 1, so that the output data of the average value calculation circuit 6 is outputted from the data selector.

Since the output data of the average value calculation circuit 6 is the average value of the data immediately before and after the output data of the latch circuit 2, average value interpolation has been performed.

Here, the average value calculation circuit 6 is composed of, for example, a full adder circuit and a 1/2 multiplier using a 1-bit shift. In this case 1
If the least significant bit of the input data of the /2 multiplier is 1, the output data of the average value calculation circuit 6 will inevitably be data obtained by rounding down the calculation result.

This will be explained in more detail below. Assuming that the current data is 4 bits, the data (A data) immediately before the low reliability data (B data) is 1101 (2+1), and the data immediately after 1 (C data) is 1001 (2). If you add human numbers, you get A + Cfloro (21), and by shifting the focus one point lower, you get 1011 (21). This is 13 + 9 in decimal notation, and -9 = 11, which means that you have obtained the correct average value data. But now the A data is 1101 (2).

If C data is 1000 (2), A + Cf
After obtaining 10101 (2) '<, we obtain 1010 (2) as the average value data, which is + when considered in decimal notation.
3+8-10, which means that correct average value data is not obtained because the fraction of the calculation result is rounded down.

In other words, the average value data is not obtained correctly) 1/
With a probability of 2, data smaller by 05 in decimal number will be output.

However, since the analog original signal varies in whether it is larger or smaller than the average value data, the output data may have a large error with respect to the analog original signal due to this rounding down.

Furthermore, unnatural frequency components may be generated. This also applies to the configuration in which fractions are rounded up.

Also, in conventional data processing devices other than the above-mentioned configuration, when obtaining interpolated data by calculation, rounding up or down greatly impairs the approximation of the output data to the original signal and generates unnatural high frequency components. There were times when I ended up doing this.

;Object of the Invention> In view of the above-mentioned drawbacks, the present invention has been designed to reduce the original output data by rounding up or down the calculation result when replacing low reliability data with new interpolation data obtained by calculation of data before and after the data. It is an object of the present invention to provide a data processing device capable of preventing loss of approximation to a signal and obtaining output data close to the original signal.

<Explanation based on examples> The present invention will be explained below using examples.

The following explanation will be made assuming that the analog signal is transmitted as 4-bit digital data. - Also, 28 conbriment is generally used in the binary system when converting audio and video signals into binarized signals. This is often used because the value corresponding to data in which all pits are 0'lJ or all pits are 1'' is around O, which tends to occur when a system abnormality occurs. Since the above-mentioned % multiplier by 1-bit shift is included, we will explain that we will be handling binary data by 6th offset binary.We still need to convert the 28-combined data to offset binary data and process it. You may consider it a thing.

FIG. 2 is a diagram showing the main part configuration of a data processing device as an embodiment of the present invention. Components in FIG. 2 that are the same as those in FIG. 1 are given the same numbers and their explanations will be omitted. Furthermore, in the configuration of FIG. 2, it is assumed that J low-reliability data are generated independently for ease of explanation. 01a, lb.

1c and Id are terminals into which binary data is input, respectively.
The data input from these terminals is transmitted through the transmission system.
Input as bit data. 16 is a full adder circuit which adds the 4-bit data supplied to terminals 1a-i-d and the 4-bit data output from the latch circuit 4, and outputs the result as 5-bit data including carry. By outputting the upper 4 bits of data including the carry out of this 5-bit data, data obtained by rounding down the average value of the output data of the latch circuit 4 can be obtained as described above. 18 is a latch circuit that delays the output of the latch circuit 4 by l sample period and outputs it; 2'0.22 is a subtraction circuit; 23 is a doubling circuit that doubles the input data and outputs it; 24 is a full adder circuit. , 30, 32, and 34 are inverters, respectively.

Next, before explaining the operation of each part according to the above-described configuration, the principle of the present invention will be briefly explained.

FIGS. 3(A) and 3(B) are diagrams for explaining the present invention. In FIGS. 3(A) and 3(B), dotted lines indicate analog original signals, ○ indicates highly reliable data, and Δ and × indicate interpolated data, respectively. Also 1,, 12.1. .

t4 indicates the sampling timing, and t
It is assumed that the data transmitted at the time of , has low reliability.

As shown in Figure 3 (A), <1. If the analog original signal is convex upward at the timing of , the analog original signal is at a relatively large level when the second derivative value is negative, so it is desirable to round up the calculation result to obtain interpolated data. .

On the other hand, if the analog original signal is convex downward at the timing < tx as shown in FIG. 3(B), it is desirable to obtain interpolated data by rounding down the fraction of the calculation result.

Next, an example of a method for determining whether a second-order differential value is positive or negative will be described. Now 1. , 17. Let the respective data values at t4 and t4 be d, dt, d. If the second-order differential value is old, it means that the slope of the signal increases as time passes, so the average slope from t to t2 and t2
What is necessary is to compare the average slope between t4 and t4. In other words, all you have to do is compare (dt-dl)/T (T indicates l sampling period) and (d4+d2)/2T, and (
When cL - dz )+ 2 (, d+' dt) is positive, it is convex downward, and when it is negative, it is convex upward. Still T than t4
When using the data (d,) at t, which is delayed by do it.

The operation of each part of the apparatus shown in FIG. 2 will be explained below using specific data. In addition, in this embodiment, the terminal 1a-
The data input to id is a sampled analog signal (for example, an audio signal) that occurs at approximately the same amplitude and at the same rate from the 0 level, and the quantization is linear 4.
It is assumed that there are 16 levels from -8 to +7.

If the double decimal theta is -8, then 0000f21.0
If it is, then it is 100012+, and if it is +7, it is 111N2+.

First, according to Figure 3 (A), d is 1000 + 21 (0)
, d, is 1011121 (+3), d4 is 111
Assume that Of2+ (+6). At this time, terminal 1
If dl is input to a to 1d, d2 is output from the latch circuit 2, and d4 is output from the latch circuit 18. At this time, since the output of the latch circuit 14 is at the noise level, the data selector 8 outputs the upper 4 bits of the output of the full adder circuit 16, that is, (d2 + d4)/2.

On the other hand, the plus input of the subtraction circuit 20 is d4, and the minus input is d2, but the most significant bit data (MSB) is inverted by inverters 30 and 32 before being input. This is because the calculation by the subtraction circuit is performed using 2's conjoint data, and each inverter 30, 32.3
4 serve to convert data based on offset binary into data based on 2S conjoint.

Therefore, dl input to the subtraction circuit 20.22 is 0000.
+2+, d, is 0011i2+, d4 is 0110t
It will be 21.

Therefore, the output data (d4-d2) of the subtraction circuit 20 is 0.
011t2+ (-3), the output data of the subtraction circuit 22 (d.

-d2) becomes 11ON2+. The output data (ti, -d,) of the subtraction circuit 22 is doubled by the doubling circuit 23 and becomes 101
012+, and the output data of the subtraction circuit 20 is 0011.
+21 and is added by the full adder circuit 24 to output 1101+2
Get +. The output of the full adder circuit 24 is (d44) +
2 (d+'t), and as described above, by distinguishing whether this data is positive or negative, the unevenness (second-order differential feature) of the signal can be determined. The data by 2's combination is its MSB.
is negative when it is '1', and positive when it is '0''. Therefore, since this MSB is 1'', it is sufficient to round up the value of (d4+a4)/2.

The full adder circuit 16 calculates d, (1
01N2+) and d4 (1110(2)) are added, and the MSB "1" of the output of the aforementioned full adder circuit 24 is input as a carry-in, and the output becomes 11010f2+. Therefore, if these upper 4 bits are taken as average value data, it becomes l 10 j+21 (+5), which means that the fraction is rounded up. Therefore, with this data, the output data (indicated by Δ in FIG. 3(A)) is approximated to the original analog signal waveform. The data indicated by x in FIG. 3(A) is output data when fractions are rounded down.

Next, according to FIG. 3(B), dl is 0111121 (-
1), d, Ka1000+21 (0), d4 is 110
Assume that N2+ (+5). At this time, the output of the subtraction circuit 2o is 0 101 due to 28 conbriment.
+21 + Also, the output of the subtraction circuit 22 is 1111+a,
The output of the doubling circuit 23 is 1110121, and the output of the full adder circuit 24 is 0011+21. Therefore, since the MSB of the full adder circuit 24 is "0", the full adder circuit 16
The carry-in of is "0". In the full adder circuit 16, the offset binary is d4 (1101+21) and d
.

(1,000f21) is added, and the output is 1' 01
0 N2+ is obtained. And this upper 4 bits 1010+
Since we get +2 from 2+, the fraction has been rounded down. Therefore, this output data (indicated by Δ in Figure 3 (B))
is when the fraction is rounded up (indicated by × in Figure 3 (B))
Compared to , Haru is approximated to the Anehara analog signal waveform.

As mentioned above, according to the configuration shown in the N2 diagram, the fraction of the calculation result of the average value circuit is rounded up or down according to the second-order differential characteristics of the original analog signal, so especially when the quantization is coarse, the output data By rounding up or down, the error from the original analog signal does not increase, but rather output data that approximates the original analog signal can be obtained.

Next, a case will be explained using FIG. 4 in which the case where two or more pieces of unreliable data occur consecutively is also taken into consideration.

FIG. 4 is a diagram showing a narrow section configuration of a data processing device as another embodiment of the present invention. Components in FIG. 4 that are the same as those in FIG. 2 are given the same numbers and their explanations are omitted.
42 and 44 are data selectors, respectively.

Further, FIG. 5 is a timing chart showing the states of each part of the fJ4 diagram, and the operation will be explained below using FIG. 5.

The DATA-IN part in Fig. 4 has the DATA-IN part in Fig. 5.
As shown in IN, Do, Di, D2...Di9.
When D20 appears in the order, it indicates that the data input through DATA-IN has low reliability. Therefore, D4.
D7. Do, D10, and DI3 to D18 each have low reliability.

Now, when the output of the latch circuit 14 is 0'', the data output from the latch circuit 2 has high reliability.

At this time, the outputs of the AND gates 38 and 40 are at a low level, and the data selectors 42 and 44 respectively select and output the data supplied to the lower side in the figure. Therefore, at this time, the output of the latch circuit 14 becomes DATA-OUT and is supplied to the latch circuit 4 as is.

On the other hand, when the output of the latch circuit 14 is "1", the output data of the latch circuit 2 is low reliability data, so it is directly sent to DATA-OU via the data selectors 42 and 44.
It cannot be T. Therefore, it is necessary to replace it with some kind of interpolated data. This can be replaced with highly reliable data that occurred in the past closest in time (holding the previous value), or replaced with data that indicates the average value of that highly reliable data and the immediately following highly reliable data (average This is done by interpolating values).

This is determined by the reliability of the data immediately following the low reliability data. That is, since average value interpolation is possible if the immediately following data has high reliability, it is replaced with average value data obtained as described above from the upper 4 bits of the output data of the full adder circuit 16. In this case, the output of the AND gate 38 becomes high level, and the data selector 42 outputs the data input to the H side in the figure (i.e., the upper bits of the output data of the full adder circuit 16), which is input to the data selector 44. It becomes DATA-OUT via the L side. D4 (D3+
The part replaced with D5)/2, D7 is replaced with (D6+D8)
This corresponds to the part replaced with /2.

- If the immediately following data has low reliability, it is impossible to perform average value interpolation, so the data output immediately before is output again.

At this time, the output of the AND gate 40 becomes high level, and the data selector 44 outputs the data that was output immediately before, delayed by one sample period by the latch circuit 4. The output data of this data selector 44 is set as DATA OUT and is again supplied to the latch circuit 4. Do to D8
This corresponds to the part where D13 to D17 are replaced with 012.

When several pieces of low-reliability data are consecutive in history, when the last low-reliability data is output from the latch circuit 2, the output of the AND gate 38 is at a high level, as is clear from the above explanation, and the AND Since the output of the gate 40 is at a low level, the upper 4 bits of the output of the full adder circuit 16 are outputted to DATA OUT. This full adder circuit uses the previous value hold data output from the latch circuit 4, that is, highly reliable data generated in the most recent past, and the DATA-I
The average value data with the high reliability data input to N is replaced with DATA-OUT by (D8+D11)/2, and Di8 is replaced with (D8+D11)/2.
This corresponds to the part substituted with D12+DI'9)/2.

It should be noted that the output data of the full adder circuit 24 is such that when it is an original analog signal, the original analog signal is convex downward, and when it is a prize, it is convex upward. Since the output of the full adder circuit 24 is data based on 2'B congruence, by supplying the MSB to the full adder circuit 16, the average value calculation result is similarly rounded up or down.

It goes without saying that even in the configuration as described above, data that is similar to the original analog signal can be obtained even if coarse quantization is performed.

Although the above explanation uses offset binary 4-bit data, the present invention is applicable regardless of the type of data and the number of quantizations. In addition, as a calculation means for obtaining interpolated data, only the average value calculation has been explained, but the present invention can also be applied when rounding up or down the calculation result in the case of the cubic interpolation method. > As explained above, according to the present invention, in addition to replacing low-reliability data with interpolated data according to the calculation output of the data before and after it, the calculation is performed so that the output data is more similar to the original signal. Rounding up the result yields a data processing device capable of rounding down.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration example of a conventional general data processing device, FIG. 2 is a diagram showing a main part configuration of a data processing device as an embodiment of the present invention, and FIG. ) is a diagram for explaining data replacement by the device of the present invention, FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention, and FIG. 5 is a timing chart showing waveforms. 2, '4, 14 and 18 are latch circuits, 8°4
2 is a data selector included in the replacement means, 16 is a full adder circuit included in the arithmetic means, 020 is a subtracter circuit, 23 is a doubling circuit, and 24 is a full adder circuit, which are included in the discriminator. It will be done. Applicant Canon Co., Ltd.

Claims (1)

[Claims] A device for processing data obtained by sampling a temporally continuous analog signal after transmission, the device comprising: means for calculating data before and after low reliability data; means for determining second-order differential characteristics of a signal waveform; means for generating new data by selectively rounding up or rounding down the calculation result according to the determining means; and means for replacing the low reliability data.