JPS60165136A - Data processor - Google Patents

Abstract

PURPOSE:To obtain an output data having a property close to that of an original signal by operating a data before and after a low reliability data and attaining alternatively the alternate round-off and cutoff in the same rate for the result of calculation at each generation of the low reliability data so as to generate a new data. CONSTITUTION:An output of a latch circuit 14 is shown in Fig. (b) and when the level is logical 1, an output data of a latch circuit 2 is a low reliability data. When an input of a full adder circuit 16 is 1011(2)(+3) and 0110(2)(-2), the output of the full adder circuit is 10001(2) when the carry-in is logical 0 and 10010(2) when the output is logical 1. Thus, the data fed to a data selector 8 is respectively 1000(2)(0) and 1001(2)(+1). If a fraction is produced when two inputs are calculated to the full adder circuit 16, that is, when the least significant bit (LSB) of the output data of the full adder circuit 16 is logical 1, the full adder circuit 16 acts like an average value arithmetic circuit rounding off the fraction by the carry-in or acts like an average value arithmetic circuit cutting off the fraction. Then the replaced interpolated data is alternately the rounded-off data just before and after and the cut-off data alternately.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a data processing device, in particular, to a data processing device that processes data obtained by sampling a temporally continuous analog signal such as an audio signal or a video signal through a transmission system such as a recording/reproducing thread. It relates to a processing device.

(Description of Prior Art) In general, data with low reliability may occur in data transmitted through a transmission system. In such cases, it is common to replace the low reliability data with newly generated data.

For example, when low reliability data occurs in data obtained by sampling an audio signal, a method has been used in which the data is replaced with interpolated data obtained using data before and after the data. The methods include the pre-hold method, in which the data immediately before the low-reliability data is used as interpolation data, the average value interpolation method, in which the average value of the data immediately before and after the low-reliability data is used as the interpolated data, and the low-reliability data. A sixth-order interpolation method is known that uses complementary data obtained from data (at least four) in the vicinity of degree data.

Regarding the degree of approximation of such interpolated data to the original signal data, the previous value hold method is the best, followed by the average value interpolation method and the 6th order interpolation method, but the scale of the hardware also increases accordingly. I end up. Therefore, they are used depending on the type of information signal processed by the data processing circuit and the scale of the device.

FIG. 1 is a diagram showing an example of a general configuration of a conventional general data processing device that performs replacement of low reliability data using an average value interpolation method. In FIG. 1, 2 and 4 are latch circuits that delay transmitted data by one sampling period.

Reference numeral 6 denotes an average value calculation circuit, which calculates and outputs the input data of the latch circuit 2 and the output data of the latch circuit 4. 8
is a data selector, which selectively outputs the output data of the latch circuit 2 and the output data of the average value calculation circuit 6.

10 is an input terminal for a timing clock, 12 is an input terminal for a well-known error detection signal, and 14 is a latch circuit for delaying the error detection signal by one sampling period. As is well known, the error detection signal is obtained by checking the parity word or CRCC, and for example, the latch circuit 2
11' is input from the terminal 12 when the data being input to is low reliability data, and '0'' is input from the terminal 12 when the data is high reliability data. When the output from 14 is ``1'', the output data of the circuit 6 is outputted to the average value calculation, and when the output is IO'', the output data of the latch circuit 2 is outputted.

If the reliability of the output data of the launch circuit 2 is high, the output of the latch circuit 14 is '0', and the data selector 14
outputs the output data of the latch circuit 2 as is. On the other hand, if the reliability of the output data of the latch circuit 2 is low, the output of the latch circuit 14 becomes 1'', so the output data of the average value calculation circuit B is outputted from the data selector.This average value calculation circuit Since the output data of B is the average value of the data after the output data of the latch circuit 2 +>ij W, it means that average value interpolation has been performed.

Here, the average value calculation circuit 6 is constituted by, for example, a full adder circuit and a 1/2+\i unit by 1-bit shift.

In this case, the least significant bit of the input data of the 1/2 multiplier is 1″
If so, the output data of the average value calculation circuit 6 will necessarily be data obtained by rounding down the calculation result.

This will be explained in more detail below. If the current data is 4 bits, the data immediately before the low reliability data (B data) (A data) is 1101 (2), and the data immediately after (
When C data) is set to 1101(2), if you lower it using the method described above, it becomes 10110(2) in Ago, and by shifting 1 bit lower, you get -('1011(2). This is in decimal notation. Thinking about it, it becomes 4-11, which means that the correct average value data has been obtained.

However, now the A data is 1101 (2) and the C data is 100.
Assuming C(2), 8 → () is 101 D 1 (2)
After that, we obtain 101 [Cz) as the average value data, but if we think about it in decimal notation, it becomes 13 + 8 - 10, so by rounding down the calculation result, we can obtain the correct average value data. This means that it has not been done. In other words, average value data cannot be obtained correctly, but data that is smaller by 0.5 in decimal number is output at a rate of 1/2.

Therefore, in a processing device that performs average value interpolation as described above, when data of low reliability is frequently input, the output is shifted downward with respect to the original signal.

Further, in conventional data processing apparatuses other than those having the above-mentioned configuration, the interpolated data is rounded up or down when obtained by calculation, so the output is shifted with respect to the original signal.

Furthermore, when dealing with a signal such as an analog audio signal in which positive and negative signals occur at almost the same rate with respect to the 0 level, this shift causes a DC component to be generated, which is not desirable.

(Purpose of "sold out") In view of the above-mentioned drawbacks, the present invention provides that when low reliability data is replaced with new interpolation data obtained by calculating the data before and after it, the output data is the same as the original signal. It is an object of the present invention to provide a data processing device which can prevent the signal from shifting to the original signal and obtain output data having properties similar to the original signal.

(Explanation based on examples) The present invention will be explained below using examples.

The following explanation will be made assuming that the analog signal is transmitted as 4-bit digital data. Furthermore, 2'8 conbriment is generally used in the binary system when converting audio and video signals into binarized signals. This tends to occur when a system error occurs, with all bits being 0” or all bits being ’1.
It is often used to explain that the value corresponding to the data of " is near 0, but since the arithmetic circuit in this embodiment includes the 1/? multiplier by the 1-bit shift described above, the so-called offset This will be explained as handling binarized data in binary format.Also, it may be assumed that data in 2'8 convolution is once converted to data in offset binary format and then processed.

FIG. 2 is a diagram showing the main part configuration of a data processing device as an embodiment of the present invention. Components in FIG. 2 that are the same as those in FIG. 1 are denoted by the same @ symbol, and their explanation will be omitted.

1'+Ibtic and 1a are terminals to which binary data is input, respectively, and the data input from these terminals is input as 4-bit data via a transmission system. 1
6 is a full adder circuit which adds the 4-bit data supplied to the terminals 1a to 1d and the 4-bit data output from the latch circuit 4, and outputs the result as 5-bit data.

If the upper 4 bits of these 5 bits of data are output, the data obtained by rounding down the average value of the input data of the latch circuit 2 and the output data of the latch circuit 4 to 10 is obtained as described above. 1B is an AND gate, 20 is a 7 lip flop (F,
F, ), and the output of F, 1.20 (1 is taken as the carry-in of the full adder circuit 16).

FIG. 6 is a timing chart showing the waveform of the second part, and the operation of each part according to the above-mentioned configuration will be explained below with reference to FIG. In this embodiment, the input data is a sampled analog signal (for example, an audio signal) that is generated at approximately the same rate with the O level as the boundary, and the quantization is performed linearly in 4 bits from 10 to +7 to 16. It shall be a stage. In other words, if the decimal data is published, it is 0ooq2)
, 1001 for o (1111 for g+7 (2
)It turns out that.

tp, 6 (b) is the output of the launch circuit 14, and when this output is 1'', it indicates that the output data of the latch circuit 2 is low reliability data.
When the output (1)) is 1'', the data selector 8 outputs the upper 4 bits of the full adder circuit 16.

Therefore, the AND gate 18 outputs a pulse signal every time the latch circuit 2 outputs low reliability data, and the AND gate 18 outputs a pulse signal every time the latch circuit 2 outputs low reliability data.
Every time 8 outputs a pulse signal, F, F, 30 inverts its output. Outputs of F, F', 30 (Fig. 6 (0)
) is the carry-in of the full adder circuit 16, so
Every time low reliability data is generated by the latch circuit 2, the carry-in of the full adder circuit 16 is switched between 1'' and O''.

Now, for example, the input of the full adder circuit 16 is 1011(2)(+
3) and 011 (J2) (-2), the output of the full adder circuit is I D OO1 (2) when the carry-in is 1D''.
), 11'', it becomes 10010(2). Therefore, the data supplied to the data selector 8 is 100q2)(0
), 1 o 01 (2) (+1 ). Like this,
When a fraction occurs when the full adder circuit 16 calculates the two inputs, that is, when the least significant bit (L8B) of the output data of the full adder circuit 16 is '1', the full adder circuit 16 uses the carry-in to calculate a fraction. It can be used as an average value calculation circuit that rounds up fractions, or as an average value calculation circuit that rounds fractions down. Therefore, the interpolated data to be replaced will be the average value of the immediately preceding and following data, rounded up and down, alternately.

According to the above-described configuration, interpolated data obtained by rounding up the average value of the immediately preceding and following data and interpolated data obtained by rounding down the average value are generated at almost the same rate, and the output data is as shown in FIG. 3 (,). There is no shift in either direction relative to the original signal. In FIG. 3 (&), the dotted line indicates the analog original signal, 0 indicates high reliability data, and Δ indicates interpolated data.

FIG. 4 is a diagram showing a data processing device according to another embodiment of the present invention. Components in FIG. 4 that are the same as those in FIG. 2 are given the same numbers and their explanations will be omitted. F, F, 20
is inverted for each data by a timing block, and the carry-in of the full adder circuit 16 is switched between '1' and '0'. Therefore, in this case as well, interpolated data obtained by rounding up the average value of the immediately preceding and following data and interpolated data obtained by rounding down the average value are generated at approximately the same rate, and the same effect as that of the apparatus shown in FIG. 2 is obtained.

Although the above explanation uses offset binary 4-bit data, the present invention is applicable regardless of the type of data and the number of quantizations. Although only the average value calculation has been described as a calculation means for obtaining interpolated data, the present invention can also be applied to the case of rounding up or down the calculation result in the case of the six-sweep method. Of course, the present invention can also be applied to interpolation when two or more pieces of unreliable data occur consecutively.

(Effect Explained J) As explained above, according to the present invention, when data with low reliability is replaced with interpolated data according to the calculation output of data before and after it, the data output by this is replaced with the original signal. The present invention provides a data processing device that can process data with similar properties.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a schematic fA configuration example of a conventional general data processing device, and Fig. 2 is a diagram showing a main part configuration of a data processing device as an embodiment of the present invention. 4 is a timing chart showing waveforms of each part in the device shown in the figure. FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention. 2 and 4 are latch circuits, 8 is a data selector included in the replacement means, 14 is a latch circuit, 16 is a full adder circuit included in the arithmetic means, 18 is an ant game h, and 2o is a flip-flop. Applicant Canon Co., Ltd. (C)

Claims (1)

[Claims] 1) A device for processing transmission data obtained by sampling a temporally continuous analog signal, which alternatively rounds up or down the calculation results of low-reliability data at the same rate and generates a new one. A data processing device comprising: means for generating data; and means for replacing the low reliability data with the data obtained by the generating means. 2. The data processing apparatus according to claim 1, wherein the σ-column generating means alternately rounds up or down the calculation result every time the low reliability data is generated. 6) The data processing device according to claim 1, wherein the generating means alternately rounds up or down the ml operation result every time the data is input to the device.