JPS60165135A - Data processor - Google Patents

Abstract

PURPOSE:To obtain an output data having a property close to that of an original signal by calculating data before and after a low reliability data and discriminating a level between the result of calculation and a prescribed value so as to attain alternately the round-off and cutoff of the result of calculation alternatively thereby generating a new data. CONSTITUTION:Suppose that a data A is a data (1101(2)) corresponding to analog + increment + 5 and a data C is a data (1010(2)) corresponding to +2. When the data A is inputted to a latch circuit 2 and the data C is outputted from a latch circuit 4, an output of a full adder circuit 16 is 10111(2). Since the data (MSB) of the most significant bit is logical ''1'', an output of an inverter 18 is logical 0 and the carry-in is logical 0 and no addition is conducted at all. In taking out a data of the high-order 4-bit of the output of the full adder circuit 16, it corresponds to 1 bit shift and an average value interpolation data (1011(2)) between the data A and C is obtained and the data (LSB) of the least significant bit of the output of the full adder circuit 16 is cut off in this case. That is, the average value interpolation data is +3.5(2+5)/2 from the analogical point of view, while the actual interpolation data is +3.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a data processing device, and particularly to a data processing device that processes data obtained by sampling analog signals such as audio signals and video signals that are continuous in time and occur at approximately the same rate with a predetermined value as a boundary. The present invention relates to a device that performs post-processing via a transmission system such as a recording/reproducing system.

(Description of Prior Art) Generally, data with low reliability may occur in data transmitted through a transmission system. In such cases, it is common to replace the low reliability data with newly generated data. For example, when low reliability data occurs in data obtained by sampling an audio signal, a method has been used in which the data is replaced with interpolated data obtained using data before and after the data.

The methods include the pre-hold method in which the data immediately before the low reliability data is used as interpolated data, the average value interpolation method in which the average value of the data immediately before and after the low reliability data is used as the interpolated data, and the low reliability data. Data near reliability data (
A sixth order interpolation method using interpolated data obtained from at least four methods is known.

As for the degree of approximation of such interpolated data to the original signal data, the forward hold method is the worst, and the average value interpolation method and the 6th order interpolation method are better, but the hardware scale also increases accordingly. It ends up. Therefore, they are used depending on the type of information signal processed by the data processing circuit and the scale of the device.

FIG. 1 is a diagram showing a schematic configuration example of a conventional general data processing device that replaces low-reliability data using an average value interpolation method. In FIG. 1, 2 and 4 are latch circuits that delay transmitted data by one sampling period. Reference numeral 6 denotes an average value calculation circuit, which calculates and outputs the input data of the latch circuit 2 and the output data of the latch circuit 4.

A data selector 8 selectively outputs the output data of the latch circuit 2 and the output data of the average value calculation circuit 6. 10 is an input terminal for a timing clock, 12 is an input terminal for a well-known error detection signal, and 14 is a latch circuit for delaying the error detection signal by one sampling period. As for error detection signals, as is well known, parity words and CI (,
It is obtained by checking the CC, and for example, when the data input to the latch circuit 2 is low reliability data, "1" is input, and when it is high reliability data, '0' is input from the terminal 12. In addition, the data selector 8
When the output from the latch circuit 14 is "1", it outputs the output data of the average value calculation circuit 6, and when the output from the latch circuit 14 is "0", it outputs the output data of the latch circuit 2.

Now, if the reliability of the output data of the latch circuit 2 is high, the output of the latch circuit 14 is "0", and the data selector 8
outputs the output data of the latch circuit 2 as is. On the other hand, if the reliability of the output data of latch circuit 2 is low,
Since the output of the latch circuit 14 becomes "1", the output data of the average value calculation circuit B is outputted from the data selector. Since the output data of the average false calculation circuit 6 is the average value of the data immediately before and after the output data of the latch circuit 2, it means that average value interpolation has been performed.

Here, the average value calculation circuit 6 is composed of, for example, a full adder circuit and a 1/2 multiplier using a 1-bit shift.

In this case, the least significant bit of the input data of the 1/2 multiplier is 1.
'', the output data of the average value calculation circuit B will necessarily be the data obtained by rounding down the calculation result.

This will be explained in more detail below. Assuming that the current data is 4 bits, the data (A data) immediately before the low reliability data (B data) is 1101 (2).

When the immediately following data (C data) is set to 1001 (2), 13+9- is obtained. If you think of this in decimal notation, it is 1. , -11, which means that the correct average value data has been obtained.
If the data is 1101(2) and the C data is 1000(2), after obtaining 1010.1(21) with A+C, we obtain 1010(2) as the average value data, but this is not considered in decimal system. In other words, the average value data will not be obtained correctly, and there is a probability of 1/2 that the decimal value will be 0.
This will output data that is smaller by 5. Therefore, in a processing device that performs average value interpolation as described above, when data with low reliability is frequently input, the output is shifted downward with respect to the original signal.

Furthermore, in conventional data processing apparatuses other than those having the above-mentioned configuration, interpolation data is rounded up or down when obtained by calculation, so that the output is shifted with respect to the original signal.

Furthermore, when dealing with a signal such as an analog audio signal in which positive and negative signals occur at almost the same rate with respect to the 0 level, this shift causes a DC component to be generated, which is not desirable.

(Object of the Invention) In view of the above-mentioned drawbacks, the present invention provides that when low reliability data is replaced with new interpolation data obtained by calculating the data before and after it, the output data is It is an object of the present invention to provide a data processing device that can prevent shifting and obtain output data having properties similar to the original signal.

(Explanation based on examples) The present invention will be explained below using examples.

The following explanation will be made assuming that the analog signal is transmitted as 4-bit digital data. In addition, 2/s conglomerate is generally used in the binary system when converting audio and video signals into binarized signals. This is often used because the value corresponding to data in which all bits are 0″' or all bits are “1” is around 0, which tends to occur when a system abnormality occurs. Since we will include a power multiplier based on a 1-bit shift of , we will explain that we are dealing with binarized data based on so-called offset binary.Also, we will first convert the data based on 2'S combination into data based on offset binary. You can think of it as something to be processed.

FIG. 2 is a diagram showing the main part configuration of a data processing device as an embodiment of the present invention. In FIG. 2, the same components as in FIG. 1 are given the same numbers and their explanations are omitted. i
A, lb, ic, and 1d are terminals to which binary data is input, respectively, and the data input from these terminals is input as 4-bit data via a transmission system. A full adder circuit 16 adds the 4-bit data supplied to the terminals 1a-1d and the 4-bit data output from the latch circuit 4, and outputs the result as 5-bit data (dt-d5). Top 4 bits of this 5-bit data) (
d2 to ds), the latch circuit 2
Data obtained by rounding down the average value of the input data of and the output data of the latch circuit 4 is obtained.

18 is an inverter; 20 is a flip-flop (F, F, ) that is triggered by the output of the inverter 18 and set every sampling period; the outputs of F, F, and 20 are carried in to the full adder circuit 16;

The operation of each part according to the above-described configuration will be explained below using a specific example of input data. In this embodiment, the input data is an analog signal (
For example, an audio signal) is sampled, and the quantization is linear with 4 bits and 16 steps from -8 to +7. In other words, if the decimal data is -8, it is 0
000(2).

10DD(2) if 0, 111 if +7
1 (2). Furthermore, the following description assumes that A data, B data, and C data are input in this order at a certain timing in the time series, and that the reliability of the B data is low and that this B data is replaced with interpolated data.

Table 1 Example of input/output data Table 1 is a table showing examples of input data and output data.
The following explanation will be given based on this table. The A data corresponds to the analog decimal amount + 5 (1101(2)), C
It is assumed that the data corresponds to +2 (1010(2)). Now, the A data is input to the latch circuit 2, and the C data is output from the latch circuit 4.
The output is 10111(2). Now, since the most significant bit data (MSB) is “1”, the inverter 18
The output is O" and the carry-in is 0, so it is not added. If the data of the upper 4 bits of the output of the full adder circuit 16 is taken out, it will be shifted by 1 bit and the average value interpolated data (1011(2)) of the A data and C data will be obtained. The data of the least significant bit of the output (LSB) is rounded down to 0. In other words, from an analog perspective, the average value interpolated data is +3.5 (=Fuji 1,000 -), whereas the actual interpolated data is This means +6.

Next, when the human data is +5 (11,01(z)) and the C data is (1001(2)), the output of the full adder circuit 16 is 10110(2), and the carry-in is "0'"
It is.

In this case as well, the interpolated data is 1011(2). This is -1+5 Even from an analog perspective, the interpolated data is +5 <--, -)
There is no rounding up or down.

Furthermore, A data is +1. Let's consider the case when the C data is -4. As shown in Table 1, the output data of the full adder circuit 16 at this time is 01101(2), but since the carry-in is set to 01110(2), the interpolated data is 0.
111(2). From an analog perspective, the average value is −
1,5<=1 4>, while the interpolated data is -1
Therefore, the LSB is rounded up. On the other hand, human data is +1. When the LSB of the output of the full adder circuit 16 is "0" as in the case where the C data is -6, the LSB of K only changes "to" even if the carry-in becomes "1'".

Therefore, the upper 4 bits of data do not change and are not rounded up or down.

According to the above-described configuration, M8 of the output of the full adder circuit 16
When B is "Z", rounding down can be performed, and when B is "01", only rounding up can be performed. This means that when the average value of A data and C data is greater than 0, it is rounded down, and when it is less than 0, it is rounded up.The MSB is used to determine whether the average value of A data and C data is greater than O. Nothing but being there.

Therefore, according to this embodiment, when the interpolation data is positive, it is always rounded down, and when it is negative, it is always rounded down, so (
・Even in the case of deviation, there is a tendency to bring it closer to the O level. Therefore, the output data does not shift in one direction, and data having properties similar to the original signal can be obtained.

Figure 6 is a diagram for explaining this, and the figure shows...
The dotted line is the analog original signal, ○ is highly reliable data, Δ
indicates interpolated data by the apparatus shown in FIG. 1, and X indicates interpolated data shown in FIG. 2, respectively. As is clear from the figure, data tends to be shifted downward in the device shown in FIG. 1, but this tendency disappears in the device shown in FIG.

Of course, on the contrary, the MSB of the output of the full adder circuit 16 is "1".
It is also possible to round up when it is `` and round down when it is #0'', and similarly obtain the effect that the signal does not shift. In this case, the MSB of the full adder circuit 16 may be directly used as the carry-in of the full adder circuit 16, and this configuration is particularly effective when the analog original signal has a sine wave shape.

In other words, in general, when the analog original signal has a sine wave shape bordering on a predetermined value, it tends to convex upwards above the predetermined value, and convexly downward below the predetermined value, so when the calculation result is above the predetermined value, it is rounded up. , the interpolated data approximates the analog original signal by rounding down the following times.

FIG. 4 is a diagram showing the main part configuration of a data processing circuit as another embodiment of the present invention. Components in FIG. 4 that are similar to those in FIG. 2 are given the same numbers, and explanations thereof will be omitted. 22 is a Noah gate, and 24 is an AND gate. According to this configuration, the output of the full adder circuit 16 is 01100 (2)
In the above case, there is no carry-in and the value is devalued to 01011 (2
) In the following cases, there is a carry-in and it is configured so that only rounding is possible.

Therefore, in this configuration, it is determined whether the result of the average value calculation is larger or smaller than -2 from an analog point of view, and it is determined whether to round up or down. Naturally, this is used when processing data obtained by sampling analog signals that occur at approximately the same rate with -2 as the boundary.

In this case as well, it is possible to obtain output data that is similar in nature to the original analog signal without being shifted to one side. Of course, if the Noah gate 21 is OR gated, rounding up and down can be reversed. Furthermore, it goes without saying that by changing the logic circuit, it is possible to determine the magnitude relationship with any predetermined value and decide whether to round up or down.

Although the above description uses offset binary 4-bit data, the present invention is applicable regardless of the type of data and the number of quantizations. In addition, as a calculation means for obtaining interpolated data, only the average value calculation has been explained, but the present invention can also be applied to rounding up or down the calculation result in the case of the 6th order interpolation method. Of course, it is also applicable to interpolation when low reliability data is continuous.

(Description of Effects) As explained above, according to the present invention, when data with low reliability is replaced with interpolated data according to the calculation output of the data before and after it, the data output by this is replaced with the original signal. The present invention provides a data processing device that can process data with similar properties.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration example of a conventional general data processing device, FIG. 2 is a diagram showing a main part configuration of a data processing device as an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention. 2 and 4 are latch circuits, 8 is a data selector included in the replacement means, 14 is a latch circuit, 16 is a full adder circuit included in the calculation means, 1B is an inverter, 20 is a free lag flop, 22 is a NOR gate, and 24 is a And gate. Applicant: Canon Co., Ltd. Continued from page 1 ■Inventor: Kashi 1) Moto - 77 Hata, Shimonoge, Takatsu-ku, Kawasaki City, Canon Co., Ltd. Tamagawa Office

Claims (1)

[Claims] A device for processing transmission data obtained by sampling analog signals that occur continuously in time and at approximately the same rate with a predetermined value as a boundary, comprising means for calculating data before and after low reliability data, and a means for calculating data before and after low reliability data, and means for determining the magnitude relationship between the calculation result and the predetermined value; means for selectively rounding up or rounding down the calculation result according to the determination means to generate new data; and means for replacing the low reliability data with data.