JP2668901B2 - Encoding device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for coding a digitized signal. 2. Description of the Related Art One of the codes for coding a digitized signal,
There is a correlative code. This is a general term for a method of transmitting information of one time slot over a plurality of time slots and receiving the information as multi-values, such as duobinary and partial response.
The code called response) belongs to this. Since it receives as multi-value, it has the feature that it can transmit in a narrow band compared to the method of receiving in two values (for example, NRZ). Problems to be Solved by the Invention Conventionally, if transmission is performed in a narrower band using a correlation code, there is a problem that the number of multilevel level stages increases and the SN ratio of the transmission path needs to be good. It was Means for Solving the Problems A signal generation circuit for generating a duobinary signal, which is a kind of correlation code, a sign inversion circuit, and a sign inversion control circuit, wherein an output signal of the signal generation circuit is the sign inversion. Circuit, the output signal of the sign inversion circuit is supplied to the sign inversion control signal generating circuit, the output signal of the sign inversion control signal generating circuit is supplied to the sign inversion circuit, and from the signal generating circuit. It is configured such that the output code string is subjected to inversion control so that the preceding and following codes do not have the same polarity, with a zero code or a series thereof being sandwiched, and output. Effect The present invention has an effect that the transmission code can receive the same ternary signal as the duobinary signal, but can be transmitted in a narrower band than the duobinary signal. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of the present invention, and FIGS. 2 (a) to 2 (d) are waveform diagrams showing signal waveform examples of respective parts in FIG. In FIG. 1, the signal waveform input to the input terminal 1 is shown in FIG. Such a signal is input to the duobinary signal generation circuit 2. The duobinary signal generation circuit 2 is well known and comprises, for example, a modulo-2 adder 6, delay circuits 7, 8 and an algebraic sum circuit 9, as shown in FIG. The operation of the duobinary signal generation circuit 2 is, for example, P.79 of PCM communication technology (published by Sangyo Shuppan) or Takashi Kaneko, or IEEE TRANSACTI communication technology (IEEE TRANSACTI).
ONS ON COMMUNICATION TECHNOLOGY, February 1966 (P.6)
7-P.68). FIG. 2C shows an output signal waveform of the duobinary circuit 2. This is the generally known duobinary signal. This signal is
In general, it often occurs that a non-zero value next to 1 becomes 1 again so that it has a DC component and, for example, 0 → 1 → 0 → 1. -1 like 0 → -1 → 0 → -1
Is often followed by -1 again as a non-zero value. This is the cause of having a DC component,
In addition, when the code transmission path is of the electromagnetic conversion type of a magnetic recording / reproducing device composed of a tape head or the like, a large distortion occurs in the reproduced waveform, and the probability of occurrence of a code error increases. In the present invention, as described below, after 0 → 1,
(If 1 continues, then 1 ends, then)
If a zero comes and then (where the zeros continue, the continuation of the zeros ends, and then a -1), the output continues as it is,
The sign inverting circuit 3 and the sign inverting control signal generating circuit 4 so that the sign inverts and outputs -1 when 1 comes.
Is configured. FIG. 4 shows a specific circuit example of the sign inversion circuit 3 and the sign inversion control signal generation circuit 4. In FIG. 4, the sign inverting circuit 3 is composed of a duobinary signal input terminal 10, a switch 13, a polarity inverting circuit 12, a flip-flop circuit 11, an output terminal 14, and an inverting pulse (p) input terminal 15. It The flip-flop circuit 11 is a toggle-type flip-flop that flips the switch 13 to a switch terminal side different from the currently tilted switch terminal side every time the inverted pulse (p) is input. The sign inversion control signal generation circuit 4 detects an input terminal 16 connected to the output terminal 14, a previous value comparison circuit 17 for judging whether the current value has changed from the previous value, and whether the current value is zero. Zero detection circuit 23
And an AND circuit 25 that ANDs the output signal of the previous value comparison circuit 17 and the output signal of the zero detection circuit 23, and the current value changes compared to the previous value, and if the current value is zero, A memory circuit 26 for storing the previous value, a coincidence detection circuit 29 for determining whether the current value of the input signal is other than zero and coincident with the output signal of the memory circuit 26, and an output terminal 38 for the inversion pulse (p). Composed of. The previous value comparison circuit 17 includes, for example, a subtraction circuit 18, a delay circuit 19, a "1" detection circuit 20, and a "-1" detection circuit 21.
It is composed of an OR circuit 22. The zero detection circuit 23 is composed of a “0” detection circuit 24. The memory circuit 26 is a delay circuit 27
And a sample hold circuit 28. The match detection circuit 29 is ANDed with the "-1" detection circuit 34 and the "-1" detection circuit 35.
It comprises a circuit 36, a "1" detection circuit 30, a "1" detection circuit 31, an AND circuit, and an OR circuit 37. The delay circuit 19,
27 is constituted by, for example, a D flip-flop (not shown), and delays an input signal sequence by one time slot.
The "1" detection circuits 20, 30, and 31 are well-known level comparators (not shown), and the "-1" detection circuits 21,
The same applies to 34 and 35, and the same applies to the "0" detection circuit 24. In such a sign inversion circuit 3 and a sign inversion control signal generation circuit 4, it is assumed that the duobinary signal shown in FIG. For explanation, it is assumed that the switch 13 initially selects a signal that is not inverted. The output signal of this embodiment at this time is shown in FIG. The first non-zero signal value "-1" (signal value 100 in FIG. 2 (c)) is input, and immediately after that, the signal changes from "-1" to "0" (signal in FIG. 2 (c)). Value 101),
The memory circuit 26 outputs the output signal value “−1” immediately before the signal 101.
(Signal value 106 in FIG. 2D) is stored. After that, the next non-zero signal "-1" (Fig. 2 (c))
Signal value 102) is input, the match detection circuit 29
Detecting that the currently input non-zero signal value matches the signal value “−1” stored in the memory circuit 26;
The inversion pulse (p) is output. Flip-flop circuit 11
Receives this pulse and causes the switch 13 to select the inverted signal. This state is maintained until the next inversion pulse (p) is input. By such an operation, the signal output from the sign inversion circuit 3 is inverted to “+1” as shown by the signal value 107 in FIG. 2D. The next non-zero signal value "-1" (signal value 103 in FIG. 2 (c)) is also the signal in FIG. 2 (d) because the switch 13 has selected the inverted signal in the above operation. It is inverted to "+1" as indicated by the value 108. Immediately after that, when the signal applied to the input terminal 10 changes from “−1” to “0” (the signal value 104 in FIG. 2C), the input signal of the previous value comparison circuit 17 also changes from “+1”. “0” (signal value 109 in FIG. 2 (d))
In response to this, the memory circuit 26 receives the signal value 109
(+1) (signal value 108 in FIG. 2 (d))
Is stored. By repeating the above operation, an output signal sequence is obtained as shown in FIG. Note that the encoding device according to the present invention is not limited to the configuration shown in FIG. 1 as long as it can transform a duobinary signal in the following manner. , Then the next zero) comes, and next (when the zero continues, then the zero comes and then -1), it outputs as it is, When 1 comes, the sign is inverted and output as -1. Similarly, after -1, (when -1 continues, the continuation of -1 ends, next), zero comes, and then (If zeros continue here, the sequence of zeros ends, then when 1 comes, it is output as it is, and when -1 comes, the sign is inverted and output as 1. Is. For example, as another embodiment, in FIG. 1, the output signal of the duobinary signal generating circuit 2 is input to the sign inversion signal control circuit 4, and the output signal of the sign inversion signal control circuit 4 causes the sign inversion circuit 3 to operate. The duobinary signal may be controlled and transformed according to the above-described procedure. Effect of the Invention The duobinary signal is transformed, and -1 comes again through zero and then -1 as in -1 → 0 → −1, and 1 as in 1 → 0 → 1 as in 1 → 0 → 1. By prohibiting both of 1 to come again via zero to 0, the nature of the duobinary signal at the time of reception (three values and even level is discriminated as 1 and odd level is discriminated as zero). Accordingly, narrowband transmission is possible without losing the original information), and when the transmission path is an electromagnetic conversion system,-
The prohibition of the pattern of 1 → 0-1 and 1 → 0 → 1 makes the electromagnetic conversion system less susceptible to distortion, and has the effect of reducing the probability of occurrence of code errors.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a main part in an embodiment of the present invention, and FIGS. 2 (a) to (d) are FIGS.
4 is a signal waveform diagram showing signal waveforms at various parts in FIG. 4, FIG. 3 is a circuit block diagram showing an example of the duobinary signal generation circuit in FIG. 1, FIG. 4 is a sign inversion circuit in FIG. It is a circuit block diagram showing an example of a sign inversion control signal generation circuit. 2 ... Duo binary signal generation circuit, 3 ... Sign inversion circuit, 4 ... Sign inversion control signal generation circuit.

Claims (1)

(57) [Claims] A duobinary signal generation circuit, a sign inversion circuit, and a sign inversion control signal generation circuit; an output signal of the duobinary signal generation circuit is supplied to the sign inversion circuit; and an output signal of the sign inversion circuit is A sign inversion control signal generation circuit is supplied, and an output signal of the sign inversion control signal generation circuit is supplied to the code inversion circuit and a zero code is supplied to the code string output from the duobinary signal generation circuit, or An encoding apparatus characterized by performing inversion control so that the preceding and succeeding codes do not have the same polarity with respect to the continuous one, and outputting the result. 2. As a sign inversion control circuit, a sign value storage circuit that stores a sign value before a sign value of an input sign inversion circuit output signal changes from positive or negative to zero, and a sign inversion circuit of an inputted sign inversion circuit. A timing detection circuit for detecting a timing at which the code value changes from zero to positive or negative; and a coincidence detection for judging the coincidence between the code value after the change and the code value stored in the code value storage circuit at the timing. And a circuit for controlling the sign reversing circuit to invert and output the sign of the output signal in the case of coincidence, and to output the original sign as it is in the case of disagreement. The encoding device according to claim (1).