JPS6120440A - Code error correcting device - Google Patents

Abstract

PURPOSE:To curtail the number of shift register circuits and selector circuits, and to reduce the scale of the circuit by constituting a titled device by providing an error decision circuit for controlling an output of the first and the second selector circuits, in accordance with whether two digital signals which are sent continuously are correct or erroneous. CONSTITUTION:Two data which are sent continuously are denoted as D1, D2 (D2 is sent first), and a data stored in a shift register circuit 15 is denoted as D3. In case D1 is correct, and D2 is erroneous, a shift register circuit 11 inputs the next correct data D1 instead of the erroneous data D2. Subsequently, an error decision circuit 18 outputs a signal so that a selector circuit 12 selects an output DO1 of the shift register circuit, and also a selector circuit 13 selects an output DO3 of a shift register circuit 16. Outputs of the selector circuits 12, 13 are inputted to a one bit full adding circuit 14 and added, become (DO1+DO3), multiplied by 1/2, (DO1+DO3)/2 is inputted to the shift register circuit 16, and a mean value interpolation is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a code error correction device that can be used to correct code errors in the transmission of digitized music signals from digital and audio equipment.

Conventional Structure and Problems In recent years, it has become popular to digitize audio signals for recording, transmission, and reproduction.

Noise on the transmission path of the digitized audio signal significantly deteriorates the quality of the reproduced audio signal and causes harshness or licks. To improve the reliability of the transmitted signal, error correction codes are used. is common. Furthermore, error correction is also performed in order to deal with noise that exceeds the error correction capability.

Special K: In a sampled acoustic signal, there is a strong correlation between values between successive sampling points, so if a sampling point is missing or has an error, the average value of the values of the preceding and following sampling points is calculated. Correction that uses or retains the value of the previous sample point is an effective and commonly used method. The former is called average value interpolation, and the latter is called previous value retention.

An example of a conventional code error correction device will be described below with reference to the drawings. FIG. 1 is a block diagram of a conventional code error correction device, where 1 is a shift register circuit into which a digital signal (n bits = 1 word) in offset binary representation is input in parallel, and 2 is the output of the shift register circuit 1. 3 is a shift register circuit whose input is 1, which will be described later.
A selector circuit selects and outputs the output of the bit full adder 9 and the output of the shift register circuit 2; 4 is a shift register circuit that receives the output of the selector circuit; 6 is a parallel output of the shift register circuit 4; a selector circuit that takes the input as input and selects whether to input it as is or shift it by one bit to the least significant bit side and output it in parallel;
7 is a latch circuit that receives the parallel input of the shift register circuit 6; and 8 is the output of the shift register circuit 1 and the output of the shift register circuit 6. 9 is a 1-bit full adder that adds the serial outputs of the shift register circuit 6 and the selector circuit 8, and 1° is a shift register circuit 1, 2.
This is an error determination circuit that outputs a signal that switches the outputs of the three selector circuits 3, 5, and 8 described above depending on whether the signals stored in the circuit are correct or incorrect.

The operation of the code error correction device configured as described above will be explained below.

For convenience, the contents stored in the shift register circuits 1.2.4 are respectively Dl, Dl, D, and their outputs are Dol, Do2, . Do4.

Now, when Dl is correct, the error detection circuit 1o outputs a signal for the selector circuit 3 to select DO□, and the shift register circuit 4 receives the contents of Do2.

Then, a signal is sent from the error determination circuit 1o so that the selector circuit 5 passes the parallel output of the shift register circuit 4 as is. In this way, the shift register circuit 6 has
The correct Do2 data is sent as a serial output or launched into the latch circuit 7 and sent out as a parallel output.

Next, if Dl is correct and Dl is incorrect, the error determination circuit 1o selects the selector circuit 8 from the shift register circuit 1.
The selector circuit 3 outputs a signal to select the output (Do, ↑Do,) of the 1-bit full adder circuit 9, and as a result, the shift register circuit 4 outputs (Do, +Do, ). Contains the contents of At this time, a signal is sent from the error determination circuit 10 to the selector circuit 6 so that the parallel output of the shift register circuit 4 is shifted by one bit toward the least significant bit. In this way, the shift register circuit 6 receives the average value interpolated data (Do, +DO3
)/2 is sent.

Next, if both J'Dl are wrong, the error determination circuit 10 causes the selector circuit 8 to select the output D03 of the shift register circuit 6, and the selector circuit 3 to select the output (Do, +DO, ) is output, and as a result, the shift register circuit 4 selects (D
o3+DO3)=Contains the contents of 2DO3. At this time, the selector circuit is controlled by the error determination circuit 1o so as to shift the parallel output of the shift register circuit 4 by one bit toward the least significant bit and output it. In this way, the data DO3 whose previous value is held is sent to the shift register circuit 6.

However, in the above-mentioned configuration, there is a problem that the number of shift register circuits is large, and particularly when the number of bits in one word, n, becomes large, the circuit scale becomes large. In particular, 16 bits like digital audio,
When dealing with data, there is also the problem that when the circuit is integrated, it occupies a large area and affects the cost.

OBJECTS OF THE INVENTION An object of the present invention is to provide a code error correction device that makes it possible to reduce the number of shift register circuits and reduce the circuit scale.

Structure of the Invention The code error correction device of the present invention includes a first shift register circuit that receives a digital binary signal of n bits per word, an output of the first shift register circuit, and a third shift register circuit. a first selector circuit that selects and outputs the output of the first shift register circuit;
The second shift register circuit selects and outputs the output of the shift register circuit.
a 1-bit full adder circuit whose inputs are the outputs of the first selector circuit and the output of the second selector circuit, and a second selector circuit whose inputs are the outputs of the 1-bit full adder circuit.
and the third shift register circuit, which shifts the parallel output of the second shift register circuit by one bit to the least significant bit side and uses it as a parallel input, and According to right or wrong, 1st. It is configured to include an error determination circuit that controls the output of the second selector circuit, thereby making it possible to reduce the circuit scale.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a code error correction device in an embodiment of the present invention. In FIG. 2, reference numeral 11 denotes a soft register circuit into which a digital signal of one word of n bits in offset binary representation is input in parallel;
2 selects the outputs of the shift register circuit 11 and the shift register circuit 16 described later; 1. 13 is a selector circuit that selects and outputs the outputs of the shift register circuit 11 and the shift register circuit 16 described later; 14 is a 1-bit full adder circuit that receives the outputs of the selector circuits 12 and 13; 16 is a shift register circuit whose input is the output of the 1-bit full adder circuit 14, 16 is a shift register circuit whose parallel input is the parallel output of the shift register circuit 15 shifted by 1 bit toward the least significant bit, and 17 is a shift register circuit. A launch circuit 18 receives the parallel output of the register circuit 16 as an input, and 18 receives the parallel output of the register circuit 16.
Selector circuit 12.1 depending on whether the two digital signals are correct or incorrect.
This is an error determination circuit that controls the output of the shift register 11 as well as the input signal sent to the shift register 11.

The operation of the code error correction apparatus of this embodiment configured as described above will be described below.

For convenience, two pieces of data that are sent consecutively are Dl.

D2 (D2 comes first), the data stored in the shift register circuit 16 is assumed to be.

Now, when D2 is correct, D2 is input to the shift register circuit 11, and the error judgment circuit 18 is input to the selector circuit 12.13.
Both output signals to select the output D02 of the shift register circuit 11. The data passing through the selector circuits 12 and 13 are added by the 1-bit full adder circuit 14 (D02+DO2
) and is input to the shift register circuit 16. The parallel output of the shift register circuit 16 is input to the shift register circuit 16 with one bit shifted toward the least significant bit, so it is multiplied by A, and (Do□+D02)/2=D0
2, and is output serially or in parallel through the latch circuit 17 as correct original data.

Next, if D is correct and D2 is incorrect, the shift register circuit 11 inputs the next correct data D1 instead of the incorrect data D2. Then, the error determination circuit 18 issues a signal so that the selector circuit 12 selects the output DO of the shift register circuit 11 and the selector circuit 13 selects the output Do of the shift register circuit 16.

The outputs of the selector circuits 12 and 13 are input to the 1-bit full adder circuit 14 and added, resulting in (Do1+DO5),
The signal is input to the shift register circuit 15. Then, as described above, it is multiplied by 11I2, (Do, +DO3)/2 is input to the shift register circuit 16, and average value interpolation is performed.

Next, if both D and D2 are incorrect, the error determination circuit 18 outputs a signal so that the selector circuits 12 and 13 select and output the output Do of the shift register circuit 16. The outputs of the selector circuits 12 and 13 are added by the 1-bit full adder circuit 14 (Do, +DO,)
and is sent to the shift register circuit 16. Then, as mentioned above, it is multiplied by A, (DO3+D03)/2=Do3
Therefore, the previous value DO6 is input to the shift register circuit 16 instead of Do2, and the previous value is held.

As described above, according to this embodiment, when data is isolated and erroneous, the following data is read in place of the erroneous data, and the data is always passed through the 1-bit full adder circuit. After that, the number is multiplied by A by shifting one bit to the second 9s bit side, thereby reducing the number of shift register circuits and selector circuits, thereby making it possible to reduce the circuit scale.

Effects of the Invention As is clear from the invention described above, the present invention provides a first shift register circuit which inputs a digital binary signal of n bits per word, an output of the first shift register circuit, and a third shift register circuit.
The first selects and outputs the output of the shift register circuit.
with selector circuit.

a second selector circuit that selects and outputs the output of the first shift register circuit and the output of the third shift register circuit; and the output of the first selector circuit and the output of the second selector circuit. A 1-bit full adder circuit as an input, a second shift register circuit that receives the output of the 1-bit full adder circuit as an input, and a parallel output of the second shift register circuit shifted by 1 bit to the least significant bit side for parallel input. the third shift register circuit, and an error determination circuit that controls the outputs of the first and second selector circuits depending on whether the two successively sent digital signals are correct or incorrect. Therefore, the number of shift register circuits and selector circuits can be reduced, and the excellent effect of reducing the circuit scale can be obtained.

As a result, the chip area when integrated into an integrated circuit is reduced, and costs can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional code error correction device, and FIG. 2 is a block diagram of a code error correction device in an embodiment of the present invention. 1...Shift register circuit, 2...Shift register circuit, 3...Selector circuit, 4...
...Shift register circuit, 5...Selector circuit, 6...Shift register circuit, r...
...Latch circuit, 8...Selector circuit, 9...
...1-bit full adder circuit, 1o old...error determination circuit, 11...shift register circuit, 12...
...Selector circuit, 13...Selector circuit,
14...1-bit full adder circuit, 16...
・Shift register circuit, 16...Shift register circuit, 17.Old...Outside notch circuit, 18...Error determination circuit.

Claims (4)

[Claims] (1) Select and output a first shift register circuit that receives a digital binary signal of n bits per word, the output of the first shift register circuit, and the output of the third shift register circuit. a first selector circuit, a second selector circuit that selects and outputs an output of the first shift register circuit and an output of the third shift register circuit;
a 1-bit full adder circuit that receives the output of the first selector circuit and the output of the second selector circuit; a second shift register circuit that receives the output of the 1-bit full adder circuit; The third shift register circuit shifts the parallel output of the second shift register circuit by one bit to the least significant bit side and uses it as a parallel input, and the first and A code error correction device comprising an error determination circuit that controls the output of the second selector circuit. (2) The code error correction device according to claim 1, wherein the data addition is performed by serially calculating data in offset binary representation starting from the least significant bit. (3) Code error correction according to claim 1, characterized in that when correction is performed by average value interpolation, erroneous data is discarded and the next correct data is input to the first shift register circuit. Device. (4) If two pieces of transmitted data are erroneous in a row, the previous value is retained, and if the transmitted data is isolated and erroneous, average value interpolation is performed by operating the data selector. A code error correction device according to claim 1, characterized in that: