JPS62216557A - Phase ambiguity removing circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit and to decrease a cost by constituting two SOM (start of message) detectors and a phase ambiguity correcting device of a large capacity ROM respectively, inputting a phase information signal and a serial signal from a PSK demodulating board by the phase ambiguity correcting device and outputting the serial signal to remove the phase ambiguity. CONSTITUTION:SOM detectors 3 and 4 and a phase ambiguity correcting device 6 are respectively constituted of one large capacity ROM of 64 K bits or above. The removing circuit corrects eight ambiguities to occur at the process of four phase phase demodulation on a demodulating board and reproduces correct data. The correction of ambiguity is controlled by the control signal of a selector in a position ambiguity correcting device 6. For example, a phase detector 5 detects the phase information by analyzing output signals 105 and 106 of the SOM detectors 3 and 4 and outputs three types of pulses for correcting the ambiguity to the selector of the phase ambiguity correcting device 6. Thus, the control signal of the selector comes to be the correct condition and the ambiguity is corrected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a 5CPC/PSK device, and particularly to a SOM (
This invention relates to a four-phase code board compatible with burst mode using a five-tart-of-message pattern.

[Conventional technology]

A one-phase ambiguity removal circuit is essential for this type of device, and hereafter the length of the SOM pattern is A.

The case where each of the eight channels is 16 bits will be explained.

A conventional phase ambiguity removal circuit performs parallel-to-serial conversion that inputs the 2-channel serial signals DATA-A and DATA-B from the PSK demodulator and outputs a 1-channel serial signal with twice the information rate. a serial-to-parallel conversion circuit that inputs the 1-digit serial signal and outputs a signal with an odd bit delay of 1 to 33 bits; and an SOM that inputs the odd bit delay signal and outputs a SOM detection signal. a detector; and an ambiguity detector that receives the SOM detection signal and outputs a phase error detection signal.

The phase error is corrected by inputting the phase error detection signal and a two-way serial signal from the PSK demodulator.
and an ambiguity corrector that outputs an f-channel serial signal.

[Problem that the invention seeks to solve]

The phase ambiguity dust removal circuit described above uses a ROM for the SOM detector, but this ROM only detects 8-bit patterns.

A channel SOM (this is called SOM A) and B
Channel SOM (this is called SOM B) 1 each
The 6-bit SOM pattern is divided into the first half and the second half and detected separately.

Also, if SOM detection is performed independently for A channel and B channel, the number of memories will be doubled, so the parallel-to-serial conversion circuit will alternate the patterns of SOM A and SOMB to create a 65-bit serial signal for one channel. Input to shift register.

Then, when all the alternating patterns of SOM A and SOMB are entered into the shift register, S is sent to the odd bit delay data output terminal of the 1st bit to 63rd bit of the 7th shift register.
The pattern of OM A is output, and the SOM is detected by the SOM detector.
A is detected. Furthermore, the SOMB pattern is output from the shift register using the primary clock signal, and SOMB is detected.

As mentioned above, the conventional phase ambiguity dust removal circuit.

A parallel/serial conversion circuit and a 63-bit shift register are required. Furthermore, since the ambiguity corrector is realized by a gate circuit, there is a drawback that one circuit becomes complicated.

Accordingly, one object of the present invention is to provide an economical phase ambiguity removal circuit using only a WR by using a large-capacity ROM and omitting redundant circuits.

[Means for solving problems]

The phase ambiguity dust removal circuit according to the present invention includes a serial-to-parallel conversion circuit that converts two columns of serial signals from a PSK demodulator into N columns of parallel signals, and an SOM that inputs the parallel signals and outputs an SOM detection signal. a detector, a phase detector that inputs the SOM detection signal and outputs a phase information signal, and a serial signal from which phase ambiguity dust is removed by inputting the phase information signal and the serial signal from the demodulation board to the P8. and a phase ambiguity corrector that outputs.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to nine drawings. FIG. 1 is a block diagram showing an embodiment of the phase ambiguity dust removal circuit of the present invention.

The serial-to-parallel converter circuit 1 receives an A channel input signal (input from the outside via the input terminal 95) 1 containing nine phase errors.
01 is input, and 16 columns of delayed signals 106 from 1 bit to 16 pits are output. Similarly, the serial/parallel converter circuit 2 is B.
Input channel input signal 102 and delay signal 1 of 16 columns
Enter 03 and enter SOMA, SOMAC, SOMB.

Four SOM detection signals of SOMB'(6+OMA'(B
C) outputs SOM) 105 when the polarity of A(B) is reversed. Similarly, the SOM detector 4 receives the delayed signal 104 and outputs four SOM detection signals 106. The phase detector 5 receives the SOM detection signal 105 from the SOM detector 3 of A channel, and the SOM detection signal 105 of B, the SOM detector 3.
Input the SOM detection signal 106 from the OM detector 4,
A/leave pulse, ambiguity A pulse.

Six phase information signals 107 of ambiguity B pulses
Output. The phase ambiguity corrector 6 is.

A input signal 101. B Taeyang Lee Input Signal 102. A channel BOM detection signal 105, B channel SOM detection signal 106° phase information signal 10
71 input acceleration signal 108 and input clock signal 109.

A phase ambiguity removed output signal 110 and a B channel phase ambiguity removed output signal 111 are output. In this embodiment, the SOM detector 3.4 and the phase ambiguity corrector 6 are each connected to 64 bits or more of large capacity ROM 1.
I try to make it consist of individuals.

Next, the operation will be explained.

First, let me explain the general operation of one circuit.

The received serial signals DATA-A and DATA-B are not necessarily the transmitted serial signals DATA-A and DATA-D sent from the partner station.
It is not necessarily the same as ATA-B. This is because eight types of ambiguity occur during the process of four-phase phase demodulation in the demodulation board. This circuit corrects this ambiguity and re-emits correct data. Ambiguity correction is controlled by a control signal of a selector within the phase ambiguity corrector 6. Table 1 shows the relationship between the states of the control signals of these selectors and phase ambiguity correction.

Table 1 Now, 1. Normally, a SOM no< turn is added to the beginning of the data. By detecting this SOM, this circuit detects an ambiguity state and outputs a corresponding pulse for ambiguity correction, which sets the state of the control signal of the selector to the required value. In this way, correct data is reproduced from the next pit of the SOM.

Next, the operation of each block will be explained.

The A channel input signal 101 whose ambiguity remains uncorrected passes through the serial-to-parallel conversion circuit 1 and is converted into a SOM as a delay signal 103 in 16 columns from 1 bit to 16 bits.
Input to detector B. The SOM detector 3 detects the SOM of A channel and L (SOMA), and the SOM detector 4 detects the SOM of B chaff /l and /L/ (SOMB). However, as mentioned above, the beginning of the burst enters the serial/parallel converter circuit 1.2 without ambiguity being corrected. Therefore, it is necessary to detect the SOM (SOMA') when the polarity of the A channel is reversed and the SOM (SOMB') when the polarity of the B channel is reversed.

The four types of patterns to be detected are as follows.

SOMA:0010000001110101SOMA
C:1 1011 1 1 1 1 0001 01
0soMB:0001010011011100SOM
B': 1 1 1 01 01 1 001 0001
1. On the other hand, the SOM pattern changes not only due to ambiguity in the demodulation board, but also due to code errors in the satellite link. On the other hand, it is necessary to ensure stable frame synchronization even if the condition of one line becomes considerably poor. Therefore, even if there is a 1-bit or 2-bit error in each of the 16-bit patterns, it is necessary to detect it as an SOM.

Therefore, the output signal SOMA of the SOM detector 3.4,
SOMA', SOMB, SOMB' are used under the following conditions.
It becomes 1″.

SOMA: 16-pit address input cover turn is SOM
Completely matches pattern A.

Or they differ by only 1 bit. Alright are different by only 2 bits.

SOM A': The 16-pit address input cover pattern completely matches the pattern of SOMA' or differs by only 1 bit. Or when they differ by only 2 bits.

SOMB: 16-bit address input card (turn is SO
Exactly matches or differs by 1 bit from MB's pattern. Or when they differ by only 2 bits.

SOMB': The 16-bit address input cover pattern completely matches the pattern of SOMB' or differs by only 1 bit. Or when they differ by only 2 bits.

Next, the 1-phase detector 5 detects phase information by analyzing the output signals 105, 106 of the SOM detector 3.4 and detects the ambiguity A pulse.

Ambiguity B Pulse, Interleaved Pulse 3
The ambiguity correction pulse of the type is output to the selector of the phase ambiguity corrector B. In this way, the control signal of this selector becomes correct and the ambiguity is corrected. Table 2 shows the relationship between the SOM detection signal and the phase information signal.

Table 2 Next, the 1-phase ambiguity corrector 6 is composed of an 8-channel selector and a control section that use the six types of phase information signals as control signals.

FIG. 2 is a block diagram showing the configuration of the control section.

The 30M pattern detector 71 inputs the Af Yangyi Lu SOM detection signal 105 and the B channel SOM detection signal 106 and outputs the BOIA pattern detection signal 701. The gate pulse generation circuit 72 receives the input acquisition signal 108
and reception clock signal 111, and outputs gate pulse signal 702. The AND circuit 73 inputs the SOM pattern detection signal 701 and the gate pulse signal 702,
A signal 703 having the value of the logical product of these two signals is output. The knot circuit 74 inputs the received clock signal 111 and outputs a signal 704 having the inverse of this signal. The retiming circuit 75 receives the received clock signal 111, the signal 703, and the signal 704, and receives the retiming signal 703.
Outputs 05. AND circuit 76 outputs retiming signal 7
05 and signal 704.

A signal 706 having the logical product of these two signals is output. The delay circuit 77 inputs the ambiguity detection signal 107 and the reception clock signal 111 and outputs a delayed signal 707. The latch circuit 78 is connected to the delay signal 707 and the signal 70.
6 is input, the value of the delayed signal 707 is stored and held until the next signal 706 comes, and the value is output as the selector control signal 708.

Next, the operation will be explained.

First, the 30M pattern detector 71 is SOM A.

4 of SOM A', SOM B, SOM B'
The SOM pattern detection signal 701 is output only when any one of the types of SOM detection signals is input to both channels A and B at the same time. However, as mentioned above, 30
Since the M pattern allows up to 2 bit errors out of 30M patterns of 16 bits each, SO
SOM pattern detection signal 70 at the 16th bit position of M
1 is not necessarily output.

For this purpose, the gate pulse generation circuit 72.

A gate pulse signal 702 that becomes 1' only at the 16th bit position of the SOM using a shift register and an AND gate.
Output. therefore.

The output signal 703 of the AND circuit 76 becomes 1'' only when the SOM pattern detection signals 105 and 106 of both channels A and B are simultaneously input at the 16th bit position of the 30M pattern.

Further, the retiming circuit 75 outputs a signal 705 which is obtained by retiming the signal 703 using a flip-flop.
The delay circuit 77 outputs a signal 707 that is the delay of the agility detection signal 107 by the amount that the signal 706 is delayed by the retiming circuit 75 . The latch circuit 78 is composed of three flip-flops, inputs the delayed signal 707 and the signal 706, and inputs the delayed signal 707 directly to the next signal 7.
It is stored and held until 06 arrives, and outputs that (direct) to the 8-channel selector as a selector control signal 708.

It goes without saying that the present invention can be applied even if the length of the 30M pattern is other than 16 bins.

〔Effect of the invention〕

As explained above, the phase ambiguity removal circuit of the present invention uses a large-capacity ROM to perform SOM detection independently for both channels A and B.

Conventional parallel column conversion circuits and 63-bit shift registers are no longer necessary. Furthermore, since the 9-phase ambiguity detection is also performed in the ROM, the conventional gate circuit is not required. In this way, there is an effect that performance equivalent to that of the conventional method can be obtained with a simple and economical circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the phase ambiguity removal circuit of the present invention, and FIG. 2 is a block diagram showing the configuration of a control section in the phase ambiguity corrector shown in FIG. 1.

Claims (1)

[Claims] 1. A serial-to-parallel converter circuit that converts two columns of serial signals from the PSK demodulator into N columns of parallel signals, and a SOM (Start of Message) circuit that inputs the parallel signals.
) A SOM detector that outputs a detection signal, a phase detector that inputs the SOM detection signal and outputs phase information, and inputs the phase information signal and the serial signal from the PSK demodulator to calculate the phase ambiguity. A phase ambiguity removal circuit comprising: a phase ambiguity corrector that outputs a serial signal from which .