JPS5815353A - Data demodulation circuit - Google Patents

Abstract

PURPOSE:To constitute a circuit with counters and memories of a low speed and to realize a demodulation circuit with high reliability, by converting an input data modulated with a CPU into a parallel data and storing the data to memories, and transferring the data to a plurality of shift registers. CONSTITUTION:A data demodulation circuit demodulating a digital data is provided with a CPU12, which controls a serial/parallel conversion shift register 11 and the modulated input serial is converted into a parallel data. The converted parallel data is once stored in an RAM13, the stored parallel data is read out to an input and output port 17, an output of the port 17 is selected under the control of the CPU12 and stored in a plurality of shift registers 18-25. The data stored in the registers 18-25 are circulated via input and output ports 26 and 17, the CPU12 controls a decoder circuit, the data in the register 18-25 are simultaneously read out to the port 26 when the transfer of data fetched to the RAM3 is finished, allowing to make the demodulation of data easy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data demodulation circuit that demodulates interleaved and transmitted digital data.

In devices that transmit digital signals, various modulation means are used to prevent errors that occur during transmission, and one of the most effective methods is a method of interleaving data. The bit arrangement (a) of this digital data before interleaving and the (modulated) bit arrangement after interleaving are shown. Here, the horizontal direction represents time, and the symbol D1j indicates information that continues after control data C. In the data, Dl, , D, .

@1pD1y$Dt@tDm鵞y °１會D鵞y+ ``bow I) 341tI) 8419 9-bit array (
b) The information data Dij is Dxew on the edge of the control data C.
Dtt"・sDmse*Ds**1Dtt eD*x
t・@'eDssttDs+t l@″：DrveD
Eight sets of 34-bit data are rearranged in the INK format, such as DssveDsnv.

The bit arrangement of the above-mentioned pre-interleaved O information data is as follows:
One set of 8-bit data consists of 4 bits for information and 4 bits for correction.
It is made up of bits, and is configured so that it can correct an error in one of these bits.

By transposing the data arrangement using bottle interleaving and transmitting the data, it is possible to prevent bit errors caused by narrow pulse-like noise such as burst noise generated from automobiles and the like. For example, without modulation, Figure 1 (a)
), if two or more bits of data within each 8 bits are transmitted (received) incorrectly due to burst noise generated from automobiles, etc., the system will no longer be able to be corrected. , I ended up having to process nine incorrect data. If we assume that the information data is rearranged (modulated) as shown in the diagram above and then transmitted,
Even if one set of each word PiF is completely destroyed, 8
Deinterleave (demodulate) one set of bits to the original.

When the data is returned to the data array, the errors are dispersed, and even one pit error in each set of 8 bits can be corrected multiple times.

Transmitting data in such an interleaved manner is effective against burst noise.

Figure 2 shows a conventional example of a circuit that rearranges this interleaved and transmitted data to the original data arrangement (data arrangement before modulation on the transmission side). . This data demodulation circuit is configured as follows.

Input terminal IK Large Input data is input to the input terminal of random access memory (hereinafter referred to as RAM) 2 that can be read and written at high speed, and ζ (7) Address that specifies the address of each memory cell in RAM Z The first output end of the clock regeneration circuit 3 is connected to the input end of the gate generation circuit 40, and the 20th clock output end is One end of each of the interlocking first and second changeover switches 5 and 6 5 A
t 6 A y-11 continued. The common terminals of these changeover switches 5 and 60 are connected to the input terminals of advance and octal counters 7 and 8, respectively, and the output terminal of this advance counter 7 is connected to the address terminal on the lower side of the high-speed RAM 2. It is connected to the input terminal of the decoder 9 of tIXl. The output end of the octal counter 8 is connected to the upper address end of the high-speed RAM 2, and is also connected to the input end of the second decoder IO.

The output terminals of the first and second decoders 9 and 10 are respectively reset terminals 7R and 8 of the arithmetic and octal kakuntas 7 and 8.
It is connected to SR, and also to the other terminals 6B and 5B of the changeover switch 6.5.

These changeover switches 5.6 are constructed to be controlled in conjunction with the output signal of the gate generation circuit 4, and are constructed so that demodulated data is output from the output end of the high speed RAM 2.

The operation of the conventional example configured as above will be explained below.

According to the control data C input to the input terminal 1, the clock regeneration circuit 3 supplies its output signal to the gate generation port wj4, and the gate generation circuit 4 turns on the common terminals of the switching switches 7B and 6, 5 and 6B, respectively. do. Then, the control data input terminal then inputs the information data Dlja high-speed RA.
MIC) The information is sequentially input to the data input terminal, and the address of the information D changes sequentially. Therefore, the input information data D1j is sequentially stored in RAM! will be written into. On the other hand, the output of the advance counter 7 is also input to the input terminal of the first decoder 90, and the output terminal of the first decoder 9 is inputted by the digital signal of the u-way carantuff corresponding to 0 to which one information data D1j is input. outputs a pulse signal, and this signal sets the advance counter 7 to ν and returns the advance counter 7 to the candy-like state 11, and also acts as a four-clock signal to the octal O counter 8. This octal counter 8 uses the output signal of the #Il decoder 9 as a clock, and sequentially supplies the binary code from its output terminal to the upper address terminal of the RAM 2, and modulates one set of M pits. Nine information data Di
j is RAM! are sequentially written within. This octal counter 8 also sequentially supplies address signals to the second decoder lO, and when eight digital signals are supplied from the octal counter 8, its output terminal outputs a pulse signal, and this signal resets the octal counter 8 and finishes scattering the data input from the input terminal 1.

In the case of taking in data input from the Tsumaya Inmandan 1, the counter 7 of the control operates as a counter for specifying (selecting) a lower-order address, and the counter 8 of 8-way operates as a counter for specifying an address of an upper-order side. It turns out.

When the input terminal IK digital signal is no longer input, the gate generation circuit 4 connects each common terminal of the changeover switches 5 and 6 to 5B.
, 6A sides are switched on, respectively, to set the read mode in which the data stored in the RAM 2 is demodulated and outputs 9 data.

In this data readout mode, the cost is first input to the octal counter 8, and the upper addresses of the RAM 2 are sequentially specified, and the data in the memory 7 specified by the addresses are sequentially read out. read out. When eight clocks are supplied, a pulse signal is output from the decoder 10, and this pulse signal not only resets the octal counter 8 but also serves as the clock for the 34-ary counter 7. In this way, the nine data are stored as Dl
o * Do e..., D3. are output sequentially and K after nine
Due=D□, . . . , Do are sequentially output.

In this way, the nine data stored in Klj are revealed, and D
When I4f is output, the decoder 9 resets the counter γ of the digit number. In this way, the data inputted in K111 as shown in FIG. The data array is read out sequentially. Tsut
In the conventional example that operates in this way, the data acquisition process is performed in real time during data transmission, so the KRAM 2 and the 34-decimal counter 7 are capable of high-speed processing. For example, if the required data transmission rate is 5.7 M (Hz), the data width is approximately 17
It has the drawback that the access time of RAM 2 needs to be relatively fast, and that high-speed processing tends to lead to a decrease in operational reliability. Also, since the RAM 2 and the counter 7 require high-speed operation, they also have the disadvantage of increasing the push-pull rate. This W14 was created in view of the above points, and uses a central processing unit to perform this function. It is an object of the present invention to provide a data demodulation circuit that converts input digital data that is modulated according to instructions from a central processing unit into parallel data, and that uses the parallel data to process data in and out of memory at low speed. purpose.

The present invention will be explained below with reference to the embodiment shown in FIG. The embodiment of the present invention is configured as follows.

Reference numeral 11 denotes a shift register for serial/parallel conversion, which has the function of outputting interleaved (modulated) input serial data as parallel data, for example 8 pieces at a time, as shown in Figure 1'(b), and in some cases. It also has a function to output parallel data as serial data, and these functions are controlled by the central processing unit (hereinafter referred to as CPU) 12. The output terminal is CPU12 and RAM1 for calculation.
3 and the read-only message for the program (referred to below as R).
It's called OM. ) 14 and are connected to each other by a data/(sline 15 and an address path line 16). Reference numeral 17 is an input/output port of III, and its input end is connected to the data path line t. The (eight, for example) output terminals are connected to the respective first data input terminals of the (also eight) shift registers 18 or sections. It is configured to control the input/output board 17, select nine data supplied to its input terminal, and output it only to that specific output terminal (as shown), and that specific output nJK is connected. Shift register (18 to 25
The data supplied to the data input terminal of any one of the shift registers 1B to 25 is configured to be accommodated by the clock supplied to each clock terminal CK of the shift registers 1B to 25. Each data output terminal Do of these shift registers 18 to 25 is connected to a parallel input terminal of a second input/output board so that data outputted from each output terminal Do of these shift registers 18 to 25 can be processed in parallel. The output terminal of the port is connected to the data path line 15. Each of the output terminals Do of the shift registers 1B to 4 is connected to the respective second data input terminal, so that the input data is outputted from each output terminal and is circulated and held without being lost. It is composed of The first and second data input terminals of these shift registers 18 and 18 are configured to be the same as the input terminal of a two-man OR circuit.

Also, each reset terminal R of these shift registers 18 to cram school
The stored data (by the CPU 12) can be cleared.The operation of the embodiment of the present invention configured as described above will be described below.

The interleaved serial data is sequentially taken in by a shift register U for serial/parallel conversion, and outputted in groups of, for example, eight (but not limited to) to the RAM 13 for calculation as parallel data. Data is stored in the shift register U by controlling a clock (not shown) by the CPU 12. Thereafter, an address signal is supplied to the RAM 13 by a counter (as shown), and data is written.
12 is performed by controlling the program ROM 14. In this way, RAM 13 is interleaved (
When the input of the modulated data is completed, the CPU 12 stores the data written in the RAM 13 in the
At this time, the CPUL2ti decoder circuit (as shown) is controlled so that data is supplied only to the first data input terminal of the shift register 18, and the clocks of each shift register 18 and terminal CKK
Supply clock. Out of the data stored in the RAM 13 in this way, the D is stored in a specific shift register 18.
□、D! . +D3°, ..., D, 4° are accommodated.

In this case, the data supplied from each output terminal Do to the other shift registers 19 to 25 is inputted to the second data input terminal, respectively, but this is the same as the data inputted to the first input terminal. Since it is at a low level, it is the same as no data being input. Also, before data is taken in, each reset terminal RK is supplied with a reset signal, and each register 18 and section are cleared.
After completing the loading, the CPtJ12 controls the input/output port 17 (from the RAM 13) and transfers the shift register 19.
A clock is supplied to each clock terminal CK of shift registers 18 to 25, and an address signal is supplied to RAM 13, so that data is supplied only to RAM 1.
The data written in 3 is read out. In this way, the data D11#D□, D□ are stored in the shift register 19.
,...@D,4. The names are accommodated sequentially. Thereafter, in the same way, the remaining shift registers are added to 25 and interleaved (
All the data that has been modulated and taken into the RM M13 has been transferred. In other words, data D in the shift register,
, .

D17. . . , D□, are sequentially accommodated to complete the data transfer.

Next, the CPU 12 inputs the first KID data among the data stored in the diad registers 18 to 25, that is, the shift registers 18, 19°...-, 25 receives data Dlo + Dtt *..., DI. The above-mentioned data D, which are simultaneously outputted to the second input/output boat 26 and supplied to the input/output boat 26, respectively. ,D,1,・
..., Dl, is read.

Next, the CPU 12 outputs the second data D of the data stored in the shift registers 18 and 18.
,. tD! 11...e Dl9 is simultaneously outputted to the second input/output boat 26, the data Dso s Dt1*...eWv supplied to this input/output boat 26 is read out, and if this operation is repeated, the first As shown in Figure (a). , DI, s...+ D+y r
Dl.

D□,...,D□,...,D,4...,D□
The modulated data is arranged in the order of .

In embodiments of the invention which operate in this manner, the series
Only the shift register 11 for parallel conversion needs to have an operating speed that enables it to take in data input at a predetermined (high) speed, and the operating speed of the arithmetic RAM 13 is relatively slow compared to that operating speed. can fully perform its function. In this case, the capacity of the serial/parallel conversion shift register 11 is about 8 bits (this number can be changed significantly), so the operating speed is several M (Hz) as described above. It is inexpensive and easy to obtain, and there will be no problem when operating at higher speeds1. In the above embodiment, a predetermined number of information data, that is, 8 pits, is used. Since the example corresponds to 1"j for one set of data, 8 shift registers 18 or units are used, but if the number differs from the above, the number of shift registers 18 or units should be adjusted accordingly. If you use it, you will mourn.

As described above, according to the present invention, when a CPU is used, input modulated data is converted into parallel data and temporarily stored in a memory, and this stored data is transmitted through multiple shifts. This is a circuit that transfers it to the register, reads this transferred data, and demodulates it.
Since it does not require high-speed operation using a high-speed counter and memory as in the past, it is possible to realize a highly reliable demodulation circuit, and it can also be configured with a low-speed counter and memory, reducing costs. It has the advantage of being possible. Furthermore, since the KCPU is used, there is an advantage that it can be used for other functions as well.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the arrangement of information data before and after interleaving (modulation), Fig. 2 is a circuit diagram showing a conventional example of demodulating modulated data, and Fig. 3 is an implementation of the data demodulation circuit of the present invention. FIG. 2 is a circuit diagram showing an example. 11...Serial/parallel conversion shift register 1.2...
・CPU 13...RAM 17, 26...I/O board 18 to Shift register

Claims (1)

[Claims] A data demodulation circuit that demodulates digital data transmitted by changing the data arrangement includes means for converting the input digital data into parallel data, means for capturing this parallel data, and a plurality of means for storing the stored data in a shift register; and means for outputting the stored data from the plurality of shift registers;
Il! Data demodulation circuit with l characteristic