JPS62271264A - Digital audio reproducing device - Google Patents

Abstract

PURPOSE:To miniaturize the circuit scale of a device, and to attain an accurate correction process, by transmitting a maximum value data having the sign opposite to that of the audio data just before, instead of an audio data, and performing a correction process by a correction circuit without using a correction flag, when an error is detected by an error detection circuit. CONSTITUTION:When the audio data in which an error is detected is inputted at a detection circuit 3, the maximum value data having the reverse code of the audio data before one sample period is inputted to a a latch circuit 8 instead of the audio data. The audio data, and e maximum value data outputted from the latch circuit 8 are inputted to a correction circuit 10, and when the data is the maximum value data, the correction circuit 10 identifies that an inputted data is a substitutional data for the audio data in which the error is detected by the fact that the data is changed to the maximum value data having the reverse code of the data before one sample period, and performs the correction process by using the data before and behind. In other words, the correction process can be performed without referring an error flag more exactly than a conventional method.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention detects errors in digital audio data reproduced in chronological order from a magnetic tape or the like, and based on the result of the detection, The present invention relates to a digital audio playback device that corrects data and outputs the corrected data to a subsequent circuit.

[Conventional technology]

Conventionally, digital audio playback devices of this type, such as 8mm video tape recorders and compact disk players, input digital audio data played back in time series from a magnetic tape or the like into an error detection circuit, for example, in units of correction processing. The detection circuit detects errors in the input audio data using the CRC code, etc., generates a 1-bit correct/incorrect flag, that is, an error flag indicating correctness, and corrects the audio data after the detection. The audio data is transmitted to a circuit, the error is corrected, and the corrected audio data is transmitted to a subsequent circuit.

The correction process of the correction circuit is performed by one of the following two methods.

(1) A method in which an error flag from an error detection circuit is transmitted together with audio data to a correction circuit, and the correction circuit corrects the audio data by referring to the error flag.

(2) Transmit only audio data to the correction circuit,
At this time, the data pattern of the audio data for which the error flag has been generated is changed to a preset error pattern, for example, a pattern in which all bits are set to 1.The correction circuit identifies the erroneous audio data and performs correction processing. how to.

Note that the method (1) above is applicable to, for example, "Sanyo T'
y Nika/l/L/By-VOL, 17 &, 2
J (published August 1985), page 42, Figure 69.

[Problem that the invention seeks to solve]

By the way, when performing correction processing using method (1) above, the amount of data transmitted from the error detection circuit to the correction circuit is (
Compared to the case of performing correction processing using method 2), there are more error flags, and it is necessary to provide a dedicated memory for error flags (to RA 8), which reduces the memory capacity within the device and the number of pass lines. There is a problem that the number of circuits increases and the circuit scale increases.

On the other hand, when performing correction processing using method (2) above,
One of the data patterns formed by audio data
Since one error pattern is set in advance as an error pattern, for example, there is a risk that audio data with the same correct data pattern as the error pattern will be incorrectly corrected. However, there is a problem in that the amount of information in the audio data decreases and the quality deteriorates.

[Failure to solve the problem]

The present invention has been made with the above-mentioned points in mind, and includes detecting errors in digital audio data reproduced in time series, and correcting the audio data based on the result of the detection to correct the errors in the subsequent circuit. In the digital audio playback device that outputs the audio data, there is an error detection circuit that detects errors in the played audio data and generates a correct/incorrect flag, and the audio data that has passed through the detection circuit is input, and the error detection of the next audio data is performed. It consists of a latch circuit that holds input data until the end of the input data, and an inverter for the number of bits of audio data.7 The most significant bit indicating positive or negative of the input data of the latch circuit is inverted to generate positive or negative maximum value data. and an inverting circuit provided between the detection circuit and the latch circuit, and transmitting the maximum value data to the latch circuit in place of the audio data output from the detection circuit when the correct/incorrect flag is an error flag. The output data of the latch circuit and the information selection concave circuit are input, and the maximum value data is identified and reproduced from the sign and content of the input data.

[For production]

For the output digital audio data, maximum value data of the maximum values opposite to the positive and negative values of the audio data immediately preceding the audio data is transmitted to the correction circuit.

〔Example〕

Next, this invention will be explained in detail with reference to FIG. 1 showing one embodiment thereof.

In Figure 1, (1) is an input terminal into which N-bit digital audio data reproduced in time series from a magnetic tape etc. is input in bit serial format, and (2) is an input terminal (1
), which outputs input audio data in N-bit parallel format. In addition, MSB in the figure.

LSB indicates the most significant bit line and the least significant bit line of N bits.

(3) is an error detection circuit connected to the conversion circuit (2), which detects errors in the input audio data using the CRC code of the data, etc.
When I II is positive, a 1-bit error flag of IT OII is generated, and the generated error flag is output to a flag latch circuit to be described later.

(4) is a flag latch circuit into which the error flag of the detection circuit (3) can be inputted, and the error detection of the next audio data is completed by the detection circuit (3) based on the first latch pulse signal of the input terminal (5). The input error flag is held and output for one sample period until the error flag is input.

(6) is a first latch circuit for data connected to the detection circuit (3), and based on the first latch pulse signal of the input terminal (5), the audio data input through the detection circuit (3) is It is held with a delay of one sample period and output.

(7) are N 2-bit selectors (7a) equipped with 2 input terminals (a), (b) and a switching control terminal (S);
..., (7n), and a latch circuit (in the input terminals of each selector (7a) to (70)).
Til+ is an error flag inputted with each bit of the audio data outputted from 6) and outputted from the latch circuit (4) to the switching control terminal (S).

Based on +101+, when the error flag is 1'', the input terminal is switched to one input terminal (a), and when the error flag is 0'', the input terminal is switched to the other input terminal (a).

(8) is a second latch circuit for data connected to the output terminal of each selector (7a) to (7n), and based on the first latch pulse signal, N-bit output data of the selection circuit (7) is sampled. Hold and output after a period of delay.

(9) is N inverters (9a), ..., (9n)
The most significant bit of the output data of the latch circuit (8) is input to each inverter (9a) to (9n), and each inverter (9a) to (90) transfers the output data to the latch circuit (8). N-bit positive or negative maximum value data obtained by inverting the most significant bit of the output data of , that is, maximum value data in which all bits are 1'' or 0''1, is input to each inverter (9a) to (9n ) outputs each bit of the formed maximum value data to the input terminals (a) of the selectors (7a) to (7n).

αG is a correction circuit to which the output data of the latch circuit (8) is input, and it compares the positive and negative signs of the output data one sample period before and the input output data, and the contents of the input output data. Based on this, erroneous data is identified and corrected, and corrected N-bit audio data is output.

aQ is a third latch circuit for data into which the output data of the correction circuit (IQ) is input; based on the second latch pulse signal at the input terminal, the input data is delayed and held for one sample period and output.

The fourth latch circuit for data is connected in series to the latch circuit q, and receives input data for one sample period according to the second latch pulse signal 'rK4! Delay and output.

The mark is an N-input AND gate into which each bit of the output data of the latch circuit αυ is input, aQ is the N-input Nants gate into which each bit of the output data of the latch circuit qD is input,
(1 is an inverter that inverts and outputs the most significant bit of the output data of latch circuit 01), α is an inverter αη
09 is an AND gate into which the output signal of the latch circuit Qυ and the output signal of the OS are input, and 09 is an AND gate into which the signal of the most significant bit of the latch circuit Qυ and the output signal of Q are input. Gate Q8), O'l
This is an OR gate into which the output signal of is input.

t2]1 is an AND gate α9. This is a flag re-formation circuit formed by αQ, 09, Nant gate αG, inverter 0″?), and OR gate ■, and a latch circuit flu).
Based on the output data of Q3, the error flag is re-formed based on the audio data output from the correction circuit.

The audio data inputted to the input terminal (1) in bit serial form is transferred from the conversion circuit (2) to the detection circuit (3).
), and since the audio data is AC signal data, the most significant bit of the audio data output from the conversion circuit (3) indicates whether the data is positive or negative. When it is negative, it becomes "°1'", and when it is negative, it becomes 11011, and the range from the maximum positive value where all bits are "°'1" to the maximum negative value where all bits are "°0", that is, N The bits vary over the entire data pattern they form.

Furthermore, the detection circuit (3) detects an error in the input audio data using the CRC code of the input audio data. An error flag is generated and the error flag is input to the latch circuit (4).

Also, if no error is detected, i.e. the latch circuit (
When the error flag of EI OIT is output from 4), each selector (7a) to (7n) is held at the input terminal (b), and at this time, the detected audio output from the detection circuit (3) Data is input to the latch circuit (8) via the latch circuit (6) 1 selection circuit (7).

By the way, since the latch circuits +61 and (8) operate simultaneously by the first latch pulse signal, the detection circuit (3
) is input to the latch circuit (6), the latch circuit (8) outputs audio data one sample period before.

Therefore, each inverter (9a) to (9) of the inverting circuit (9)
n) always receives the most significant bit of the output data of the latch circuit (8) one sample period before.

Then, when an error is detected by the detection circuit (3) and the latch circuit (4) outputs an error flag of 1'',
Each selector (7a) to (7n) is switched to the input terminal (a), and at this time, the selection circuit (7) selects a substitute for the audio data output from the latch circuit (6), that is, the audio data in which an error has been detected. The N-bit data output from the inverting circuit (9) is input.

If the audio data one sample period before the audio data in which the error was detected is positive data, that is, the most significant bit is 1'', then the total pip indicating the minimum value) IT O11 negative maximum value Data is reversed (9
), and conversely, if the audio data one sample period before the audio data in which the error was detected is negative data, that is, data whose most significant bit is 0'', all the pixels indicating the maximum value are output. The maximum positive value data of "M" is output from the inverting circuit (9).

Therefore, when audio data in which an error has been detected is output from the detection circuit (3), instead of the corresponding audio data, the latch circuit (8 ) is entered.

Then, the audio data and maximum bamboo data output from the latch circuit (8) are input to the correction circuit QG, and the correction circuit αq, when the input data is maximum value data,
Since the input data is the maximum value data with the opposite sign of the data input before the l sample period, it is identified that the input data is data that replaced the audio data in which the error was detected, and the input data is Correction processing is performed using the data before and after. Note that for data that cannot be corrected, the input maximum value data is output as is.

By the way, in the case of audio data in which no error is detected, the data input to the correction circuit qO will be data that has a correlation with the previous and subsequent data, and will be the maximum of the opposite sign of the data input one sample period ago. Value data is rarely input to the correction circuit αG, especially audio data for an analog audio signal with a frequency up to 1/4 of the sampling frequency used to form audio data.

Therefore, the correction circuit QG performs correction processing more accurately than the conventional method (phantom method) by using the entire N-bit pattern as the audio data pattern without referring to the error flag.

Then, the data corrected by the correction circuit GO is transmitted to the interpolation circuit etc. via the latch circuits 0υ and C13. At this time, since an error flag is required for the interpolation process, in this embodiment, the correction circuit 00 The error flag is re-formed by the re-formation circuit 121) based on the output data of.

In other words, if the correction cannot be completed through the correction process,
The correction circuit 00 also has a latch circuit (1υK), and the input maximum value data is output.

Then, when the output data of the latch circuit aυ becomes the positive or negative maximum value, the output signal of the ant gate (15) or the output signal of the gate αG becomes 1°I+'.

On the other hand, data one sample period before the output data of the latch circuit αυ is output from the latch circuit 03.

Then, the signal of the most significant bit of the output data of the latch circuit α1 and the signal obtained by inverting this signal by the inverter (17) are input to the AND gates α'J, Q8), respectively, and the AND gates 128 and QcJ are input to the AND gates α'J and QcJ. (
15.

Since each output signal of the Nandt gate αQ is input, when the latch circuit α outputs maximum value data with a positive or negative sign opposite to the data from one sample period ago, that is, maximum value data that has not been corrected. In, anime games
The output signal of the 10th stage or Og becomes "I'', and the OR gate E outputs an error flag indicating whether the output data of the latch circuit q3 is correct or incorrect.

Therefore, the error flag generated by the detection circuit (3) is not transmitted to the correction circuit qa.
This allows correction processing to be performed based only on the input data, reducing the memory capacity of the device and the number of path lines, reducing the circuit size. In this case, since the maximum value data with the opposite sign to the data from one sample period ago is input to the correction circuit 00, correct audio data and errors are detected using the pattern of positive and negative maximum values of the audio data. Therefore, it is possible to accurately identify and correct maximum value data instead of audio data, and accurate correction can be performed without reducing the amount of information in the audio data.

As mentioned above, the frequency that can be accurately identified and corrected is 174 or lower than the sampling frequency of audio data, but for example, when applied to a compact disc player, the sampling frequency is 4
Since the frequency is 4.1 KHz, correction processing can be performed without error on analog audio signals with frequencies of 11 or lower, and since analog audio signals usually have almost no components of 10- or higher,
In practice, this does not cause any inconvenience.

In the above embodiment, the latch circuit (8) was provided together with the latch circuit (6), but the latch circuit (8) may be omitted, and even if the subsequent circuit of the correction circuit αG is different from the embodiment, the latch circuit (8) may be omitted. Of course it's good.

〔Effect of the invention〕

As described above, according to the digital audio playback device of the present invention, when an error is detected by the error detection circuit, the maximum value data with the opposite sign of the previous audio data is sent to the correction circuit instead of the audio data. By transmitting the information and performing correction processing without using a correct/incorrect flag using a correction circuit, it is possible to reduce the circuit scale of the device and perform accurate correction processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the digital audio playback device of the present invention. (3)...Error detection circuit, (4)...Flag latch circuit, +61, (8'l...Data ambient temperature 1. second latch circuit, (7)...Information @ selection circuit , (9)...
- Inversion circuit, 00...correction circuit.

Claims (1)

[Claims] (1) In a digital audio playback device that detects errors in digital audio data played back in time series, corrects the audio data based on the detection result, and outputs the corrected audio data to a subsequent circuit. an error detection circuit that detects an error in the error detection circuit and generates a correct/incorrect flag; a latch circuit that receives audio data that has passed through the detection circuit and holds the input data until error detection of the next audio data is completed; an inverting circuit comprising an inverter with a number of bits and inverting the most significant bit indicating positive or negative of the input data of the latch circuit to generate positive or negative maximum value data; and a combination of the detection circuit and the latch circuit. an information selection circuit that is provided between and outputs the maximum value data to the latch circuit instead of the audio data output from the detection circuit when the correct/incorrect flag is an error flag; What is claimed is: 1. A digital audio playback device comprising: a correction circuit that identifies the maximum value data from the code and content of the input data, detects error data, and performs correction processing on the error data.