JPS61296572A - Time base correcting device - Google Patents

Abstract

PURPOSE:To decrease propagation of an error by using an address count-up address without using a synchronous address when the continuity of the synchronous address with a just preceding content is lost and it is the error only once. CONSTITUTION:The synchronous address 21 read by a synchronizing signal is compared with a value added by one block to a count of a preceding clock at an adder 24 by a comparator 25. When they are equal as the result of comparison, the content of the synchronous address is loaded to a counter 10. When the result of comparison is equal at the preceding block and different in this case, the counter 10 does not load the synchronous address and the block content counted up automatically is outputted. When the synchronous address is '3' as B shown in figure and the counted-up value is '5', for example, the comparator 25 outputs a dissident signal '1'.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention is used for recording and reproducing in a storage device of an information processing device, and is a time axis for absorbing jitter that occurs when recording and reproducing digital signals in a magnetic recording and reproducing device. The present invention relates to a correction device. (Prior Art) FIG. 4 shows a conventional example of this type of time base correction device. A read address generator 6 generates a read address according to the reference signal 2. On the other hand, the synchronization signal detector 7 detects a synchronization signal other than the input signal 1. The synchronous address reader 8 reads out the synchronous address from the input signal for each synchronous signal. A write address is generated in the counter 10 from this synchronous address. The read address and write address are selected by the selector 9, the input signal 1 is written into the storage device 4, and read out again.
The time axis is corrected. Now, it is possible to add synchronization information and synchronization address information to data of about 200 to 1000 bits.1) t-1
Consider a time axis correction device that absorbs jitter (time axis fluctuation) of ±4 blocks. Assuming that there is a time difference of 4 blocks between the write address and the subsequent address, the result will be as shown in FIG. Figure 5 shows the synchronization address "0" corresponding to the synchronization signal.
For example, a write address "5" is read out as a read address "5" with a delay of 4 blocks. (Problem to be Solved by the Invention) However, the above-mentioned conventional time axis correction device mistakenly reads out the "5" block as the "3" block in the synchronous address reader, as shown in FIG. 6, for example. Assuming this, the data originally written in the "5" block is read into the "3" block output from the time axis correction device, and the data that was originally written in the "5" block of the time axis correction device is read out from the input signal. Ninety eight
The data of "5" block before the block is read again. (Nothing should be written to the "5" block within the same cycle.) Generally, the synchronization signal

[Compared to this, there is a high probability of an error in the synchronization address, so even if only the synchronization address is incorrect, the entire data of two blocks may be incorrect, which is a problem. The purpose of the present invention is to completely reduce the propagation of errors by not using all of the synchronization addresses when the synchronization address loses continuity with the immediately preceding content, and when it is a one-time error. The purpose of the present invention is to provide a time axis correction device that can perform the following steps. (Friendly Means for Solving Problems) In order to achieve the above object, the time axis correction device according to the present invention includes a storage device that temporarily stores input signals for time axis forward correction, and a storage device that temporarily stores input signals in synchronization with the input signals. A write address generator generates all addresses when all the signals are committed to the storage device, and data from the storage device is synchronized with a reference signal? In a time axis correction device including a read address generator that generates an address for reading, the write address generator includes a synchronization signal detector that detects a synchronization signal from a human input signal, and a synchronization signal detector that detects a synchronization signal from a human input signal. A synchronous address reader that reads a synchronous address from an input signal using a synchronous signal, and a synchronous address reader that either replaces all the counted values with the synchronous address for each input of the synchronous signal according to a control signal, or counts up the counted value. Then, with a counter that outputs as a write address and all write addresses output from the counter, next,
When a synchronization signal is input, it is converted into a value that can be taken by the counter, and the value and the synchronization address are compared for each input of the synchronization signal, and if the two do not match only once, the count value of the counter is and a controller that outputs a control signal t- to count up the counter, and when the two match or do not match twice or more, outputs a control signal to replace the counted value of the counter with the value of the total synchronization address. has been done. (Embodiment) Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a time axis correction device according to the present invention. The input signal l is input to the storage device 4 and the write address generator 5, and the reference signal 2 is input to the read address generator 6. The output of the write address generator 5 and the output of the read address generator 6 are selected by the selector 9 and input to the storage device 4. The input signal 1 input to the write address generator 5 is internally supplied to a synchronous signal detector 7 and a synchronous address reader 8. The output of the synchronization signal detector 7 is output from the synchronization address detector 8.
is supplied to the controller 11 and the counter 10, and the output of the synchronous address reader 8 is supplied to the counter 10 and the controller 11,
The output of controller 11 is supplied to counter 10. The output of the counter 10 is supplied to the controller 11 and also to the selector 9 as the output of the write address generator 5. FIG. 3 is a diagram showing a specific circuit of the controller 11. The synchronous address 21, which is the output of the synchronous address ejector 8, is input to the comparator 25, and the write address 22, which is the output of the counter 10, is incremented by one block address by an adder (for example, FROM) 24. The signal is input to the comparator 25. The output of the comparator 25 is input to a D flip-flop 26, and the output of the D clip-flop 26 is input to a D slip 70 tube 27 and an AND gate 28. D flip 7
The inverted output of the 0 tube 27 is input to an AND gate 28, and the output of the AND gate 28 is input to a NAND gate 2.9. Synchronization signal 23 which is the output of synchronization signal detector 7
is input to the D flip-flop 26, the D flip-flop 27 and the NAND gate 29, and the NAND gate 2
The output of 9 is connected to the load terminal of the counter 0 as the output of the controller 11, and controls whether or not the synchronous address 21 is loaded into the counter 10. FIG. 2 is a detailed timing chart explaining the operation of FIG. 1. The nine synchronization addresses 21 read out by the synchronization signal are added by one block to the count value of the previous block in an adder 24, and compared with the ratio value in a comparator 25. As a result of the comparison, if they are equal, the contents of the synchronous address will be loaded into the counter 10. A in Figure 2 is an example of such a case, where the synchronization address is "
2", the count is up and the t value is also "2", so
Is comparator 25 a match signal? Output. 0” as a match signal
is output, @O# is stored in the D flip-flop 26. If it matches in the previous comparison, @o# is also stored in the D flip-flop 27. As a precaution, ゞ0# appears at the output of the AND gate 28, and the output of the NAND gate 29 becomes 10#. This NA
The output of the ND gate 29 is the content of the synchronous address in the counter 1.
Load it to 0. Further, if the comparison result is the same in the previous block and different this time, the counter 10 will not load the synchronization address, but will automatically count up and output the contents of t block. B in FIG. 2 is an example. Since the synchronization address is "3" and the count is up and the ratio value is "5", the comparator 25 outputs a mismatch signal "1#". D flip-flop 26 This “1#” is stored in D.
Since "0" is stored in the clip-flop 27, the output of the AND gate 28 becomes "1". Please be careful N
The output of the A, ND gate 29 becomes @1 #, which does not cause the counter 10 to load the synchronization address, but automatically outputs the entire contents of the counted up block. Next, if the comparison results are different for the previous block and this time,
In this case, the contents of the synchronization address will be loaded into the counter 10. C in Figure 2 is an example of such a case, where the synchronization address is "3".
If the value counted up at "5" was the previous time, the synchronous address was counted up at "4" and the t value was "6".
In both cases, the output of the comparator 25 is "1". "1#" is stored in the D flip-flop 26 and the D flip-flop 27.The output of the refined AND gate 28 becomes "0", and the output of the NAND gate 29 also becomes "0".
becomes #. Therefore, the content of the synchronization address is
loaded into. (Effects of the Invention) As explained in detail above, according to the present invention, when a synchronization address loses continuity with the immediately previous content, if it is a one-time error, the synchronization address cannot be used. By using a false address without counting up, there is an effect that the propagation of errors can be completely reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the time axis correction device according to the present invention, Fig. 2 is a timing chart for explaining the operation of Fig. 1, and Fig. 3 is a circuit diagram showing a specific example of the controller. , FIG. 4 is a block diagram showing the configuration of a conventional time axis correction device, and FIGS. 5 and 6 are diagrams explaining the operation of FIG. 4.
This is a timing chart. 1... Input signal 2... Reference signal 3... Output signal 4... Storage device 5... Write address generator 6... Read address generator 7... Synchronization signal detector 8 ...Synchronous address reader 9...Selector】0・
...Counter]1...Controller 21...Synchronization address 22...Write address 23...Synchronization signal 24...Adder 25...Comparator 26...
・I) Flip-flop 27...D flip-flop 2B-AND gate 29...NAND gate 1B 4

Claims (1)

[Claims] a storage device that temporarily stores input signals in order to correct the time axis; a write address generator that synchronizes with the input signal and generates an address for writing the input signal to the storage device;
A time axis correction device including a read address generator that generates an address for reading data from the storage device in synchronization with a reference signal, wherein the write address generator includes a synchronization signal detector that detects a synchronization signal from an input signal. a synchronous address reader that reads a synchronous address from an input signal according to a synchronous signal detected by the synchronous signal detector, and a synchronous address reader that replaces the counted value with the synchronous address for each input of the synchronous signal according to a control signal. or a counter that counts up the counted value and outputs it as a write address; and compares the value with the synchronization address for each input of the synchronization signal, and if the two do not match only once, outputs a control signal for incrementing the count value of the counter. and a controller that outputs a control signal for replacing the counted value of the counter with the value of the synchronization address when the two match or do not match two or more times.