JPH0319540A - Access fault detector for elastic buffer - Google Patents

Abstract

PURPOSE:To prevent mis-detection by using an advanced clock of other address so as to latch one of a read address and a write address, comparing the address with other address and allowing a flip-flop to fetch the result of comparison with a clock not identical to the advanced clock. CONSTITUTION:A write clock and a readout clock are given, then a write counter 3 and a readout counter 5 are advanced and a write address and a readout address are outputted. The write address is fetched to a write address latch 100 in the leading of a readout clock RCLK and address changeover takes place at the leading of the readout clock RCLK. Thus, hazard appearing at the output of a NOR gate 62 synchronizes with the leading of the readout clock RCLK. On the other hand, an output signal of the NOR gate 62 is fetched in a D-FF 63 at the leading of the inverse of the readout clock RCLK. Thus, when hazard appears, no fetch is implemented to the D-FF 63 and mis-detection is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an access light detection device for an elastic buffer used in an asynchronous digital communication system.

[Conventional technology]

Conventionally, in asynchronous digital communication systems,
An elastic buffer is provided to absorb differences and fluctuations between the input signal transmission speed and the data transmission speed on the receiving side, or to adjust the phase of the human input signal.

Here, if writing and reading are performed simultaneously to the same address of the data storage memory of the elastic buffer, an error may occur in the read data. Therefore, the elastic buffer is provided with an access abnormality detection device.

An elastic buffer containing such a device is shown in FIG. In the figure, 1 indicates a memory in which data is stored. The transmitted data is written into the memory 1 by the writing section 2 using the address given from the write address generation section 3. The write address generator 3 is incremented by the old clock generated from the incoming data, and generates an address that cyclically indicates the address of the memory 1. On the other hand, the written data is in the continuous part 4
As a result, the address given from the successive address generation section 5 is read out from the memory 1.

The read address generator 5 is incremented by a read clock (asynchronous to the !f clock) generated on the receiving side, and generates an address that cyclically indicates the address of the memory 1.

The address output from the write address generation section 3 and the address output from the read address generation section 5 are set to be identical, but in order to detect this when they match, an access abnormality detection device is used. 6 is provided.

This access abnormality detection device 6 has conventionally been configured as shown in FIG. That is, the corresponding addresses of the write counter (address generation circuit) 3 and the read output counter (address generation circuit) 5 are inputted to the exclusive OR gates 61 to 61.
613 and provide these outputs to the NOR gate 62. by this,
When the read address and write address match, the output of NOR gate 62 becomes H level.

The output signal from the NOR gate 62 is applied to a D-type flip-flop (D-FF) 63, and is taken in by RCLK, which is the read clock inverted by an inverter 64, and is used as an access abnormality detection signal. When this access abnormality detection signal is active (H level), for example, the read data is discarded.

[Problem to be solved by the invention]

However, when the write clock and the read clock are in an asynchronous relationship as shown in FIG. A hazard occurs. Therefore, a hazard is superimposed on the output signal of the NOR gate 62, and when this is taken into the D-FF 63 at the rising edge of the inverted signal RCLK of the read clock, the hazard due to the switching of the write address causes the
- There was a problem in that the H level was latched in the FF 63, resulting in false detection.

Therefore, in the present invention, the write clock and the read clock are in an asynchronous relationship, and an elastic buffer that can prevent false detection even when a hazard occurs when switching between the write address and the read address in the comparator. The objective is to provide an access anomaly detection device.

[Means for resolving issues]

Elastic buffer access 5' according to the present invention (
The normal detection device uses a memory in which data is written in synchronization with the transmission clock of incoming data, but data is read out based on a clock asynchronous to the transmission clock, and the read address of the memory is and a write address using a clock that increments the other address, a comparison section that compares the address latched to this with the other address, and a latch circuit that compares the result of this comparison. The device is characterized in that it includes a flip-flop that receives data using a clock that is not the same as the latch timing clock.

[Effect]

Since the elastic buffer access abnormality detection device according to the present invention is configured as described above, one of the read address and the write address is latched using the increment clock of the other address, and the latched The address is compared to the other address. In other words, the switching timings of both addresses related to the comparison match, and a hazard occurs only at this time. Moreover, since the flip-flop captures the comparison result using a clock that is not the same as the step clock, the data is not captured when there is a hazard.
Prevent false positives.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An elastic buffer access abnormality detection apparatus according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2 of the accompanying drawings. In the description of the drawings, the same components are designated by the same reference numerals and the description thereof will be omitted.

The elastic buffer to which the access abnormality detection device 6A according to the embodiment is applied is the same as that shown in FIG. 3, and the device 6A is used instead of the access abnormality detection device 6 shown in FIG. used.

FIG. 1 shows the configuration of a first embodiment of the present invention. Here, the write clock frequency is lower than the read clock frequency (
1/2), there are three D-Fs on the output side of write counter 3.
A write address latch 100 consisting of F is connected. The write address latch 100 latches the write address output from the write counter 3 at the rising edge of the read clock RCLK. The exclusive OR gates 61 to 613 and the t-NOR gate 62 constitute a comparison section that compares the output of the write address latch 100 and the output of the read output counter 5. The output of the NOR gate 62 is taken in by the D-FF 63 in synchronization with the rise of the inverted signal RCLK of the read clock RCLK.

In the access abnormality detection device 6A configured as described above, a write clock and a read clock are applied as shown in FIG. As a result, the write counter 3 and the read output counter 5 are incremented, and the write address and read address are output as shown. Here, the write address is taken into the write address latch 100 at the rising edge of the read clock RCLK, and irrespective of the address switching timing by the write counter 3, address switching occurs at the rising edge of the read clock RCLK. As a result, the i switching timing of the input signals of the exclusive OR gates 61 to 613 is synchronized with the rising edge of the read clock RCLK, and a hazard occurs only at this time.

Therefore, the noise appearing at the output of the NOR gate 62 is synchronized with the rising edge of the successive clock RCLK as shown in FIG. On the other hand, the output signal of the NOR gate 62 is applied to the D-FF6 at the rising edge of the inverted signal RCLK of the read clock RCLK.
It will be incorporated into 3. Therefore, when a hazard appears, the data is not imported into the D-FF 63, and erroneous detection can be prevented. As in the conventional case, the access abnormality detection signal obtained by the D-FF 63 is used in the reception system to determine whether to adopt/discard data read from the memory 1.

The invention is not limited to the embodiments described above, and various modifications are possible. For example, if the write clock is faster than the read clock, a latch may be placed on the output side of the read output counter 5, and in this case, the inverted signal of the write clock is used to cause the D-FF 63 to take in the data.

[Effects of the Invention] As described above in detail, according to the present invention, the switching of the address on the side latched by the latch circuit is synchronized with the switching of the other address, and the switching of the address on the latched side is synchronized with the switching of the address on the other side. Hazards caused by switching will no longer occur. Then, the generated hazard can be removed by importing the comparison result into the flip-flop at a timing different from the timing at which the hazard appears, and 24 detection by the nose can be prevented.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an access abnormality detection device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the device shown in FIG. 1, and FIG. 3 is a configuration of an elastic memory. 4 are configuration diagrams of the conventional example, and FIG. 5 is a timing chart for explaining the operation of the conventional example. 1...Memory, 2...Writing unit, 3...Write address generation unit (write counter), 4...Reading unit, 5...Reading address generation unit (readout counter), 6A. ...Access "Jl! Normal detection device, 61 to 613...Exclusive OR gate, 62...Nor gate, 63...D-FF, 1
00...Write address latch.

Claims (1)

[Scope of Claims] An access abnormality detection device for an elastic buffer using a memory in which data is written in synchronization with a transmission clock of incoming data, while data is read out based on a clock that is asynchronous with the transmission clock. , one of the read address and write address of the memory is set to
A latch circuit that latches using a clock that increments the other address, a comparison section that compares the address latched by this latch circuit with the other address, and a comparison result of this comparison section that is applied to the latch of the latch circuit. Elastane with a timing clock and a flip-flop clocked by a non-identical clock.