JPS607542A - Error processing circuit - Google Patents

Abstract

PURPOSE:To make a study of the cause of generation of an error easy by preventing inputting of a set clock signal to a data register at a time point when the error arises, and holding the faulty data at the register. CONSTITUTION:A data buffer receives the data to be processed from the outside and stores it temporarily. A data checking part 2 checks the data stored in the buffer 1 through a parity checking circuit. The error detection signal of the part 2 is transmitted to an error state holding part 4. A gate G2 prevents the transmission of the input signal to an output terminal when the error detection signal is delivered from the part 2. Therefore the clock signal transmitted from an oscillator 3 is prevented by the gate. Thus the input of the clock signal is prevented to the buffer 1 immediately after a data error is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to error processing, and in particular to an error processing circuit that checks input data and stops sending out a clock signal from an oscillator when an error is discovered. Pertains to.

(tel Background of technology) Reliability of processing results is as important as data processing speed in electronic devices.In other words, even if the processing speed is high, the reliability of the results is low for devices that have low processing speed. Even if it is a little slow, it is inferior to equipment with high reliability of results.For this reason, various techniques have been developed and put into practical use to check whether the data to be processed is correct.As a typical data check method, Parity check method.

Examples include the CRC method.

(C) Problems with the conventional technology Now, from the viewpoint of the reliability of processing results, if an error is found in the data to be processed, Juf& processing must be stopped. It is common practice to stop the clock signal that controls the timing of the circuit when an error is discovered in the data.

However, the clock signal is stopped by stopping the sending of the clock signal from the oscillator 1fn.

Therefore, the clock signal is input to the data buffer between the time the error check circuit detects the error and the time when the oscillator stops sending the clock signal, and as a result, the next data is set in the data buffer and the error occurs. The data will be deleted. Therefore, it has the disadvantage that it is impossible to investigate the cause of the error.

(dl) Purpose of the Invention In view of the above, an object of the present invention is to provide an error processing circuit that does not erase data in which an error has occurred even if a data error occurs.

(e) Embodiments of the Invention Below, embodiments of the error processing circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing an error processing circuit, in which 1 is a data buffer, 2 is a data check section, 3 is an oscillator, 4 is an error state section, Gl is a first gate, and Gl is a first gate.
2 is the second gate.

The data buffer l has a function of receiving data to be processed from the outside and temporarily storing it, and is composed of registers. The data check section 2 checks the data stored in the data buffer 1, and is composed of, for example, a parity check circuit. The error detection signal of the data check section 2 is sent to the second and error state holding section 4. The gate 2 has a function of blocking the input signal from being sent to the output terminal when the error detection signal is output from the data check section 2. Therefore, the clock signal being sent from the oscillator 3 is blocked in cases 1 through 1, and the input of the clock signal to the data buffer 1 is blocked immediately after a data error occurs. Therefore, the secondary data is not secessed into the buffer, and the data containing the error remains in the buffer. On the other hand, data 1-Gl is gated later than data 1-G2 by the output of the error state holding section 4, so that the transmission of the clock signal from the oscillator 3 is stopped.

FIG. 2 is an error processing circuit showing details of FIG. 1,
REGI is a 9-bit/7-bit register, PC is a parity check circuit, FFI and FF2 are flip-flop circuits,
Δ1 to A3 are AND circuits, OR1 is OR circuit, OSC
is an oscillator.

The register REGI stores data to be processed from the outside in synchronization with the arrival of the set clock signal CLKS input to the terminal C. The output of register REGI is connected to parity check circuit PC. The parity check circuit PC has a function of checking the data stored in the register REGI using a parity check method. An error detection signal ERDI which becomes logic 1 when an error occurs in the data is connected from the output terminal of the parity check circuit PC to the set terminal J of the FFI via the AND circuit female. A check timing signal CHT is input to the other input terminal of the AND circuit 2. The error signal ER from the Q terminal of PFI is connected to the OR circuit OR, and the cross-inhibit signal CLKI from the Q terminal is connected to 1 to the AND circuit. The output from another parity check circuit is connected to the OR circuit OR. The output of the OR circuit OR is input to the set terminal J of FF2. F
An inhibit signal ST that prevents the reference clock signal CLK from being sent is sent from the Q terminal of F2, and it is connected to one input of the AND circuit, and the clock signal from the oscillator OSC is input to the other input. There is. The output of the AND circuit A3 is input to the AND circuit as a reference clock signal CLK. Clock gate 1/signals C1 and KG are also manually input to AND circuit 1. Note that the signal R3T is a reset signal.

Input to reset terminal R of register/FFI/FF2. Further, CLKI is a clock signal for FFI and FF2. An alarm signal RM is sent from the Q terminal of FF2.

Next, the operation of this circuit will be briefly explained along the time chart of FIG. Note that the signal names in FIG. 3 match the signal names in FIG. 2.

The non-stop clock signal NCLK is sent from the oscillator O3C as shown in (al), and since the inhibit signal ST is logic 1, the reference clock signal CLK, which is in phase with the signal NCLK, is input to the AND A1. Cloth inhibit signal CLKI and clock gate signal CLK
Since G is a logic circuit, it is in phase with the reference clock signal CLK.
/Tokurosoku signals C and LKS are input to terminal C of data register RIEGI via 1 to an AND circuit. Therefore, 9-bit data is sent to the register by certain set clock signals C1 and KS. This data is checked by the check circuit PC, and if an error is detected, the circuit pc sets the error detection signal ERDI to logic 1. As a result, I"Fl is set and the error state is maintained. Since the terminal Q becomes logic 0 due to the cent of FFI, the cross interrupt inhibit signal CLKI gates the AND circuit AI, and sets the set clock signals C1 and KS to the register REG1. input is blocked. Therefore, the data in which an error has been detected remains held in the register. On the other hand, the error signal ER which is the Q terminal output
Since becomes a logic 1, I'F2 is also set, and as a result, the inhibit 1- signal ST becomes a logic 0, so the non-stop clock signal NCLK is blocked by 3 to the AND circuit, and the sending of the reference clock signal CLK is stopped. .

fg+ Effects of the Invention As described above, according to the present invention, when an error occurs in the data, the clock signal C to the data register is
The input of L K S is blocked, and the resulting erroneous data is held in that register. Therefore, it is convenient to investigate the cause of the error.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of the error processing circuit, FIG. 2 is a block diagram showing the details of the error processing circuit shown in FIG. 1, and FIG. 3 is a time chart of the main signals in FIG. In the figure, l is a data buffer, 2 is a data check unit,
3 is the oscillator, 4 is the error state section, and Gl is the first data 1.
−． G2 is the second gate, G1 is the register, PC is the parity check circuit, Flil, FF2
is a flip-flop circuit, and Al-A3 is an AND circuit. ORI is an OR circuit, and O and SC are oscillators. -1-! ＝〉′

Claims (1)

[Scope of Claims] A storage means for storing manually-generated data, and a data check for checking the data stored in the storage means. an oscillation unit that sends a clock signal for controlling data storage timing to the storage unit; an error status holding unit that stores and holds a state when a data error occurs by the data checking unit; The device is characterized by comprising a first gate means that prevents the clock signal from being outputted from the oscillation section by an output, and a second gate means that prevents the input of the clock signal to the storage means when the data error occurs. Error handling circuit.