JPH04268647A - Register with double read preventing function - Google Patents

Abstract

PURPOSE:To prevent double read by providing a read register into which information of a holding register where event occurrence/non-occurrence information is held is read and successively resetting both registers by the end of information read. CONSTITUTION:Event occurrence/non-occurrence information is held in a holding register 10. This information is read out from the holding register 10 to a read register 11 by a read command signal. A holding register reset circuit 13 resets the holding register 10 after detecting that event occurrence information is written from the holding register 10 to the read register 11. A read register reset circuit 12 resets the read register 11 after detecting the end of read of event occurrence/non-occurrence information from the read register 11 due to the read command signal. Registers 10 and 11 consist of D type flip flops. Each of reset circuits 12 and 13 consists of two D type flip flops and one HAND circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register with a double read prevention function. In various types of equipment such as data processing equipment and communication equipment, it is desired to improve the reliability of the equipment by always monitoring the latest occurrence of events such as alarms, and by being able to take immediate action in the event of an abnormality. I have a request. In order to do this, a register is required to hold the occurrence status of these events, but in such a register, the event presence information held for one event occurrence may be read out twice, causing the occurrence of two events to be mistaken. It is necessary to be able to prevent this from happening.

0002

2. Description of the Related Art FIG. 4 shows a conventional register of this type for holding alarm information. In the figure, ALMin
is an alarm signal that remains "H" during the period in which the alarm is occurring, and a period in which "H" continues continuously means the occurrence of one alarm event. ALMout is an alarm output signal indicating "alarm present" by "H", and is output as read alarm information in response to a read command. *REN is a negative logic read enable signal serving as a read command signal, and instructs a read operation at "L". This read enable signal *RE
N is generated periodically or at an appropriate timing, and is asynchronous with the alarm input ALMin. *RES is a negative logic reset signal generated at the rising edge of read enable signal *REN.

51 is a flip-flop for holding alarm information to be read; 52 is a rising edge of the read enable signal *REN (that is, the end of the read command);
The rising edge detectors 53 to 55 are logic gates. The circuit composed of logic gates 53 to 55 is “H”
When the alarm input ALMin is input, the flip-flop 51 is set to "H" indicating "alarm present", and after that, the alarm input ALMin is input until the reset is applied.
It functions to maintain the output state of the flip-flop 51 as it is even if it disappears.

In this conventional circuit, while an alarm is occurring, the alarm is held preferentially, the alarm information is read from the flip-flop 51 in response to a read command by the read enable signal *REN, and furthermore, when the read enable signal *REN rises, the alarm information is read out from the flip-flop 51. The alarm information held in the flip-flop 51 is reset by the reset signal *RES generated by detecting the end of the read command (that is, the end of the read command).

[0005]

[Problems to be Solved by the Invention] In the above-mentioned conventional circuit,
When the alarm input ALMin of "H" continues for a long time, the alarm information is read twice. This situation is shown in FIG. That is, when an alarm occurs, an alarm input ALMin of "H" is input, and this alarm input ALMin becomes a read enable signal *RE.
In the case where it is continued until after the end of N■ and then released, the flip-flop 51 is not reset by the reset signal *RES■ in the circuit of FIG. Therefore, not only the alarm output ALMout of "H" is read out by the read enable signal *REN■, but also the same alarm output ALMout is read out by the read enable signal *REN■ at the next timing, and the same alarm output ALMout is read out by the read enable signal *REN■ at the next timing. twice for the alarm input ALMin.
"There is an alarm" is read out. If such alarm information is read twice, it will result in a malfunction when counting the number of alarm occurrences.

The present invention has been made in view of the above problems, and its purpose is to prevent malfunctions due to double reading of registers that hold events such as occurrence of alarms.

[0007]

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. In order to achieve the above-mentioned object, the register with a double read prevention function according to the present invention has a holding register 1 that holds information on the occurrence or non-occurrence of an event.
0 to which event presence information is written when an event occurs, and a read register 11 from which event presence/absence information is read in response to a read command signal, which is held from the holding register 10 when the read command signal is received. A holding register reset circuit 13 detects that event presence information is written from the holding register 10 to the read register 11 and resets the holding register 10, and a holding register reset circuit 13 detects that event presence information is written from the holding register 10 to the read register 11. The device includes a read register reset circuit 12 that detects the completion of reading of the event presence/absence information and resets the read register 11.

Another form of the register with a double read prevention function according to the present invention is a holding register 10 consisting of a D-type flip-flop, in which a constant logic level signal is input to a data input terminal, and a clock input terminal A readout register 11 is configured such that status information is inputted to the input terminal and a holding register reset signal is inputted to the reset input terminal, and a readout register 11 is composed of a D-type flip-flop, and the data is outputted from the holding register 10 to the data input terminal. The device is configured such that event presence information is input to the clock input terminal, a read command signal is input to the clock input terminal, and a read register reset signal is input to the reset input terminal, and information indicating that an event exists from the holding register to the read register. The holding register reset circuit 13 detects that a read command signal has been written and generates a holding register reset signal, and the read register reset circuit 12 detects the end of a read command signal and generates a read register reset signal. .

[0009]

[Operation] When a certain event occurs, event occurrence information is written to the holding register 10. The event presence information in the holding register 10 is written from the holding register 10 to the reading register 11 in response to the generation of a read command signal. When the writing to the read register 11 is completed, it is detected by the holding register reset circuit 13, and the holding register 10 is reset by a holding register reset signal generated by the holding register reset circuit 13.

Read register 1 based on read command signal
When the reading of the event presence/absence information from 1 is completed, it is detected by the read register reset circuit 12, and the read register 11 is reset by the read register reset signal generated by the read register reset circuit 12.

Because of the above operation, even when event presence information is continuously generated before and after the read command signal, the holding register 10 is triggered by the read command signal.
Both the read register 11 and the read register 11 are reset, so that the read command signal input at the next timing will not cause the same event information to be read twice on the output side.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a register with a double-read prevention function as an embodiment of the present invention. In the figure, alarm input AL
Min, alarm output ALMout 1, alarm output ALMout 2, and read enable signal *REN are signals with the same logic as explained in the above-mentioned conventional example.

Reference numeral 1 denotes an alarm holding register composed of a D-type flip-flop, which operates to hold "H""alarmpresent" information at the rising edge of the alarm input ALMin. The data input terminal D of this alarm holding register 1 is fixed at "H" level, and the alarm input ALMin is input to the clock input terminal CK.

2 is an alarm read register composed of a D-type flip-flop, and a read enable signal *
Alarm output ALMo output by alarm holding register 1 at the falling edge of REN (that is, the start of alarm reading)
It operates to read and hold ut1. The alarm output ALMout 1 from the alarm holding register 1 is input to the data input terminal D of the alarm read register 2, and the read enable signal *REN is input to the clock input terminal CK.

Reference numeral 3 denotes a read enable rising edge detection section which detects the rising edge of the read enable signal *REN (that is, the end of the alarm read command), generates a pulse of one clock length of the clock CLK, and generates a reset signal *RES1.
as reset input terminal R of alarm read register 2
It operates to send to. This read enable rise detection section 3 includes D-type flip-flops 31, 32, NAND (
NAND) circuit 33.

4 is an alarm output rise detection section, which detects the alarm output ALM output from the alarm reading register 2.
It operates to detect the rising edge of out 2, generate a pulse of one clock length of clock CLK, and send it to reset input terminal R of alarm holding register 1 as reset signal *RES2. This alarm output rise detection section 4 is D
It consists of flip-flops 41 and 42 and a NAND circuit 43.

The operation of this embodiment circuit will be explained below with reference to FIG. FIG. 3 is a time chart of signals of each part of the embodiment circuit.

First, the operation of the alarm input ALMin that occurred and disappeared during period A will be explained. This is the case indicated by the dashed dotted line in FIG. This alarm input AL
At the rising edge of Min, "H" is held in the alarm holding register 1, and the alarm output ALMout1 becomes "H". This alarm output ALMout 1 is read into the alarm read register 2 at the falling edge of the read enable signal *REN■, and the alarm read register 2 outputs an "H" alarm output ALMout 2. The rise of this alarm output ALMout 2 is detected by the alarm output rise detection section 4, and a reset signal *RES2■ is generated, and the alarm holding register 1 is reset by this reset signal *RES2■, and its output signal becomes "L".
becomes. In other words, the contents of the alarm holding register 1 are transferred to the alarm reading register 2 in response to the read enable signal *REN■.

The alarm output ALMout 2 is read from the alarm read register 2 during the "L" period of the read enable signal *REN■ and becomes alarm occurrence information. Alarm read register 2 uses read enable signal *R
It is reset to "L" by the reset signal *RES1■ generated by the read enable rise detection section 3 at the rising edge of EN■ (that is, the end of alarm reading).

In this way, the alarm input ALMin that occurred and disappeared during the period A becomes the read enable signal *
It can be read by REN■. Similarly, period B
The alarm input ALMin that occurs and disappears during this period can be read by the read enable signal *REN■.

Next, a case will be described in which the alarm input ALMin occurs before the read enable signal *REN■ is generated and continues until after the read enable signal *REN■ ends. This is the case of timing ■ in the figure, and the waveform is indicated by a solid line. This is a situation in which double reading occurs in conventional circuits. The operation in this case is also the same as in the case of section A described above. Therefore, the alarm input ALMi
Even if n continues before and after the read enable signal *REN■, the alarm output ALMout 1■ from the alarm holding register 1 is the read enable signal *R
It is reset at the falling edge of EN■, and the alarm output ALMout 2■ from the alarm read register 2 is reset at the rising edge of the read enable signal *REN■, so the read enable signal input at the next timing ■ *REN■ does not cause double reading.

Next, a case where the rising edge of the alarm input ALMin and the rising edge of the read enable signal *REN overlap will be explained. This is the case of timing ■ or ■ in the figure. First, in the case of timing ■, the alarm output ALMout 1■ from the alarm holding register 1 becomes "H". However, at the falling timing of the read enable signal *REN■, the alarm output ALMout 1 is “L”.
”, the alarm read register 2 is set to “L”.
is read and alarm output ALMout 2 is “L”
It remains as it is. Therefore, the presence of an alarm cannot be detected by the read enable signal *REN■. However, when the read enable signal *REN is input at the next timing, the alarm holding register 1
"H" of the alarm input ALMin1 is transferred to the alarm read register 2, and the occurrence of an alarm can be detected.

On the other hand, as shown in the figure, if the rising edge of the alarm input ALMin and the rising edge of the read enable signal *REN overlap at the next timing ■, the alarm output AL
“H” of Mout1 is transferred to the alarm reading register 2, and its alarm output ALMout 2 becomes “H”, and at the rising timing of this alarm output ALMout 2, the alarm output ALMout of the alarm holding register 1 is transferred to the alarm reading register 2.
ut1 is reset. Furthermore, if the timing at which the alarm output ALMout 1 of the alarm holding register 1 is reset coincides with the rising edge of the alarm input ALMin, the reset takes priority and the alarm output ALMout
1 is reset. At the end of the read operation, that is, at the rising edge of the read enable signal *REN■, the alarm output ALMout 2 of the alarm read register 2 is output.
is reset. In this way, the example circuit uses register 1 for holding alarms and register 2 for reading,
When an alarm is input, the alarm holding register 1 holds the alarm, and when reading the alarm information, the alarm information is transferred from the alarm holding register 1 to the alarm reading register 2 to perform a reading operation, and then the alarm holding register 1 is reset.

[0024]

As described above, according to the present invention, it is possible to prevent the same event (for example, an alarm) from being read twice, which greatly contributes to improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a register with a double-read prevention function as an embodiment of the present invention.

FIG. 3 is a time chart of signals of various parts for explaining the operation of the embodiment.

FIG. 4 is a block diagram showing a conventional example circuit.

FIG. 5 is a time chart of various signals for explaining the operation of a conventional circuit.

[Explanation of symbols]

1 Alarm holding register 2 Alarm read register 3 Read enable rise detection section 4 Alarm output rise detection section 31, 32, 41, 42 D-type flip-flop 33
, 43 AND circuit ALMin Alarm input ALMout 1 Alarm output from the alarm holding register ALMout 2 Alarm output from the alarm reading register *REN Read enable signal *RES1 Reset signal for resetting the alarm reading register *RES2 Reset signal for resetting the alarm holding register CLK clock

Claims (2)

[Claims] 1. A holding register (10) that holds information on the occurrence of an event, into which the event presence information is written when an event occurs, and a read register (11) from which the event presence information is read in response to a read command signal. When the read command signal is received, the held event presence/absence information is written from the holding register to the read register, and when it is detected that the event presence information is written from the holding register to the read register, the holding is performed. A holding register reset circuit (13) for resetting a register, and a read register reset circuit (12) for detecting completion of reading of event presence/absence information from the read register by a read command signal and resetting the read register. Register with degree reading prevention function. 2. A holding register (10) consisting of a D-type flip-flop, in which a constant logic level signal is input to a data input terminal, status information is input to a clock input terminal, and holding register reset is input to a reset input terminal. A read register (11) configured to receive a signal and a D-type flip-flop, the event presence information output from the holding register is input to the data input terminal, and read to the clock input terminal. The holding register is reset by detecting that a command signal is input, a read register reset signal is input to the reset input terminal, and information indicating an event has been written from the holding register to the read register. A register with a double read prevention function, comprising a holding register reset circuit (13) that generates a signal, and a read register reset circuit (12) that detects the end of the read command signal and generates the read register reset signal.