JPH02214348A - Access fault detector - Google Patents

Abstract

PURPOSE:To avoid malfunction due to hazard caused at an address change point by applying logic operation to output signals of a 1st latch circuit latched based on an advance clock of a write address data and a 2nd latch circuit latched based on an advance clock of a readout address data. CONSTITUTION:EX-OR 111-113 compare write address data WAi and readout address data RAi with corresponding bits and send a signal of the result of comparison to a NOR gate 12. The NOR gate 12 when 3 inputs are all at an L level gives an H level signal and in other cases gives an L level signal to a data terminal D of 1st and 2nd latch circuits D-FF 131 and 132. The D-FF 131 latches an output signal of the NOR gate 12 by an inverted write clock signal WCLK and the D-FF 132 latches the output signal of the NOR gate 12 by an inverted readout clock signal RCLK. The output signals of the D-FF 131 and 132 are led to an AD gate 14, where they are ANDed. Since the latch clock of the D-FF 131 and 132 is asynchronous, no hazard exists in the same timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is an access abnormality that is suitable for use in detecting the occurrence of an access abnormality in an elastic buffer used in an asynchronous digital communication system. This invention relates to a detection device.

[Conventional technology]

Conventionally, in asynchronous digital communication systems,
An elastic φ buffer is provided to absorb differences and fluctuations between the input signal transmission speed and the data transmission speed on the receiving side, or to perform phase matching with respect to the input signal.

This elastic buffer has a plurality of memory cells in which data is stored, and each memory cell is assigned an address and used for reading and writing data. When reading or writing data, specifying the same address may result in incorrect data being read, so an access abnormality detection device detects when the write address and read address match and determines that the access is abnormal. is necessary.

FIG. 3 shows a conventional access abnormality detection device.

In this example, it is assumed that the address is represented by 3 bits, but in reality, the number of bits corresponds to the address of the elastic φ buffer, A. Write address data (
Corresponding bits of WAi) and read address data (RAi) are led to EX-OR (exclusive or gates) 311 to 313, respectively, for comparison. Then, the comparison result is sent to the NOR gate 32 and used as an inverted signal of the logical sum of the D-type flip-flop (hereinafter referred to as D-F).
It's called F. ) 33 and latched with a clock RCLK that increments the read address data. The output signal of this D-FF 33 is given to the data processing device as an access abnormality (address match) detection signal ClCD, and is used for processing such as invalidating the data read at this time.

[Problems to be Solved by the Invention] However, in the conventional access abnormality detection device as described above, EX-
Hazards (so-called "whiskers") in OR31-313
) is generated by the NOR gate 32 as shown in FIG. 4, and this is captured by the latch operation in the D-FF 33, resulting in a problem of false detection.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an access abnormality detection device that can accurately detect access abnormalities when the same address is accessed in a buffer, and that does not malfunction due to hazards that occur at address change points. shall be.

[Means to solve the problem]

The access abnormality detection device according to the present invention includes at least a predetermined bit of write address data used for writing data to a buffer that temporarily stores incoming data and outputs it in a FIFO format, and a read address used for reading data from the buffer. Comparing means for comparing both predetermined bits with at least a predetermined bit of data and outputting a match signal; and a first latch circuit for latching the match signal of the comparing means based on a step clock of write address data. , a second latch circuit that latches the match signal of the comparison means based on the step clock of the read address data. 1st, 2nd
The present invention is characterized by comprising a logic operation means for performing a logic operation on the output signals of the latch circuits to cancel hazards generated in the respective output signals.

[Effect]

Since the access abnormality detection device according to the present invention is configured as described above, the first latch circuit does not capture the hazard that occurs at the change point of the write address data, and the second
The latch circuit does not take in the hazard that occurs at the change point of the read address data, and signals with hazards are obtained at different timings. Therefore, the hazard can be eliminated by guiding these signals to a logic calculation means and, in the simplest way, creating a logical product. Note that the point of detecting address matching is not lost in this calculation.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 2 shows an elastic buffer section in which the access abnormality detection device of FIG. 1 is used. INPU
The data arriving at the T terminal is sent to the buffer 2 by the writing section 21.
2 memory cells. In this embodiment, buffer 22 has eight memory cells and is given addresses from 1 to 8. The write address generator 24 is composed of an octal counter that is incremented by a write clock WCLK synchronized with incoming data, and outputs three-digit address data. The output address data is given to the write section 21, and the write section 21 writes data into the memory cell of the buffer 22 having an address corresponding to the address data. The read address generator 26 is composed of an octal counter that is incremented by a read clock RCLK asynchronous to the write clock WCLK, and outputs three-digit address data. This address data is given to the readout section 23, and the readout section 23 reads out the data of the memory cell in the buffer 22 having the address corresponding to the address data. The read data is 0U
The data is sent from the TPUT terminal to a data processing device, etc. Here, the write address data and the read address data are initially set so that they are not the same. Note that the write clock WCLK and the read clock RCLK are output from the illustrated clock generation section.

The access abnormality detection device collects write address data sent from the write address generation section 24 and read address generation section 2.
Read address data sent from 6, write clock W
CLK inverted signal WCLK.

It receives the inverted signal RCLK of the read clock RCLK and outputs the detection signal ClCD.
As shown in the figure.

In FIG. 1, EX-ORs 11 to 113 constitute (1) comparison means, which compares write address data WAi and read address data RAi of corresponding bits, and sends a comparison result signal to NOR gate 12. noah gate 1
2 outputs an H level signal when all three inputs are at L level, and an L level signal at other times, to the first latch circuit (D-FF131) and the second latch circuit (D-FF131).
F132) data terminal. The D-FF 131 inverts the output signal of the NOR gate 12 and converts it into a write clock signal WC.
The D-FF 132 latches the output signal of the NOR gate 12 using the inverted read clock signal RCLK.

The output signals of D-FF1B and D-FF13□ are led to AND gate 14, which is a logic operation means, and a logical product is created.

The output signal of the AND gate 14 is applied to the data terminal of the D-FF 15, and the inverted read clock signal RCL
It is latched at K and sent to the data processing device as an access abnormality (address match) detection signal ClCD.

As a result of the access abnormality detection device 25 being configured as described above, the fourth
Even if a hazard occurs at the address change point as shown in the figure, the inverted write clock signal W
Since latching is performed at CLK, no hazard is introduced at the point where the read address data changes. Also, D
In the -FF 132, latching is performed using the inverted read clock signal RCLK, so there is no hazard at the point where the write address data changes. Also, D-FF13.
In D-FF132, the hazard at the point where the write address data changes may be taken in, and in the D-FF132, the hazard at the point at which the read address data changes, but the hazards in each output signal appear at the same timing. Therefore, when the AND gate 14 generates a logical product, the hazard is canceled and the attribute as a detection signal when the addresses match remains. The output signal of this AND gate 14 is converted to D-FF1
Since the detection signal ClCD is latched at 5, a detection signal ClCD that does not cause false detection due to a hazard can be obtained. This detection signal ClCD is used in the same manner as before.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, the logical operation means may have a similar configuration using several gates instead of an AND gate. Further, instead of using all bits of the address data, for example, some high-order bits may be used to detect that the interval between the read address and the write address is abnormally close. In this way, if the frequency of either the read clock or the write clock becomes abnormal, it is possible to detect the abnormality and take measures such as stopping the operation before erroneous data is read. can.

〔Effect of the invention〕

As described in detail above, according to the present invention, since the latch clocks of the first latch circuit and the second latch circuit are asynchronous, the hazards present in the output of each latch circuit occur at the same timing. It turns out that it doesn't exist. Therefore, by performing a logical operation on this, it is possible to accurately detect an access abnormality without being affected by the hazard that occurs at the address change point.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an access anomaly detection device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of an elastic contention buffer section in which the access anomaly detection device is used, and FIG. 3 is a conventional access anomaly detection device. FIG. 4 is a timing chart for explaining the operation of the conventional access abnormality detection device. 11-113...EX-OR, 12...Noah Gate, 13. 13. 15...D-FF, 14...AND gate, 21...Writing section, 22...Buffer,
23...Reading section, 24...Write address generation section, 2
5... Access abnormality detection device, 26... Read address generation unit. Patent Applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney: Yoshiki Hase Figure 2: Elastic pot buffer to which the embodiment is applied

Claims (1)

[Scope of Claims] At least a predetermined bit of write address data used to write data to a buffer that temporarily stores incoming data and outputs it in a FIFO format, and at least a predetermined bit of read address data used to read data from the buffer. a comparison means that compares the match signal with a predetermined bit and outputs a match signal; a first latch circuit that latches the match signal of the compare means based on a step clock of the write address data; a second latch circuit that latches the read address data based on a step clock, and performs a logical operation on the output signals of the first and second latch circuits to cancel hazards occurring in the respective output signals. 1. An access anomaly detection device comprising: logical operation means.