KR100338402B1 - Memory device and method of controlling the same - Google Patents

Abstract

The memory includes a differential circuit for outputting a signal corresponding to the difference value between the input read address signal and the input write address signal, a decision circuit for outputting a determination signal in response to the output of the differential circuit, and an input read address signal, input write Based on the address signal and the determination circuit, an address generation circuit for outputting a generation write address and a generation read address having a given or greater difference signal value is made.

Description

MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

The present invention relates to a method for controlling a multi-port memory for use in data delay circuits such as video systems.

The multi-port memory (hereinafter referred to as "two-port memory"), which represents one embodiment of the conventional multi-port memory, has a read decoder and a write decoder, and can execute read processing and write processing for the same period.

It is an object of the present invention to avoid the problem that data to be read is damaged due to matching of the read address and the write address or read simultaneously with writing when the periods of the read address and the write address supplied to the memory are different from each other.

1 is a schematic block diagram of a two port memory illustrating an embodiment of the invention.

2 is a block diagram of a write address generation circuit.

3 is a block diagram of a read address generation circuit.

4 is a circuit diagram of an address match detection circuit 8;

5 is a circuit diagram of an address match detection circuit 15. FIG.

Fig. 6 is a timing chart showing the operation of a two port memory showing an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

1: differential circuit

2: judgment circuit

3: address generation circuit

4: read address decoder

5: write address decoder

6: input / output circuit

7: memory

According to one aspect of the present invention, in order to achieve the above object,

A differential circuit for outputting a signal having a value corresponding to the difference value between the input read address signal and the input write address signal,

A determination circuit for outputting a determination signal having a first level when the signal value output from the difference circuit is within a predetermined value, and outputting a determination signal having a second level when the value exceeds the predetermined value;

Receives an input write address signal, an input read address signal and a determination signal, and generates a write and read address having a difference in signal value exceeding at least a predetermined value regardless of the difference value between the input write address signal and the input read address signal; Address generation circuit for outputting,

A write address decoder for decoding the generated write address,

A read address decoder for decoding the generated read address, and

A storage device is provided having a memory for storing input data at an address corresponding to an output generated from a write address decoder and outputting output data from an address corresponding to an output generated from a read address decoder.

Hereinafter, one typical of various inventions to which the invention is applied will be briefly described. However, various inventions and specific configurations of these inventions will be understood from the following description.

The specification includes claims that specify the subject matter of the invention, and the objects and features of the invention, further objects, features, and advantages of the invention will become apparent from the following description with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

Figure 1 is a schematic block diagram of a two port memory illustrating one embodiment of the present invention.

The two-port memory includes a differential circuit (1), a determination circuit (2), an address generating circuit (3), a read address decoder (4), a write address decoder (5), an input / output circuit (6) and a memory or storage section ( 7) consists of.

The difference circuit 1 is provided as a circuit for outputting a difference signal representing the absolute value of the difference between the input read address and the input write address. The determination circuit 2 is provided as a circuit for outputting a determination signal indicating whether or not the value of the difference signal exceeds a predetermined value (2 in the present embodiment). In detail, the determination circuit 2 outputs a low level determination signal when the difference signal value is larger than two, and outputs a high level determination signal when the difference signal value is two or less. The address generation circuit 3 consists of a read address generation circuit and a write address generation circuit. The address generation circuit 3 is provided as a circuit for outputting a generation read address and a generation write address based on an input read address, an input write address, a determination signal and a difference signal. The input / output circuit 6 is provided as a circuit which inputs data from the outside and outputs this data to the memory 7, inputs the data output from the memory 7 and outputs this data to the outside. The read address decoder 4 is provided as a circuit for decoding the generated read address. The write address decoder 5 is a circuit for decoding the generated write address. The memory 7 writes data output from the input / output circuit 6 to an address designated by the write address decoder 5 and serves as a circuit for outputting data stored at the address designated by the read address decoder 4. do.

2 is a circuit diagram of a write address generation circuit.

The write address generation circuit consists of the address agreement detection circuit 8, the NOR circuit 9, the counter 10, the D type flip-flops 12 and 13, the latch circuit 14, and the selector 11. The address agreement detection circuit 8 is provided as a circuit for outputting a signal A indicating whether the difference signal value coincides with a predetermined value "2". In detail, the address agreement detection circuit 8 outputs the low level signal A when the output of the determination circuit 2 coincides with the setting value "2", and the output of the determination circuit 2 is the set value. If it does not coincide with "2", the high level signal A is output. The D-type flip-flop 12 is a circuit which receives a determination signal and a write clock, and outputs the signal B which delayed this determination signal by one clock of the write clock. The NOR circuit 9 is provided as a circuit which performs the NOR of the signals A and B and outputs the signal C. FIG. When the high level signal C is input to the counter 10, the counter 10 outputs the predetermined jump address "16" as the counter value "16" on the rising edge of the next write clock. The counter 10 then increments the previously output counter value in response to the leading edge of the write clock and outputs the incremented result. The D type flip flop 13 is provided as a circuit which receives an input write address and a write clock and outputs a signal which delayed the input write address by one clock of the write clock. The selector 11 receives the output of the counter 10 and the output of the D type flip flops 12 to 13, and responds to the signal B corresponding to the output of the D type flip flop 12. And one of the outputs of the D-type flip flop 13 as a generation write address. In detail, the selector 11 outputs the output of the D-type flip-flop 13 when the low level signal B is input to the selector 11, and the high level signal B outputs the selector 11. In the case of input to the output, the output of the counter 10 is output. The generation write address terminal 19 is electrically connected to the selector 11 to receive the generation write address. The latch circuit 14 receives the generation write address and the signal C. When the high level signal C is input to the latch circuit 14, the latch circuit 14 latches the input generation write address thereto, and then outputs the latched generation write address as the signal J.

4 is a circuit diagram showing the address match detection circuit 8. As shown in FIG.

The address agreement detection circuit 8 consists of eight EXOR circuits 81, two NOR circuits 82, and one NAND circuit 83. One input (A7, A6, A5, A4, A3, A2, A1 and A0) of the eight EXOR circuits 81 is supplied with a set value <2> as a binary representation signal in the form of (00000010). . On the other hand, to the other inputs B7, B6, B5, B4, B3, B2, B1, and B0 of the eight EXOR circuits 81, the differential signal is supplied as a binaryly indicated signal.

3 is a circuit diagram showing a read address generation circuit. The read address generation circuit consists of an address match detection circuit 15, a counter 16, a selector 17 and a T type flip flop 18.

The signal J and an input read address are input to the address match detection circuit 15. The address coincidence detection circuit 15 outputs a low level signal a when the signal J and the input read address value do not coincide with each other, and when the value of the signal J and the input read address coincide with each other. It is supplied as a circuit for outputting the high level signal a.

When the high level signal a is input to the counter 16, the counter 16 outputs a predetermined jump address (here 16) as the counter value 16 on the rising edge of the next read clock. The counter 16 then increments the previously output counter value in response to the leading edge of the read clock and outputs this incremented result. The T type flip-flop 18 serves as a circuit that receives the signal a and outputs the signal b. In detail, the T-type flip flop 18 inverts the level of the previously output signal b and outputs a signal whose level is inverted in response to the falling edge of the signal from the high level to the low level. The selector 17 receives the output of the counter 16, the signal b and the input read address. The selector 17 is provided as a circuit which outputs either the input read address or the output of the counter 16 as a generated read address in response to the signal (b) level. In detail, the selector 17 outputs an input read address when the low level signal b is input, and outputs an output of the counter 16 when the high level signal b is input. The generation read address terminal 20 is electrically connected to the selector 17 and supplied with the generation read address.

5 is a circuit diagram showing the address match detection circuit 15. As shown in FIG.

The address agreement detection circuit 15 is composed of eight EXNOR circuits 151, two NAND circuits 152, and one NOR circuit 153. One input (A7, A6, A5, A4, A3, A2, A1 and A0) of the eight EXNOR circuits 151 is supplied with "J" as a binary notation signal. On the other hand, to the other inputs B7, B6, B5, B4, B3, B2, B1 and B0 of the eight EXNOR circuits 151, input read addresses are supplied as signals in binary notation.

Hereinafter, the operation of the embodiment according to the present invention will be described with reference to FIG. 6.

6 is a timing chart illustrating the operation of a two port memory, showing an embodiment in accordance with the present invention.

According to the timing chart, the data (10, 12, 13, ...) input to the two-port memory in the period T is delayed and output in the period 2T corresponding to twice the period T. Further, according to the timing chart, the write address is repeated for each period 8T by a write address counter not shown.

First, the operation of the two-port memory during the first period will be described.

This period corresponds to a period during which the absolute value of the difference between the input read address and the input write address is greater than two. The difference circuit 1 outputs a difference signal indicating a value larger than two. Since the difference signal value is larger than two, the determination circuit 2 outputs a low level determination signal. Since the D-type flip flop 12 of the write address generation circuit outputs the low level signal B during this period, the selector 11 outputs the output of the D-type flip-flop 13. That is, the address generation circuit 3 outputs a signal obtained by delaying the input write address by one clock of the write clock as the generation write address. Further, since the T-type flip flop 18 of the read address generation circuit is reset to output the low level signal b, the selector 17 outputs an input read address. That is, the address generation circuit 3 outputs the input read address as the generation read address.

Next, the operation of the two-port memory during the second period will be described.

The differential circuit 1 supplies a differential signal representing a value of 2 or less during the time interval between the input of the input read address “2” and the input write address “0” and the input of the input read address “5” and the input write address “7”. Output While the difference circuit 1 outputs a difference signal representing a value of 2 or less, the decision circuit outputs a high level decision signal. First, when the difference signal value output from the difference circuit 1 reaches " 2 " during the second period, the NOR circuit 9 receives the low level signal A and the low level signal B and the high level. Output the signal (C). In response to the high level signal C, the latch circuit 14 latches the generation write address " 7 " input at that time. The latch circuit 14 outputs the latched generation write address "7" as the signal J. In response to the high level signal C, the counter 10 outputs a predetermined jump address " 16 " as the counter value " 16 " on the rising edge of the next write clock. Subsequently, the counter 10 increments the previously input counter value in response to the leading edge of the write clock and outputs the incremental result. When the selector 11 receives the low level signal B, the selector 11 outputs the output of the D-type flip flop 13 as a generation write address. On the other hand, when the selector 11 receives the high level signal B, the selector 11 outputs the output of the counter 10 as a generation write address. Next, the differential circuit 1 receives the input read address "6" and receives the input write address "0". Further, the difference circuit 1 outputs a difference signal whose value is "6". At this time, the determination circuit 2 outputs a low level determination signal because the difference signal value is larger than two. Since the D-type flip-flop 12 outputs a decision signal delayed by one clock of the write train clock, this D-type flip-flop 12 has one clock of the write clock after the level of the decision signal goes low. Output the low level signal B delayed by. When the selector 11 receives the low level signal B, the selector 11 outputs the output of the flip flop 13. That is, the address generation circuit 3 outputs a signal obtained by delaying the input write address by one clock of the write clock as the generation write address. Since the value of the input read address does not coincide with the value "7" of the signal J during the second period, the address coincidence detection circuit 15 outputs a low level signal. Since the T type flip-flop 18 outputs the low level signal b, the selector 17 outputs an input read address. That is, the address generation circuit 3 outputs an input read address during the second period.

Next, the operation of the two-port memory during the third period will be described.

This period corresponds to the period while the absolute difference value between the input read address and the input write address is greater than two. The difference circuit 1 outputs a difference signal representing a value greater than two. Since the difference signal value is two or more, the determination circuit 2 outputs a low level determination signal. During this period, since the D type flip flop 12 of the write address generation circuit outputs the low level signal B, the selector 11 outputs the output of the D type flip flop 13. That is, the address generating circuit 3 outputs a signal obtained by delaying the input write address by one clock of the write clock as the generated write address. When the address match detection circuit 15 of the read address generation circuit receives the input read address "7", the address match detection circuit 15 outputs a high level signal. Then, when the input read address value becomes a value other than "7", the address match detection circuit 15 outputs a low level signal. The counter 16 responds to the high level signal a output from the address coincidence detection circuit 15 and, at the rising edge of the next read clock after inputting the high level signal to the counter 16, the predetermined jump address. (In this case, 16) is output as the counter value (16). The counter 16 then increments the previously output counter value in response to the leading edge of the read clock and outputs the incremental result. The T type flip flop 18 outputs the high level signal b in response to the signal a transitioning from the high level to the low level. The selector 17 outputs the output of the counter 16 while the high level signal b is input.

Next, the two-port memory operation during the fourth period will be described.

During the interval between the input of the input read address "2" and the input write address "0" and the input of the input read address "5" and the input write address "7", the differential circuit 1 displays a difference signal representing a value of 2 or less. Outputs While the difference circuit 1 outputs a difference signal representing a value of 2 or less, the difference circuit 2 outputs a high level determination signal. First, when the difference signal value output from the difference circuit 1 reaches " 2 " for the fourth period, the NOR circuit 9 receives the low level signal A and the low level signal B and the high level signal. Output (C). In response to this high level signal C, the latch circuit 14 latches the generation write address " 7 " input at this time and then outputs it as the signal J. FIG. After the high level signal C is input to the counter 10, the counter 10 outputs a predetermined jump address (in this case 16) as the counter value "16" on the rising edge of the subsequent write clock. Subsequently, the counter 10 increments the previously output counter value in response to the leading edge of the write clock and outputs the incremental result. The selector 11 outputs the output of the D-type flip flop 13 as a generation write address while receiving the low level signal B. As shown in FIG. On the other hand, when the selector 11 receives the high level signal B, the selector 11 outputs the output of the counter 10 as the selected write address. Next, when the difference circuit 1 receives the input read address "6" and the input write address "0", the difference circuit 1 outputs a difference signal whose value is "6". At this time, since the difference signal value is larger than 2, the determination circuit 2 outputs a low level determination signal. Since the D-type flip flop 12 outputs a determination signal delayed by one clock of the write clock, the D-type flip flop 12 is a low-level signal (delayed by one clock of the write clock after the determination signal becomes low level). Output B). When the selector 11 receives the low level signal B, the selector 11 outputs the output of the flip flop 13. Since the T type flip flop 18 outputs the high level signal b during the fourth period, the selector 17 outputs the output of the counter 16.

Next, the operation of the two-port memory during the fifth period will be described.

This period corresponds to the period while the absolute value of the difference between the input read address and the input write address is greater than two. The difference circuit 1 outputs a difference signal representing a value greater than two. The determination circuit 2 outputs a low level determination signal because the difference signal value is larger than two. During this period, since the D type flip flop 12 of the write address generation circuit outputs the low level signal B, the selector 11 outputs the output of the D type flip flop 13. That is, the address generation circuit 3 outputs the signal obtained by delaying the input write address by one clock of the write clock as the generation write address. The address agreement detection circuit 15 outputs a high level signal when it receives the value "7" of the input read address. Then, when the input read address value becomes a value other than "7", the address match detection circuit 15 outputs a low level signal. The counter 16, in response to the high level signal a, follows the predetermined jump address (in this case 16) at the rising edge of the next read clock after inputting the level signal a to the counter 16. It outputs as a counter value (16). The counter 16 then increments the previously output counter value in response to the leading edge of the read clock and outputs the incremental result. The T type flip flip 18 outputs the low level signal b in response to the signal a transitioning from the high level to the low level. When the low level signal b is input to the selector 17, the selector 17 outputs an input read address as a generation read address.

During the first to fifth periods, the write address decoder 5 decodes the generation write address and the read address decoder 4 decodes the generation read address. In addition, the memory 7 stores input data at an address corresponding to the output of the write address decoder 5 and outputs data from an address corresponding to the output of the read address decoder 4.

Although the present invention has been described with reference to exemplary embodiments, such description should not be interpreted in a limiting sense. It is apparent that various modifications can be made by those skilled in the art with reference to the present description as well as exemplary embodiments. Accordingly, the appended claims should be understood to cover any modifications within the substantial scope of the invention.

As described above, the two-port memory according to the embodiment of the present invention supplies two addresses having a desired address difference to the memory when the difference between the input read address and the input write address exceeds a predetermined value. Therefore, since a collision between addresses supplied to the memory can be prevented, malfunction of the storage device can be prevented. In addition, since there is no need to examine address control in the use of the two-port memory, the system can be easily constructed.

Claims (3)

A differential circuit for outputting a signal having a value corresponding to the difference value between the input read address signal and the input write address signal; A determination for outputting a determination signal having a first level when the signal value output from the difference circuit is within a predetermined value and a determination signal for outputting a determination signal having a second level when the value exceeds a predetermined value Circuit, A generation having received the input write address signal, the input read address signal and the determination signal and having a difference in signal value exceeding at least a predetermined value regardless of the difference between the input write address signal and the input read address signal An address generation circuit for outputting write and read addresses, A write address decoder for decoding the generated write address; A read address decoder for decoding said generated read address, and And a memory for storing input data at an address corresponding to the output generated from the write address decoder and outputting the output data from an address corresponding to the output generated from the read address decoder. A differential circuit for outputting a signal having a value corresponding to the difference value between the input read address signal and the input write address signal; A determination for outputting a determination signal having a first level when the signal value output from the difference circuit is within a predetermined value and a determination signal for outputting a determination signal having a second level when the value exceeds a predetermined value Circuit, Receives the input write address signal, the input read circuit address signal and the determination signal, outputs a generation read address signal from a generation read address terminal, and generates a generation read address signal from the generation write address terminal in response to the determination signal having the first level. Output a signal having a first value set as a difference value between the signal having the first value exceeding a predetermined value and the input write address signal, and generating the response in response to the determination signal having the second level. An address generation circuit for outputting a signal corresponding to the input write address from a write address terminal, A write address decoder for decoding the output obtained from the generation write address terminal, A read address decoder for decoding the output obtained from said generated read address terminal, and And a memory for storing input data at an address corresponding to the output generated from the write address decoder and outputting the input data stored at an address corresponding to the output generated from the read address decoder. A signal corresponding to the input read address signal and the input write address signal in response to a difference value between an input read address signal and an input write address signal having a period different from the input read address signal exceeds a predetermined value; Supplying a signal to the memory, and In response to the difference value being within a predetermined value, generating a generation read address and a generation write address having a difference signal value that exceeds at least the predetermined value and used to read data from and write data to the memory. And supplying the memory to the memory.

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