JPS6220177A - Time base correcting device - Google Patents

Abstract

PURPOSE:To decrease erroneous propagation and to correct a time base by so constituting the titled device that in case a synchronization address loses continuity to the immediately preceding content, the said address is not used if the said discontinuity occurs due to errors consecutive for N times or less. CONSTITUTION:A synchronizing signal detector 4 detects a synchronizing signal from an input signal and outputs it to a synchronization address reader 5, a counter 11, and a controller 12. The controller 12, when a write address is inputted to its adder 14, increments one-block address and outputs it to a comparator 15. Accordingly, the comparator 15 compares the synchronization address signal and a one-block adding value signal, And when they coincide with each other or do not coincide for consecutive N+1 times (where N is a natural number) or more, the comparator 15 outputs a first controlling signal from an output terminal 12d. Also, in case of the dissidence between them but for consecutive N times or less, a second controlling signal is outputted from the terminal 12d to the counter 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time axis correction device during recording and reproduction in a magnetic recording and reproducing device for digital signals.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional time axis correction device. In the figure, 1 is an input terminal into which an input signal is input, 2
is a reference terminal to which the reference signal shown in FIG. 5(C) is input, 3
4 is a storage device, 4 is a synchronous signal detector that detects and outputs the synchronous signal shown in FIG. 5 (sudden) from the input signal, and 5 is a synchronous signal detector that reads out the synchronous address shown in FIG. 5 (b) by inputting the synchronous signal. a synchronous address generator for outputting; 6 a counter for counting the synchronous addresses, generating and outputting a write address;
7 is operated by the input of the reference signal, as shown in FIG. 5(d).
A read address generator that generates and outputs the read address shown in FIG. 8 is a movable contact 9a and fixed contacts 8b and 8c.
9 is an output terminal.

Note that 10 is a write address generator composed of the synchronous signal detector 4, synchronous address reader 5, and counter 6.

Next, the operation of the time axis correction device having the above configuration will be explained.

First, the input signal input to the input terminal 1 is input to the storage device 3. The signal is input to a synchronization signal detector 4 and a synchronization address reader 5. The synchronization signal detector 4 detects the synchronization signal shown in FIG. 5(a) from the input signal and outputs it to the synchronization address serializer 5 and counter 6. Therefore, the synchronous address generator 5
operates every time the synchronization signal shown in Fig. 5 (&) is input,
The synchronization address shown in FIG. 5(b) is read out, and the counter 8
Output to.

This counter 6 counts the synchronization addresses shown in FIG. 5(b) every time the synchronization signal shown in FIG. 5(a) is input, generates a write address, and outputs it to the fixed contact 8b of the selector 8. do. On the other hand, the read address generator γ operates upon receiving the reference signal shown in FIG. 5(,) input through the reference terminal 2, generates the read address shown in FIG. Output to fixed contact 8C. Therefore, when the movable contact 8a of the selector 8 contacts the fixed contact 8b, the write address outputted from the counter 6 is transferred to the memory device fJ! via the fixed contact 8b and the movable contact 8 of the selector 8. The input signal can be written to the storage device 3 for input to t,3. Then, when the movable contact 8& of the selector 8 contacts the fixed contact 8C, the read address output from the read address generator γ is transferred to the fixed contact 8b of the selector 8 and the movable contact 8C.
Since the data is input to the storage device 3 via the data a, the time axis of reading to the storage device 3 can be corrected. For example 200~
When considering time axis correction that absorbs jitter (time axis fluctuation) of ±4 blocks, each block is approximately 1000 bits of data plus synchronization information and synchronization address information, and the write address and read address are If there are 4 blocks of address time difference, Figure 5(a)~
This can be shown in FIG. 5(d).

[Problem that the invention seeks to solve]

The above-mentioned conventional time axis correction device has an error in the synchronization address (1), as shown in FIG.
Assuming that the %5# block is read as the %31 block, the 13'th block output from output terminal 9 will read the data originally written to the 5# block, and similarly the 15th block will be read within the same cycle. Since nothing is written to the 15th block outputted from the output terminal 9, the data of the 5th block 8 blocks earlier, which was incorrect due to the input signal, is read out again.

Moreover, in general, the probability of erroneous synchronous addresses is higher than that of synchronous signals, so even if only the synchronous address is erroneous, there is a problem that the entire data of two blocks will be erroneous.

[Means for solving problems]

The time axis correction device according to the present invention compares the value that the counter can take when one more open period signal is input with the synchronization address at the time of waiting for the input of the synchronization signal, and determines whether they match or do not match, and the conditions thereof. The counter outputs the first control signal or the second control signal, and when the first control signal is input, the counter replaces the counted value with the value of the synchronous address and outputs it as a write address. By inputting the 2 control signal and directly outputting the counted value as a write address, the time axis in recording and reproducing digital signals is corrected.

[Effect]

In this invention, even if a synchronization address loses continuity with its immediately preceding contents, the propagation of the error can be reduced and the time axis can be corrected.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a time axis correction device according to the present invention. In the figure, 11 is shown in Figure 3 (b
), the third input terminal 11m receives the synchronization address shown in
It is equipped with an input terminal 11b to which the synchronization signal shown in FIG. When the synchronous address is counted and the first control signal is input to the input terminal 11e, the counted value is replaced with the synchronous address value, and the result shown in FIG.
) is outputted from the output terminal 11d as a write address, and when the second control signal is input, the counted value is outputted from the output terminal 11d as a write address, as shown in FIG. 3(e). , and a counter that is reset to the initial value when the count value reaches a value indicating the time length of the time axis correction range; 12 is an input terminal 12 & to which a synchronous address signal is input; and input terminal 1 to which a write address signal is input.
2b, an input terminal 12e for inputting a synchronization signal and an output terminal 12df for outputting a control signal; the counter 11;
Compares the value obtained when the synchronization signal is input one more time with the synchronization address at the time of input of the synchronization signal, and when the two match, or N +, 1 - (however, N is a natural number) or more The controller outputs the first control signal when they do not match consecutively, and outputs the second control signal if they do not match N times or less consecutively.The detailed circuit is shown in FIG. 2.

13 is the synchronization signal detector 4. Synchronous address generator5. The controller 1 shown in FIG. 2 is a write address generator composed of a counter 11 and a controller 12.
2, 14 is an adder that outputs a 1-block addition value shown in FIG. pu, 18 is and gate,
19 is Nantes Gate.

Next, the operation of the time axis correction device having the above configuration will be explained. First, an input signal input to the input terminal 1 is input to the storage device 3 and the synchronization bias W4.

This synchronization signal detector 4 detects the synchronization signal shown in FIG.
1 and the controller 12. Therefore, the synchronous address reader 5 operates every time the synchronous signal shown in FIG. 3(a) is input, and the synchronous address shown in FIG. . When the K write address is input to the adder 14 (see FIG. 2), this controller 12 increments by one block address and outputs the one-block added value shown in FIG. 3(d) to the comparator 15. . Therefore, the comparator 15 compares the synchronous address signal shown in FIG. 3(b) with the 1-block addition value number shown in FIG. 3(d) K, and when the two match, or
If there is a mismatch (N is a natural number) or more times in a row, the first control signal is output from the output terminal 12d, and even if the two do not match, if it is less than N times in a row, the second control signal is output from the output terminal 12d. Output to counter 11. Therefore, when the first control signal is input to the input terminal 11e of the counter 11, the counter 11 corrects the counted value by replacing the counted value with the value of the synchronous address as shown in FIG. from the output terminal 11d as the selector 8
When the second control signal is input to the fixed terminal 8b and the second control signal is input to the input terminal 11c, the counted value is shown in FIG. 3(e).
As shown in the l! It is output from the output terminal 11d to the fixed terminal 8b of the selector 8 as a write address.

Therefore, when the movable contact 8a of the selector 8 contacts the fixed contact 8b, the write address output from the counter 11 is input to the storage device 3 via the selector 8, so that the input signal is written to the storage device 3. be able to. and,
When the movable contact 81 of the selector 8 contacts the fixed contact 8C,
Since the read address output from the read address generator T is input to the storage device 3 via the selector 8, the time axis of reading to the storage device 3 can be corrected.
[Effects of the Invention] As explained in detail above, according to the time base correction device according to the present invention, when the synchronization address loses continuity with the immediately previous content, and when the error occurs N times or less consecutively,
By avoiding the use of synchronous addresses, the error υ
This has the effect of reducing the propagation of data and correcting the time axis.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the time axis correction device according to the present invention, Fig. 2 is a detailed circuit diagram of the controller shown in Fig. 1, and Figs. 3(,) to 3(d). 1 and 2, FIG. 4 is a block diagram showing a conventional time axis correction device, FIG. 5 (Jl) to FIG. 5(d), and FIG. 6(a) ), FIG. 6(b) is a diagram showing the waveforms of each part in FIG. 4. 1...Input terminal, 2...Reference terminal, 3...'
- Storage device, 4... Synchronous signal detector, 5... Synchronous address reader, T... Read address generator,
8・Φφ・Selector, 9 fist-...output terminal, 11...Φ
#F counter, 12... Φ controller, 13... write address generator, 14 reference... adder, 1511... comparator, 16 and 11... D7 lip-flop.

Claims (1)

[Claims] A storage device that temporarily stores input signals to correct the time axis, a write address generator that synchronizes with the input signal and generates an address for writing the input signal to the storage device, and a write address generator that synchronizes with the input signal and generates an address for writing the input signal to the storage device. In a time base correction device equipped with a read address generator that generates an address when reading data, the synchronous address is counted for each synchronous signal, and when the first control signal is input, the counted value is set as the synchronous address. Replace it with a value, output it as a write address, and write the second
A counter that outputs the count value as a write address when a control signal is input, and a value that this counter can take when the synchronization signal is input one more time and the synchronization address are compared at the time of input of the synchronization signal, When both match or N
+1 times (however, N is a natural number) or more consecutively when they do not match, outputs the first control signal, and even if the two do not match, if N times or less consecutively, outputs the second control signal. Features a time axis correction device.