JPH0344394B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention divides one block of a medium for recording/reproducing information into N records, and each record is marked with a record mark or a check character to prevent record errors. The present invention relates to an error correction method for a recording/reproducing apparatus that uses a data format that can be detected.

(b) Background of the Technology Recently, technology for converting information into digital values and recording/reproducing them has been put into practical use using various methods in various devices ranging from computer systems to home appliances.

The information to be recorded/reproduced is important in any case and generally requires high reliability. In order to obtain the required highly reliable recorded/reproduced information, various methods have been implemented to detect and correct errors that have occurred, but there is a need for more detailed error correction methods to be put to practical use.

(c) Prior Art and Problems A conventional error correction method during information reproduction will be explained with reference to the drawings.

Figure 1 shows information (hereinafter referred to as data) recorded/
The data format of the medium to be reproduced is shown, and A shows the data format of one block, and B shows the data format of A divided into records and rearranged vertically.

In the figure, 1 is a data block, 2 is a record, 3 is a sync byte, 4 is a data byte, 5 is an error check code (CRCC), 6 is an error correction code, and 7 is a code word. Note that the error correction code 6 is composed of 2 bytes, ECC ₁ and ECC ₂ . This data format is used for technical or theoretical reasons when recording/reproducing data.
Data block 1, which is a collection of records that can be handled as one entity,
Records 2 and data blocks 1 are collections of a certain amount of data for handling data.
sync byte 3 indicating the start of record 2, data byte 4 indicating the data in record 2, error check code 5 checking for errors in the entire data byte 4 of record 2, error checking code 5 for errors occurring in code word 7. It is constituted by an error correction code 6 having the ability to correct errors, a code word 7 which is a collection of columns of data bytes 4 of each record 2.

Here, when using error check code 5,
Error correction code (ECC ₁ and
The error correction ability of ECC 6 (consisting of ECC ₂ ) is limited to two errors (two bytes) that occur within the corresponding code word, and the error correction ability of only error correction code 6 is limited to up to two errors (two bytes) occurring within one code word 7. Up to one error (one byte) can occur.

Note that when an error check code is used, as will be described later, the code itself is not used, but a "pointer" which is an error record number generated using this code is used.

Now, the error correction ability of the conventional method is that if the error correction is performed using an error correction code and a pointer, one data block 1 can correct two errors.
record 2 (for example, record No. B in Figure 1).
Only errors that occur in records 1 and 2) can be corrected; if an error occurs in three or more records 2, an error will occur even if the error is distributed in 1 byte in each code word 7. correction becomes impossible.

On the other hand, the method of performing error correction using only the error correction code 6 has the disadvantage that if two or more errors occur in one code word 7, the errors cannot be corrected or the error is incorrectly corrected since there is only one error correction capability.

(d) Purpose of the Invention The purpose of the present invention is to provide a new error correction method that eliminates the above-mentioned drawbacks, and in particular, the drawbacks of the method of correcting errors using pointers and the method of correcting errors using only error correction codes. The objective is to realize an error correction method that complements each other's shortcomings and takes advantage of the characteristics of each.

(e) Structure of the Invention The present invention provides data having a plurality of records consisting of a plurality of data, and a record consisting of a plurality of error correction codes in which a collection of data at the same address in each record is an error correction unit. It is a block and has an error check code for each record, so it is possible to detect a record in which an error has occurred, and the error correction code can correct errors over a predetermined number of records if the record in which an error has occurred is known in advance. It is also a data block configured so that errors can be corrected in at least one record even if they are not known in advance, and when the data block is played back, an error is detected using an error check code, and the record in which the error was detected is checked. In an error correction method that uses a pointer to display a record and corrects the record indicated by the pointer using an error correction code, if the number of records in which errors are detected by the error check code is less than or equal to a predetermined number, the pointer and the error correction code If the number of records in which errors are detected by the error check code is greater than a predetermined number, the pointer is invalidated, and the error that can be corrected by the error correction code is corrected using the error correction code. This can be achieved by an error correction method that makes it possible to correct errors that randomly occur in three or more records using an error correction code in each code word.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows a circuit diagram of the error correction method according to the invention.

In the figure, 8 is a read register, 9 is an exclusive OR circuit, 10, 13, and 19 are inverting circuits, and 11
is a register circuit for cyclic redundancy check (hereinafter abbreviated as CRC); 12 is an all '0' detection logic circuit;
4, 15, and 16 are AND circuits, 17 is a pointer counter circuit, 18 is a decoder circuit, 20, 21 is a register circuit, and 22 is a flip-flop circuit, respectively. Here, 8 to 13 are component parts of the error check means in the claims, 14 and 17 are component parts of the error record counter means, 15,
Reference numerals 16, 18 to 21 are components of the pointer generation means, and 22 is a component of the present invention. This embodiment includes a read register 8 that temporarily stores read data, an exclusive OR circuit 9 that checks for errors in one record 2 using a CRC register 11, and a record start that occurs at the start of reading each record. A NOT circuit 10 that guides the pulse to the CRC register 11, and a CRC circuit that inspects the data input from the read register 8 byte by byte using the exclusive OR circuit 9 and the output of the CRC register 11, and temporarily stores the results. register circuit 11,
All '0' detection logic circuit 1 that detects all '0' from the signal output from the CRC register 11
2. A negation circuit 13 that outputs a negation signal of the output of the all '0' detection logic circuit 12, a logic that performs an AND calculation between the signal from the negation circuit 13 and the record end timing signal generated at the end of reading each record. A product circuit 14, an AND circuit 15 that calculates the AND of a signal from the AND circuit 14 and a signal from the NOT circuit 19 (PCNT0), a signal from the AND circuit 14 and a signal from the NOT circuit 19 (PCNT1)
and a pointer counter circuit 17 that counts the signals from the AND circuit 14 and outputs the counted value as a pointer count value to the decoder circuit 18, and a pointer count from the pointer counter circuit 17. A decoder circuit 18 that identifies the value and converts it into each output signal, a negation circuit 19 that extracts a negation signal of the signal from the decoder circuit 18, and temporarily stores the signals from the AND circuits 15 and 16 and the read record number. register circuits 20 and 2 that output the signals of pointer 0 and pointer 1 to an ECC logic circuit (not shown);
1. The signal from the AND circuit 14 is used as a clock.
Signal from negative circuit 19 (PCNT2) to CK terminal
is input to the J terminal, and a '0' signal is input to the K terminal, but the J
When a '1' signal is input to the terminal, an ECC logic circuit (not shown) sends a pointer disable signal indicating invalidity of pointer 0 and pointer 1 from the output terminal.
It is composed of a flip-flop circuit 22 which outputs an output to.

Now, the first record 2 in data block 1
Data is read from (record No. 1), data byte 4 stored in read register 8 is taken out, and the presence or absence of an error is checked by a circuit consisting of exclusive OR circuit 9 and CRC register circuit 11. (1) If there are no errors in the record If no errors are found as a result of checking,
Since all eight outputs of the CRC register circuit 11 output '0' signals, the all 0 detection logic circuit 12 detects all 0's and outputs a '1' signal. Therefore, the NOT circuit 13 outputs a '0' signal to the AND circuit 14, which turns off the circuit 14, and outputs a '0' signal to the pointer count circuit 17 and the AND circuits 15 and 16.

The pointer counter circuit does not perform a counting operation, and the pointer counter value 0 is set to the decoder circuit 18.
The decoder circuit decodes the '0' signal and outputs the '0' signal as PCNT0 to the AND circuit 15 via the NOT circuit 19, so that the circuit 15 is turned off.

For this reason, even if the read record number is input to the register circuit 20, it cannot be taken in, and the pointer 0 is in a state of all 0s. In other words, this indicates that no error record has been found yet.

(2) If there is an error in the record If an error is found as a result of checking,
The CRC register circuit 11 outputs a '1' signal to one of eight output signals. The all '0' detection logic circuit 12 detects a '1' signal and outputs a '0' signal to the NOT circuit 13. Negation circuit 1
3 outputs a '1' signal, which is a negation signal of the input, to the AND circuit 14. When the record end timing signal generated at the end of the record 2 (No. 1) being read is input, the AND circuit 14 performs an AND operation between the record end timing signal and the input signal '1' from the NOT circuit 13. , outputs a '1' signal to the pointer counter circuit 17. Here, the record end timing signal is obtained by counting the number of bytes from the sync byte SB shown in FIG. Ru.

This '1' signal becomes the counting clock of the pointer counter circuit 17. Pointer counter circuit 1
7 outputs the counted pointer counter value to the decoder circuit 18. The decoder circuit 18 decodes the input pointer counter value and outputs a '1' signal as PCNT0 to the AND circuit 15 via the NOT circuit 19. The register circuit 20 receives the '1' signal from the AND circuit 15 and the number No. of record 2.
1 and ECC logic circuit (not shown)
output as pointer 0 signal. The ECC logic circuit (not shown) uses this input signal to correct the error that occurred in record 2 No.1.

Next, if an error occurs when No. 2 record 2 is read, a '1' signal is output as PCNT1 through the same route, and pointer 1 of the output of this register circuit 21 is transferred to the ECC logic circuit (not shown). used to correct errors.

Here, pointer 0 indicates the number of the first error record found, that is, the position information of the error record, and pointer 1 indicates the position information of the next error record found.

For example, if an error occurs in record No. 1 and record No. 2, pointer 0 and pointer 1
is output, it is known that an error has occurred in record No. 1 and record No. 2 shown in Figure 1B.
The error correction codes ECC ₁ and ECC ₂ use this information to correct errors that have occurred in the two records (this is called first error correction).

Furthermore, if an error occurs when record 2 of No. 3 is read, a '1' signal is output as PCNT2. While this '1' signal is being output, the output of the AND circuit 14 becomes '1', the flip-flop circuit 22 outputs a '1' signal, and this output signal is sent to the ECC logic circuit (not shown). Output. ECC logic circuit (not shown)
receives this signal as a pointer disable signal, and thereafter the first error correction using pointer 0 and pointer 1 is disabled, and the second error correction function using error correction codes ECC ₁ and ECC ₂ for each word is disabled. Switch to error correction method.

(g) Effects of the invention With the invention as described above, even if there are three or more records in which an error has occurred, errors that occur randomly in multiple records can be corrected within the range that can be corrected by the ECC of each code word. This has the effect of providing an error correction method that can

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the data format of one block of a medium for recording/reproducing data, and FIG. 2 shows a circuit diagram of an error correction method according to the present invention. In the figure, 1 is a data block, 2 is a record, 3 is a sync byte, 4 is a data byte, 5 is an error check code, 6 is an error correction code, 7 is a code word, 8 is a read register, and 9 is an exclusive OR circuit, 10, 13, 19 are negative circuits, 11
is a CRC register circuit, 12 is an all '0' detection logic circuit, 14, 15, 16 are AND circuits, 17 is a pointer counter circuit, 18 is a decoder circuit, 2
0 and 21 are register circuits, and 22 is a flip-flop circuit, respectively.

Claims (1)

[Scope of Claims] 1. A data block having a plurality of records consisting of a plurality of data, and a record consisting of a plurality of error correction codes in which a collection of data at the same address in each record is an error correction unit. Since each record has an error check code, it is possible to detect a record in which an error has occurred, and the error correction code enables error correction over a predetermined number of records if the record in which an error has occurred is known in advance. This is a data block that is constructed in such a way that it is possible to correct errors in at least one record even if the error is not detected.When the data block is played back, errors are detected using an error check code, and the record in which the error was detected is displayed with a pointer. However, in an error correction method in which the record indicated by a pointer is corrected using an error correction code, if the number of records in which an error is detected by the error check code is less than a predetermined number, the record indicated by the pointer is corrected using the pointer and the error correction code. The error is corrected, and if the number of records in which an error is detected by the error check code is greater than a predetermined number, the pointer is invalidated, and the error correctable by the error correction code is corrected using the error correction code. How to correct errors.