JP2603613B2 - Information storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method for a digital information storage device, and more particularly to a method for generating an erasure flag required for an error correction code.

[Conventional technology]

FIG. 4 is a diagram corresponding to the recording format of the information storage device shown in, for example, page 205 of Nikkei Electronics November 21, 1983 issue. However, the code configuration and the like are different. In the figure, reference numeral 1 denotes a preamble section, which is a section for facilitating generation of a clock at the time of information reproduction.
This is a section in which a pattern having a characteristic having a high periodicity, for example, “100” is repeatedly recorded. The synchronizer 2 is a section having a unique pattern for performing data synchronization of the data part 3, and the synchronizer 2 is periodically arranged in the data part 3 in addition to the head of the data part 3. In the example of FIG. 4, a 1-byte synchronization unit is added for every 12 bytes. The recording direction of the information device is D in the data section 3 following the preamble section 1 and the synchronization section 2.
1, D131, D261, D391, D2, D132,...

On the other hand, four error correction codewords are provided in the horizontal direction. One codeword is composed of 130 bytes of digital information and 16 bytes of check symbols, and has a Hamming distance of 17 (146,130,1).
7) Reed-Solomon code. The correction capability of the Reed-Solomon code is based on the number E of erroneous data whose error position is unknown.
Assuming that the number of error data at which the error position is found is F and the Hamming distance is D, correct correction processing can be performed within a range satisfying F + 2 · E <D (1). However, since the error position is usually unknown, 2 · E <D (2).

[Problems to be solved by the invention]

In the above-described recording format, a case where a reproduction error as shown in FIG. 5 occurs due to a defect of the recording medium or the like. In the error A, since the data reproduction failure continues for a long period of time, a bit slip occurs in the reproduction clock, that is, when the number of the reproduction clocks is deviated from the number of data, the data is out of synchronization. The data becomes erroneous until the synchronization unit 2 is detected. That is, the data part indicated by the symbol △ in the figure becomes an error. Short errors such as error B do not cause a bit slip. In the error example of FIG. 5, the error A causes a 7-byte error in each error correction codeword. Therefore, in this example, even if there is no means for specifying the error position, only one byte error can be corrected.

The method of correcting the (146,130,17) Reed-Solomon code is not described in detail here, but for example, US Pat.
162,480 and IEICE PRL73-77 (1974/1)
Month).

As described above, in the conventional apparatus, an error due to a bit slip cannot be specified, that is, error correction must be performed while the error position is unknown, and there is a problem that the bit slip becomes a heavy burden at the time of error correction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to specify the position of an error due to a bit slip, set an erasure flag on data based on the information, and effectively use the correction capability of an error correction code. An object is to obtain an information storage device.

Here, considering the recording formats shown in FIGS. 4 and 5 in more detail, as described above, the synchronization unit 2
Are periodically arranged in the data.For this reason, if the interval between the detection of one synchronization part and the detection of the next synchronization part is counted, a normal value indicates a predetermined value. If a bit slip occurs during that time, a count value different from the above-mentioned predetermined value will be obtained. Therefore, it is considered that the position of the error due to the bit slip can be specified by the counted value.

[Means for solving the problem]

Therefore, the information storage device according to the present invention forms an error correction codeword from digital information and a check symbol, divides this error correction codeword into a plurality of blocks equally, and uses a data synchronization pattern for each of the divided blocks. In an information storage device that stores the error correction codeword with a synchronization unit having, a synchronization detection unit that detects a synchronization unit from stored information, and a measurement unit that measures an interval at which the synchronization unit is detected. When the detection interval of the synchronous unit is not a predetermined value, the immediately preceding synchronous unit of the first synchronous unit whose detection interval first differs from the predetermined value, and the detection interval is equal to the predetermined value. Bit slip section detection means for detecting a section including a bit slip between the different synchronization sections, and digital information or a check symbol of the section including the bit slip. And erasure flag generation means to make a loss flag is obtained by so and a decoding means for decoding the error correction code words by using the erasure flag.

[Action]

According to the present invention, by counting the interval between the synchronization units, a data reproduction error position due to a bit slip can be specified, an erasure flag is set at the position, and the capability of the error correction code is effectively used.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the basic principle of the present invention will be described with reference to FIG. In FIG. 2, reference numeral 2 denotes a synchronization unit, and reference numeral 3 denotes a data unit. Crosses indicate erroneous locations due to defects in the medium and the like. Here, it is assumed that a bit slip has occurred in the error A. The synchronization section 2 is periodically inserted into the data section 3, and when the detection interval of the synchronization section 2 is counted, in the example of FIG. 2, it is normally detected every 13 × n bytes. Normally, n is 1. However, when the synchronization unit 2 cannot be detected due to an error, counting is performed up to the next synchronization unit 2, so that n is an integer value of 2 or more. However, when a bit slip occurs, the detection interval of the synchronization unit becomes a value different from 13 × n bytes.

Therefore, when the detection interval of the synchronization unit is different from 13 × n bytes, a loss flag is set for the data from the synchronization unit 2 detected immediately before to the synchronization unit 2 correctly detected next (arrow in the figure).

FIG. 1 shows an embodiment of the present invention based on such a basic principle. 4, reference numeral 4 denotes an input terminal of a reproduction signal, 5 denotes a clock reproduction unit, and 6 denotes a synchronization unit 2 in FIG.
Is a counter for counting the detection interval of the synchronization signal. 8 is a timer which becomes "0" by the output of the counter 7, 9 is a counter which outputs the frame number indicating the number of the detected synchronous unit from the head, 10 and 11 are registers, and 12 is a bit. This is an erasure flag generation unit that sets an erasure flag on data of a frame including a slip. 13 is a data reproducing circuit for decoding a reproduced signal, 14 is an error correction unit for performing error correction, 15 is an output terminal, 16 is an inverter circuit, and 17 is a gate circuit.

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 1, and the operation will be described below with reference to FIG.

The reproduction signal a obtained from the recording medium is input from the input terminal 4 and sent to the clock reproduction unit 5 and the synchronization detection unit 6. In the clock reproducing unit 5, a clock necessary for decoding the reproduced signal is created, and in the synchronous detecting unit 6, the synchronous unit 2 shown in FIG. 2 is detected and the synchronous detecting signal b is output. The counter 7 outputs a signal c every 13 bytes, which is the interval of the synchronization unit 2. This counter 7 has been reset by the synchronization detection signal b. The output c of the counter 7
Is inverted by the inverter 16 to become a signal d, which is input to the gate 17 together with the synchronization signal detection signal b. The output e of this gate 17 becomes low when a synchronization part is detected at a position other than the scheduled position of the synchronization part 2. When the timer 8 detects the output c of the counter 7, it becomes “0” and generates a signal f that becomes “1” after a certain time. The counter 9 is reset when the synchronization detecting section 6 detects the leading synchronization section 2 immediately after the preamble section 1, and counts with the signal f. Therefore, the output signal g of the counter 9 is the synchronization signal in the data section of the reproduced signal. The frame number indicates the number of the part 2 from the top.

The register 10 temporarily stores the frame number each time the synchronization unit 2 is detected, and the register 11 stores the contents of the register 10 and the frame number output from the counter 9 when the signal e becomes "0". . Therefore, the output x of the register 11 is the synchronization unit 2 detected immediately before the error A in which the bit slip has occurred.
And the output y is the frame number (i) corresponding to the synchronization unit 2 detected for the first time after the bit slip.
+2) is output. The erasure flag generation unit 12 receiving the outputs x and y generates an erasure flag in the data of the frame including the bit slip, and outputs this to the error correction unit 14. Here, the disappearance flag corresponds to the arrow in FIG. In the data reproducing circuit 13, the data is decoded to "1" and "0" by the synchronization detection signal b and the clock generated by the clock reproducing unit 5.

Here, the erasure flag is also generated in the error-free data in FIG. Although this is disadvantageous for the error correction code, there is a great advantage that an erasure flag is set at an error portion. That is,
In the example shown in FIG. 2, the number of erasures due to the error A is nine.
Therefore, from the above equation (1), F = 9, and 9 + 2 · E <
The remaining error correction capability can be calculated in 17 and 3 bytes (E
= 3) capable of correcting data errors. On the other hand, the expression (2) is applied to the error correction power when there is no erasure flag, and only one byte error can be corrected correctly.

Although the above example is one example, considering that errors occur intensively when a bit slip occurs, the means for specifying the position where the bit slip occurs is effective for improving the error correction capability. .

In the above embodiment, the method of setting the erasure flag is performed by focusing on the frame number. However, another method may be used.

〔The invention's effect〕

As described above, according to the information storage device of the present invention, an error correction codeword is composed of digital information and a check symbol, and the error correction codeword is equally divided into a plurality of blocks. A synchronization unit having a pattern for data synchronization and storing the error correction codeword in the information storage device, a synchronization detection unit for detecting the synchronization unit from the stored information, and an interval for detecting the synchronization unit. Measuring means for measuring the synchronization interval, the synchronization unit immediately before the first synchronization unit whose detection interval first became different from the predetermined value when the detection interval of the synchronization unit is not a predetermined value, and the detection interval A bit slip section detecting means for detecting a section including a bit slip between the synchronizing section having a value different from the predetermined value, and digital information of the section including the bit slip is not provided. Since the apparatus includes erasure flag generation means for setting an erasure flag on a check symbol and decoding means for decoding the error correction codeword using the erasure flag, an erasure flag indicating an error position can be set, and There is an effect that the error correction capability of the storage device can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information storage device according to an embodiment of the present invention, FIG. 2 is a diagram showing a recording format for explaining the operation, FIG. 3 is a time chart of the device shown in FIG. FIG. 4 is a diagram showing a recording format of a conventional information storage device, and FIG. 5 is a diagram for explaining a conventional error correction capability. 2... Synchronization section, 3... Data section, 6... Synchronization detection section, 7
... A counter for counting the detection interval of the synchronization unit, 12... A lost flag generation unit, and 13 an error correction unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toru Inoue 5-1-1, Ofuna, Kamakura-shi In-house Research Institute of Electronics and Information, Mitsubishi Electric Corporation (56) References JP-A-60-89873 (JP, A)

Claims (1)

(57) [Claims] An error-correcting codeword is composed of digital information and a check symbol, the error-correcting codeword is equally divided into a plurality of blocks, and a synchronizing unit having a data synchronization pattern is provided for each of the divided blocks. An information storage device for storing the error-correcting codeword attached thereto; a synchronization detection unit for detecting a synchronization unit from the stored information; a measurement unit for measuring an interval at which the synchronization unit is detected; When the detection interval is not the predetermined value, the detection interval differs from the predetermined value at the first immediately before the first synchronization unit where the detection interval became different from the predetermined value, and the detection interval became different from the predetermined value. A bit slip section detecting means for detecting a section including a bit slip between the synchronization section, and an eraser for setting an erasure flag on digital information or a check symbol in the section including the bit slip. An information storage device comprising: a lost flag generating means; and a decoding means for decoding the error correction codeword using the lost flag.