KR880002411Y1 - Interflation circuit of digital-audio tape recorder - Google Patents

Abstract

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Description

Interpolation Circuit of Digital-Audio Tape Recorder

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: Decoder 2, 3, 7: 1st to 3rd Shift Register

4: Full adder 5: Control circuit

6, 8: 2x1 multiplexer AD1, AD2: AND gate

DF1 ~ DF3: 1st ~ 3rd D flip flop

The present invention relates to an INTERPOLATION circuit of a digital audio tape recorder. In particular, after reading normal data before and after one error data, which can not be compensated by a decoder, among simple noises. By selecting the intermediate value thereof, the present invention relates to an interpolation circuit of a digital-audio tape recorder that compensates for data close to normal data.

In a conventional cassette tape recorder, an analog audio signal is recorded and reproduced on a magnetic tape. At this time, the analog audio signal is continuously changed in value with time, and used in a digital audio tape recorder. The signal is a PCM (Pulse Code Modulation) signal, in which an analog audio signal is sampled at a predetermined time interval (SAMPLING), and encoded according to the level.

As described above, the digital-audio tape recorder detects data read from the magnetic tape (for example, digital data such as straight and offset binary and binary complements), and then errors due to noise and other errors. Detecting the error, the decoder corrects the error. In order to correct the error in the decoder, the parity bit is added to the normal data during recording, and the error is corrected by using the parity bit during playback. The parity bit detects whether each bit is "0 (Low)" or "1 (High)" in the data, and sets the parity bit to the number of "0 (Low)" or "1 (High)" of each bit. In addition, the parity bit is always adjusted to be odd so as to be "1 (High)" or "0 (Low)". However, the error that can be corrected among the generated errors is corrected by the decoder, but depending on the generated error, the decoder cannot be corrected. When the error is sent to the digital / analog converter, it is clear. The drawback of not being able to reproduce the analog audio signal is generated.

The present invention is designed to eliminate the above-mentioned drawbacks, and compensates for simple error data that can be corrected in a decoder of a digital-audio tape recorder, and then replaces one error data that cannot be compensated with the median value of normal data before and after. The present invention relates to an inflation circuit that allows a value similar to normal data to be selected.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a data output terminal of a known decoder 1 that compensates for simple error data among the errors read from the columns and rows of the magnetic tape on which the PCM signal is recorded, when the digital-audio tape recorder is reproduced. Respectively connected to the data input terminal of the first shift register 2, and the data output terminal of the first shift register 2 connects the second shift register 3 to the data input terminal of the full adder 4, respectively. The output terminal of the gate AD1 is passed through a control circuit 5 composed of first to third D-type flip-flops DF1-DF3, a 2x1 multiplexer 8, and an AND gate AD2. 1 is connected to the control terminal S of the multiplexer 6, and the data output terminal of the second shift register 3 and the output terminal of the full adder 4 are connected to the data input / output terminals of the 2x1 multiplexer 6; Connect the inputs of (Carry, Sn-1… SO) and the third shift register (7), respectively. The output terminal of the third shift register 7 is connected to a data output terminal OUTPUT and a data input terminal of the full adder 4, respectively, and includes first to third shift registers 2, 3, 7 and 1, respectively. The third D flip-flops DF1 to DF3 have a structure that can be controlled by a clock pulse by a known decoder 1.

Unexplained symbols D, Q, Denotes an input / output terminal of the first to third D flip-flops DF1 to DF3.

The present invention having the above-described structure compensates for a simple correctable error among errors generated by the magnetic tape in the known decoder 1, and then reconstructs one (nbit) error data that cannot be compensated. An interpolation circuit that selects an intermediate value of the normal data and compensates the error data with data close to the normal data. For example, n-bit data sequentially includes the normal data a1 and the error data a2. If the data is supplied to the decoder in the order of normal data a3, normal data a4, etc., the data a1, a2, a3, a4 are sequentially input to the first shift register 2; It is supplied to the input terminal of the AND gate AD1, and the clock signal by the known decoder 1 is the clock terminal of the first to third shift registers 2, 3 and 7 and the first to third D-types. Supply them to the clock stages of the flip-flops DF1 to DF3, respectively.

Under the above conditions, first, an AND gate for determining whether or not normal data a1 of n bits is applied to the data input terminal of the first shift register 2 at the output terminal of the decoder 1 is also normal data. The clock signal is supplied to the input terminal of AD1, and in this state, the normal data a1 is latched to the first shift register 2 and the output of the AND gate AD1 becomes 0 (Low). Data is composed of n-1 bit signal and 1 bit parity bit. If all n-1 bit signals become 1 (High), 1 bit parity bit becomes 0 (Low), and normal data always Since 1 (High) and 0 (Low) are in a mixed state, the output signal of the AND gate AD1 is always 0 (Low) by such data.

Subsequently, the error data a2 not corrected by the decoder 1 is input to the first shift register 2 and the AND gate AD1 with all bits set to 1, and when a clock signal is applied at this time, In addition, normal data a1 is latched in the second shift register 3, error data a2 is latched in the first shift register 2, and a first D-type flip-flop is included in the second D flip-flop DF2. Since the 0 (Low) signal, which was the output of DF1, is latched, and the error data a2 is an error signal in the first D-type flip-flop DF1, all bits are 1 (High), so that the AND gate AD1 Output becomes 1 (High), and the 1 (High) state is latched.

In this state, the AND gate AD2 is in a 0 (Low) state, so this signal is input to the control terminal of the 2x1 multiplexer 6 (8), and the normal data in the multiplexer 6 is normal. (a1) is selected, and the 2x1 multiplexer 8 selects and outputs the output Q of the second D-type flip-flop DF2. Subsequently, when the normal data a3 is applied to the first shift register 2 and the AND gate AD1, the output of the AND gate AD1 becomes 0 (Low).

When the shift clock is applied in this state, since the normal data a1 has maintained the state of 0 (Low) of the AND gate AD2, the third shift register 7 is provided through the 2x1 multiplexer 6. ), The error data a2 is latched in the second shift register 3, and the normal data a3 is latched in the first shift register 2, respectively.

At the same time, the 0 (Low) signal, which is the output Q of the second D-type flip-flop DF2, was output through the 2x1 multiplexer 8 because the output of the AND gate AD2 was 0 (Low). The high signal, which is latched on the third D flip-flop DF3 and the output Q of the first D flip-flop DF1, is latched on the second D-type flip-flop DF2, and the AND gate ( The 0 (Low) signal, which is the output of AD1), is latched on the first D flip-flop DF1.

In this state, that is, the output Q of the first D-type flip-flop DF1 is 0 (Low), the output Q of the second D-type flip-flop DF2 is 1 (High), and the third D-type. Since the clock signal is input while the output Q of the flip-flop DF3 is 0 (Low), and the output of the AND gate AD2 is 1 (High), the 2x1 multiplexer 6 Instead of the output of the second shift register 3, the output of the full adder 4 is selected and input to the third shift register 7, and in the 2x1 multiplexer 8, the second D flip-flop is provided. Output of (DF2) ) Is input to the third D flip-flop DF3.

At this time, looking at the operating state of the full adder 4, a value (a1 + a3) obtained by adding the normal data a1 and the normal data a3 of the first shift register 2 to the third shift register 7 is added. The outputs of the full adder 4 are output to the output terminals Carry, Sn-1, ... S1, S0.

However, what is needed for correction is the intermediate value of both data, so that the output of the full adder 4 is equal to one divided by two when shifted by one digit to the LSB. When is selected, the desired corrected data ((a1 + a3) / 2) is obtained.

Subsequently, when the clock pulse is applied while the normal data a4 is output from the decoder 1, the normal data a4 is applied to the first shift register 2, and the AND gate is applied to the third shift register 7. Since the output of (AD2) was 1 (High), the corrected data ((a1 + a3) / 2), which is the output of the full adder 4, is latched, and the second shift register 3 has normal data a3. In the first shift register 2, normal data a4 is latched.

At the same time, the output of the second D-type flip-flop DF2 is output to the third D-type flip-flop DF3. ), The 0 (Low) signal is latched, and the 0 D (Low) signal, which is the output of the first D flip-flop DF1, is input to the second D flip-flop DF2, and the first D flip-flop ( Since the 0 (Low) signal, which is the output of the AND gate AD1, is latched on the DF1, the output of the AND gate AD2 becomes 0 (Low) again, and the second shift register 3 is driven by the next clock signal. Selects the normal data a3 and applies it to the third shift register 7. At the same time, the output Q of the second D flip-flop DF2 is transferred to the third D flip-flop DF3. ) Is applied.

Therefore, in the third shift register 7, the intermediate value of the normal data a1 (a3) is latched with the data ((a1 + a3) / 2) taken, and then the normal data (a5) from the decoder 1 Is supplied to the first shift register 2 and the AND gate AD1, respectively, the error data a3 latched in the third shift register 7 is compensated for as data ((a1 + a3) / 2). It is sent to the data output terminal (OUTPUT).

Therefore, the error data a2 between the normal data a1 and a3 passing through the data output terminal OUTPUT is supplied to the digital / analog converter as compensated data ((a1 + a3) / 2). It is possible to reproduce a clean analog signal almost identical to the original signal.

As described above, the present invention selects error data that cannot be corrected by the decoder among the errors generated in the tape rows and columns of the digital-audio tape recorder as an intermediate value of the normal data before and after the error data, and selects the error data. There is an advantage to compensate as data close to normal data.

Claims (1)

Among the errors read from the columns and rows of the magnetic tape on which the PCM signal is recorded, the data input terminals of the AND gate AD1 and the first shift register 2 are respectively provided at the data output terminals of the known decoder 1 which compensates for simple error data. The data output terminal of the first shift register 2 is connected to the data input terminals of the second shift register 3 and the full adder 4, respectively, and the first gate to the third gate D1 to the AND gate AD1. The control terminal S of the 2x1 multiplexer 6 is passed through the control circuit 5 consisting of the type flip-flops DF1 to DF3, the 2x1 multiplexer 8, and the AND gate AD2. The output terminal of the second shift register 3, the output terminal of the full adder (Carry, Sn-1,... S1, S0) and the third shift register ( 7) are respectively connected to the output terminal of the third shift register (7) and the data output terminal (OUTPUT) and Audio tape inter inflation circuit of the-adder 4 hayeoseo connect the data input terminal of each of the decoder (1) a single error in the data which could not be compensated between normal digital data to give to compensate the nearest data to normal data in.