JPS58161420A - Monolithic analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain a converter having high reliability, without using externally mounted components, by frequency-dividing a clock inputted from an external clock input terminal and incorporating a clock frequency selecting circuit capable of selecting an arbitrary frequency clock. CONSTITUTION:The titled converter is applied to an integrating A/D converter, and a clock frequency selecting circuit 11 is provided between a clock input terminal 1 and a logic control circuit 3. An analog input signal is applied to an integration circuit 12 via a multiplexer 9 and integrated for a prescribed time. A reference voltage is applied to the circuit 12 and a time from this moment to the time when the output of the circuit 12 comes to less than the threshold voltage of a comparator 8, is counted at a counter 13. The counter 13 is operated in synchronizing with an external clock frequency-divided at the circuit 11. The result of count of the counter 13 shows the result of digital conversion of an analog input signal and is outputted externally via an output register and an output buffer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic analog-to-digital converter, and in particular, to a monolithic analog-to-digital converter, the present invention relates to a monolithic analog-to-digital converter. Concerning analog/digital converters.

Conventionally, analog-to-digital converters (hereinafter referred to as A/D converters) are often used as peripheral components of microcomputers. In this case, A/
L) The converter clock is the microcomputer clock,
It is desirable for the system configuration to be the same as the original.

However, as the speed of microcomputers increases, the clock frequency becomes higher and higher, and the clock frequency of the microcomputer becomes higher than that of A/IJ.
In many cases, it has become impossible to use one history as a 6 clock. Therefore, in order to operate the A/iJi generator, it is necessary to prepare another clock generator.On the other hand, an A/υ converter with a built-in clock generator has also been commercialized. However, this R-type A/IJ converter requires external parts such as a crystal molecule and a capacitor, which increases the cost of the entire system and at the same time makes it monolithic.
This results in an increase in the chip area of the U transformer. Furthermore, there is also the drawback that conversion accuracy is degraded due to noise generated by the clock generation circuit.

FIG. 1 is a block diagram of a conventional A/l) converter -l+11.

The conversion method of this A/IJ converter is a successive approximation type conversion method. In FIG. 1, an analog human input signal input to an analog input terminal 10 is supplied to a first input terminal of a comparator 8 via a multiplexer 9. On the other hand, the logic control circuit that operates in synchronization with the external clock input to the clock input terminal 1 starts with the successive approximation register 4.
Only IQt MH (most significant bit) is turned on. Spread this widely.

The digital-to-analog conversion circuit 7 supplies a signal corresponding to MOB to the @2 input terminal of the comparator 8. This
The analog input signal and M8B signal are compared by nl
If the analog input signal is larger than the M8B signal, the MSB of the successive approximation register 4 is kept on; if n1 is smaller, the MSB is set off. In this way, from MfMB to LMB of successive approximation register 4
(lower bits in 1j/) The comparison operation is performed sequentially in m,
As a result, the value set in the successive approximation register 4 is outputted to the outside as a digital conversion value of the analog input signal via the output register and the output buffer.

In this way, when the same clock as the clock used by the microcomputer 1e is input to the clock input terminal l, the clock is less than or equal to the eruption clock input frequency of the A/l) converter and n# i The A/υ converter is assembled normally. However, as recent microcomputers become faster, their clock frequencies have become higher, and clock frequencies of 4M) 1z or more are now commonly used. For this, A/D
The maximum input clock frequency of the converter is generally IMH, variant. Therefore, if the same clock as that used in high-speed microcomputer 1 is directly input to the A/L converter, there is a drawback that accurate conversion operation cannot be expected.

The present invention eliminates the above-mentioned drawbacks, and uses the same clock as that of a high-speed microcomputer, and without using any external parts, is a simple and highly reliable monolithic, analog-to-digital system. A converter is provided.

The monolithic analog-to-digital converter of the present invention is a monolink analog-to-digital converter that converts an analog input signal into a digital signal in synchronization with an externally input clock. The present invention is characterized in that it has a built-in clock frequency selection circuit that can frequency divide the clock n and select an arbitrary divided clock t.

@The lock frequency selection circuit is the first clock.

a frequency divider circuit that divides the frequency of a clock input from the input terminal and the core clock input terminal; a clock frequency divided by the frequency divider circuit and one of the input clocks;
A switch circuit that can be selected arbitrarily, a decode circuit that controls the switch circuit, and a circuit connected to the decode circuit that holds frequency selection data. .

Next, a 4m example of the present invention will be explained using the drawings.

FIG. 2 is a block diagram of a first practical example of the present invention.

In this embodiment, the present invention is applied to a successive approximation type A/l) converter, and the clock input terminal 1 and the logic circuit are connected to each other.

A clock frequency selection circuit 11 is provided between the control circuit 3 and the control circuit 3. The external clock input to the clock input terminal 1 is frequency-divided by the clock frequency selection circuit 11 and then supplied to the logic control circuit 3.

Hereinafter, a successive approximation sequence similar to that described in FIG. 1 is executed.

FIG. 3 is a block diagram of a second embodiment of the invention.

In this embodiment, the present invention is applied to a multilayer iA/D converter, and the clock frequency selection circuit 11 has a clock frequency selection circuit 11 having a clock input terminal and a logic input terminal, as in the first embodiment.

and the control circuit 3. The analog input signal is supplied to an integrating circuit 12 via a multiplexer 9, and is integrated over a certain period of time. Next, a reference voltage is applied to the integrating circuit 12, and the counter 13 counts the time from this moment until the output of the integrating circuit 12 crosses the threshold voltage of the comparator 8.

This counter 13 operates using an external clock whose frequency is divided by the clock frequency selection circuit 11. The count result of the counter 13 indicates the result of digital conversion of the analog input signal, and is outputted to the outside via the output register and output buffer 5.

In this way, the input terminal 1 and the logic control circuit 3
By providing a clock frequency selection circuit behind the scenes, the high frequency input clock is divided to a frequency below the maximum input clock frequency of the A/1) converter.

Therefore, accurate conversion operation is possible.

FIG. 4 is a circuit diagram of an example of a detailed circuit of the clock frequency selection circuit shown in FIGS. 2 and 3.

This clock frequency selection circuit includes a frequency divider @20 that divides the frequency of the clock signal inputted from the four input terminals l, a frequency division circuit @20 which divides the frequency of the clock signal inputted from the four input terminals l, and a frequency division circuit @20 that divides the frequency of the clock signal n, +clock signal and the input frequency signal 0.20. A switch circuit 301 that can arbitrarily select one clock! -Nuclear switch circuit 30
t-controlled decoding circuit #815 and the decoding circuit 15
The latch circuit 14 is connected to the latch circuit 14 and holds n% clock frequency selection data.

4 of the clock frequency selection circuit using FIGS. 4 and 5.
The operation of the clock frequency selection circuit will be explained using the diagram and FIG. The clock frequency selection data applied to the terminals 25 and 26 is latched into the latch circuit 14. According to this 2-bit data, the decoding circuit 15 turns on a predetermined switch among the switches 16-17*18 and 19.

On the other hand, the clock input to clock input terminal 1 is L)
By the frequency divider circuit 20 composed of n-type flip-flops,
The frequency is divided into 1/2, 1/4 and 1/8. Therefore, if the maximum input clock frequency of the A/l) converter is IMH2
If n, the maximum allowable frequency of the externally input clock is aM)i, and therefore, in a system that operates in the range from IMH2 to 8MH2, no external parts are added.

It becomes possible to directly input the clock to the A/L converter. Further, it is not necessary to provide independent terminals for each of the terminals 25 and 26 for inputting one frequency selection data, and it is possible to use these terminals also as other terminals.

That is, the clock frequency is constant throughout the operation of the system including the A/l)i converter, and therefore, the clock frequency is constant during the initialization for the peripheral devices performed by the microcomputer when the system starts up. It is possible to input clock frequency selection data through other terminals, for example data bus terminals. This data is then held in a latch circuit while the nuclear system is operating.

The above clock frequency selection circuit uses a three-stage frequency divider, but it is clear that if the number of stages is further increased, a higher frequency can be added manually to the A/IJ converter.

As described above, by applying the present invention, by widening the clock manual frequency range of the A/L converter 4, it is possible to directly input the same clock f to a microcomputer that operates on a high frequency clock. Therefore, A/L)
There is no need for a lower frequency black signal generator for the converter, and the entire system can be constructed economically.

Furthermore, even if the present invention is applied, no external parts are required, and the number of terminals of the A/L converter itself does not increase.

Furthermore, the frequency divider circuit, switch circuit, decode circuit, and latch circuit are also constructed from known logic circuits. - It does not require any special technology and has a great contribution to the industry.

Furthermore, since the A/L)-& converter according to the present invention does not include a built-in clock generating circuit, the conversion accuracy does not deteriorate due to noise generated by the clock generating circuit.

As described above in detail, the present invention provides an economical and highly reliable monolithic system that can be used with the same clock as that of a high-speed i-microcomputer without using any external parts.

The effect is great because an analog/digital converter can be obtained.

[Brief explanation of drawings]

Figure 1 shows an A/IJ that receives input from a conventional external source.
Block diagram of converter m-1, l! Figure 2 is the first example of the present invention.
FIG. 3 is a block diagram of a second embodiment of the present invention, I! Fig. 4 is a block diagram showing the complete circuit of the clock frequency selection circuit shown in Figs. 2 and 3, and Fig. 5 is a timing chart when operating the clock frequency selection circuit shown in Fig. 4. be. 1...Clock input terminal, 2...Control terminal, 3...Logic control circuit, 4...
... Successive approximation register, 5 ... Output register and output buffer, 6 ... Data bus terminal, 7 ... Digital fist analog conversion circuit, 8.
... Comparator, 9 ... Multiplexer, 10 ... Analog input terminal, 11 ...
...Clock frequency selection circuit, 12...Integrator circuit. 13...Counter, 14...U, child circuit, 15...Decode circuit s 16*17t
18*19°°...switch, 20...divider circuit, 21...1/2 division clock output terminal, 22...1/4 frequency division clock Output terminal, 23
...1/8 frequency divided clock output terminal. 24...Selected clock output 25 * 2
6...Clock frequency selection data input terminal, 3
0...Switch circuit. /A-2 Mulberry 3 Figure

Claims (2)

[Claims] (1) In a monolithic analog-to-digital converter 4 that converts an analog input signal into a digital signal in synchronization with an externally input clock. A monolithic device is characterized in that it has a built-in clock frequency selection circuit that divides the clock signal input from an external clock input terminal and selects an arbitrary divided clock number.
Analog to digital converter. (2) The clock frequency selection circuit includes a first clock input terminal, a frequency dividing circuit that divides the frequency of the clock signal input from the clock input terminal, and a clock frequency divided by the frequency dividing circuit. A switch circuit that can arbitrarily select any one of the input clocks, a decode circuit that controls the switch circuit, and a latch circuit that is connected to the decode circuit and holds a clock frequency selection data. A monolithic analog-to-digital converter according to claim 1, characterized in that the monolithic analog-to-digital converter comprises: n.