JPS60113532A - Ad converter - Google Patents

Abstract

PURPOSE:To avoid the noise from a logical operation circuit and to obtain an AD converter with high accuracy by staggering the timing of the sampling in a comparator of the AD converter from the operation timing of other logical operation circuits. CONSTITUTION:A system clock phi, which controls a logical operation circuit part, is given as a reference signal by dividing an output F0 of an oscillation circuit, and a clock phis', which controls a comparator of an AD converter which is in the same semiconductor chip with the logical operation circuit, is formed by using the system clock phi as a reference. The rising of the clock phis' can be made so that it will avoid the noise by setting the time lag from the rising of the system clock phi.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] Kibori 1 relates to an AD converter formed together with a logic circuit in the same semiconductor chip on which an MO8 integrated circuit is formed.

<Prior art> As the technology of conventional circuits using MOS transistors has progressed, the analog signal processing circuits that used to be conventionally made use of dipolar transistors have come to be constructed using MOS transistors. Analog mixed integrated circuits are now being put into practical use.7jo This type of integrated circuit receives an input signal, for example, by converting it into an analog signal, or by converting it into a signal suitable for the tickle circuit that makes up the logic circuit, and processing the input signal. An output signal corresponding to 1i is generated. In order to convert analog signals into digital signals as described above, an AD circuit is provided within the same semiconductor chip on which the MO5 integrated circuit is formed. Analog signals can usually contain any signal level from OV to voltage level, so if noise is added due to the influence of surrounding logic circuits, it may be recognized as a false signal. This not only deteriorates the accuracy of the AD controller but also causes the system to malfunction.

Figure 3 (a), (bl shows the time chart of the clocks φ, φ5, etc. that drive this type of integrated circuit, and the frequency of jf o is divided into the reference a from the oscillation circuit to form the above clocks φ, φ5. φ is a system clock that is a reference when making an integrated circuit, and various control signals are generated based on the system clock φ.It controls the comparator included in the AD converter. The clock φ5 is also formed from the system clock φ.Therefore, the clock φ5 obtained is an calendar number synchronized with the system clock φ as shown in the figure.

Processing D A converter output A Id, is formed under the control of a signal synchronized with the system clock φ, so its output is formed as a signal with noise at the rise and fall of the system clock φ, as shown in the figure. Ru. The output A of the DA converter affected by such noise
For K, if the above-mentioned clock φ5 is introduced to control the AD converter, 1) noise will be received at the end of sampling of the A converter output, that is, at the falling edge of the clock φ, and the voltage value will eventually have an error. will be sampled. In order to avoid such inconveniences, conventional integrated circuits take measures such as arranging the AD converter to prevent it from coming close to the logic circuit as much as possible, or using a separate power supply line for the AD converter. are doing. However, in integrated circuits that take the above-mentioned conventional improvement measures, pattern design work is time-consuming, and the chip size increases, which not only increases costs.
It was not possible to completely eliminate the influence of the logic circuit on the AD converter.

<Object of the Invention> The present invention eliminates the drawbacks of the conventional MO5 integrated circuit and the AD converter formed on the same chip, and provides a highly reliable AD converter that is not affected by the operation of the logic circuit. .

<Example> The integrated circuit according to this example is a microcomputer constructed of digital logic circuits and a semi-dedicated chip KA.
It is composed of D. Koshibark.

FIG. 1 (al is a time chart showing the clock φ・das for driving the integrated circuit based on the wood-based F!A[) and the DA converter output BQ. Similarly, the output fo of the oscillation circuit is frequency-divided and given as a reference signal.-The clock φ'5 that controls the comparator of the power AD converter is inverted in the form 1 based on the system clock φ. As shown in the figure, the rise of the clock φ'5 is set to have a time lag from the rise of the system clock φ.In other words, the AD converter comparison is performed by avoiding the transition point of the clock that controls the microcomputer part 1u. The rising and falling timings of the device clock φ'8 can be set.

A circuit for forming the clock φ'5 is shown in FIG. 1(b). The circuit consists of three Noritsu flops F, , F2 ., similar to the conventional circuit shown in FIG. 3(b). Although it is configured using F3, Noritubu Flotsub I? The clock terminal CPK of No. 3 is an AND gate G in the conventional circuit.

In contrast, in the signal generation circuit shown in FIG. Since the output φN is formed as a signal whose timing is shifted from the rising edge of the system clock φ, by controlling the knob F3 of the groove 70 using the output φN, the rising edge of the clock φ'8 is synchronized with the system clock. It can be shifted from the timing of φ.

As the comparator of the AD converter which operates when the above-mentioned clock 7'8 is applied, a chopper type comparator as shown in FIG. 2 is used, for example. The chopper comparator has a clock φ/
The output B of the DA converter, which serves as a reference signal for comparison, is sampled during the period when S is at the °'H'' level, and the input is received during the period when the clock φ'5 is tt L 1 level to compare the two. In the operating timing of such a comparator, by shifting the timing of both lock falsehoods, there is no noise at the end of sampling of the DA controller output, that is, immediately before the falling edge of chita lock φ'5. Signal levels can be sampled without error.

Figure 4 shows A operated by the clock signal of this embodiment.
The measurement results for D Converk are shown. That is, in the 16 stages of output digital values (00-FF), the output digital value P and the input voltage range Q are approximately within the range E of zero error shown in the figure.
It is possible to fit it into . On the other hand, for the same integrated circuit, when the clock φ is synchronized with the tally clock φ of the logic circuit as in the conventional case, the error deviates greatly from the range of error O, as shown in FIG. 5, and an error of about 8 LSH appears.

According to ``Effects'', the timing of sampling in the comparator of the AD converter is simply changed to that of other logic circuits, without giving any special consideration to the package design of the integrated circuit.
! By shifting the operation timing of Is, it is possible to avoid noise from the logic circuit and obtain an AD converter with high viscosity.

[Brief explanation of drawings]

FIG. 1 shows a clock signal of one embodiment according to the present invention.
Fig. 2 is a circuit diagram showing the main parts of the same embodiment, Fig. 3 is a time chart showing the clock signal used in the conventional device, and Fig. 4 shows the measurement results of the circuit after performing Misfire 1. The figure shown in FIG. 5 is a diagram showing measurement results of a conventional circuit.

Claims (1)

[Claims] ]) AD converter (same as the cycle logic circuit) In an MO3 integrated circuit formed in a semi-rod chip, the clock that controls the logic circuit is used as a clock that performs darcipling control of input disturbances for AD conversion. An A'D Konno-Goku featuring a clock that is powered by out-of-phase clocks.