JPH0572359A - Clock circuit - Google Patents

Abstract

PURPOSE:To obtain a resolving power to match accuracy demanded by a method wherein an exclusive OR gate is arranged to input a brake control signal which sets or resets an uppermost frequency division stage of a logical braking circuit and at least one other brake control signal and an output thereof are inputted into a setting or resetting terminal of a frequency division circuit. CONSTITUTION:A reference signal 1 is inputted into an advance correction block 2 made up of a frequency division circuit comprising a memory circuit with a setting and an output thereof is inputted into a delay correction circuit 3 at the uppermost stage. Furthermore, a 1-sec. signal 8 is outputted from the frequency divider circuit 7. With a value of a brake control input L4' as input of an exclusive OR gate 10 together with a value of an input L5, an output L4 thereof is inputted into a brake controlling block 4. A brake control signal is inputted into setting terminals of the frequency divider circuits of the circuit 2 and a resetting terminal of the frequency divider circuit of the circuit 3 from the block 4 at a fixed time interval by a braking operation control signal 5. Thus, an output of the circuit 3 is corrected to delay or advance to make a 1-sec. signal corrected via a circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the mechanism of a logic regulation circuit of a timing circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional logic regulation circuit of a clock circuit.

The reference signal 1 is input to the advance correction circuit block 2 which is composed of a 1/2 frequency dividing circuit including a storage circuit with a set, and is logically regulated based on a 1/2 frequency dividing circuit including a memory circuit with a reset. The frequency-divided signal of the lead correction block is input to the input of the delay correction circuit 3 at the highest stage of
The frequency-divided output output from the delay correction circuit 3 is further output from the frequency-division circuit block 7 as a 1-second signal 8. The value of the slow / fast control input 6 set from the outside is input to the slow / fast control input selection block 4, and the 1-second signal 8 is input.
Is input to the slow-and-quick operation control signal 5 generated by the slow-and-quick operation control signal generation circuit 9, and the slow-and-quick control signal advances from the slow-and-quick control input selection block 4 at fixed time intervals. 3 is input to the reset terminal of the frequency divider circuit. By inputting the slow / fast control signal to the set terminal of the advance correction circuit 2 and the reset terminal of the delay correction circuit 3 at a constant time interval, the frequency division signal output from the correction circuit 3 is corrected for delay or advance, and The signal is output as a corrected one-second signal 8 from the frequency dividing circuit 7 of. When the slow / fast control signal input to the set terminal of the advance correction circuit 2 is "0", the output of the memory circuit continues frequency division output, but when the slow / fast control signal is "1", the output of the memory circuit is "". It is set to the 1 "state, the lead correction for one input signal of each frequency division stage is performed, and the result is input to the delay correction circuit 3. When the slow / fast control signal input to the reset terminal of the delay correction circuit 3 is "0", the output of the memory circuit divides the signal input from the fast correction circuit 2 by 1/2 and outputs it. Is "1", the output of the memory circuit is reset to "0" to perform delay correction for one input signal of the delay correction circuit and input to the next frequency dividing circuit 7 to advance at regular time intervals or A delay-corrected 1-second signal 8 is obtained. The configuration is such that the advance or delay is corrected at regular time intervals by the individually set slow / fast control input.

Table 1 below shows combinations of slow and fast control inputs.

[0005]

[Table 1]

[0006]

However, in the logical regulation circuit of the prior art, even when the lead / lag correction is performed with high accuracy as shown in Table 1, when the accuracy of the reference signal source is high or the output is 1 Even when performing lead / lag correction with low accuracy when high accuracy is not required for second signal output,
Since the number of logic inputs to be set to the slow / fast control input terminals does not change, it has been difficult to achieve the efficiency of slow / fast control input setting with a reduced number of setting terminals with low accuracy.

Therefore, according to the present invention, when the lead / lag correction required for the output signal of 1 second has a high precision, the number of slow / fast control inputs (that is, resolution) commensurate with the high precision is provided, and when it is low, it is low. It is possible to select the number of slow / fast control inputs commensurate with the accuracy, and at the same time, it is possible to maintain the logic combination of the slow / fast operation at each resolution.

[0008]

According to the clock circuit of the present invention, a signal from a reference signal source is connected to an input of a serially connected divider circuit of a 1/2 divider circuit composed of a storage circuit with set or reset. A set or reset input of the 1/2 frequency divider circuit is provided with a logic slow / fast circuit which is set or reset by a slow / fast control input terminal corresponding to each frequency dividing stage at a constant time interval. Of at least one slow-and-quick control signal other than the slow-and-quick control signal for setting or resetting the highest frequency-dividing stage as the input of the exclusive OR gate, The output of the OR gate is input to the set or reset terminal of the frequency divider circuit corresponding to the slow / fast control signal used for the input of the exclusive OR gate. To.

[0009]

According to the above configuration of the present invention, at least a slow-and-fast control signal for setting or resetting the highest frequency division stage of the logic slow-and-fast circuit and at least a slow-and-quiet control signal for setting or resetting the highest frequency division stage. One slow / fast control signal is used as an input of the exclusive OR gate, and the output of the exclusive OR gate is used to set the frequency divider circuit corresponding to the slow / fast control signal used as the input of the exclusive OR gate. Logic input / output is performed by inputting it to the reset terminal.

Therefore, according to the present invention, a slow-and-fast control input signal for setting or resetting the highest frequency division stage and at least one slow-and-quick control signal other than the slow-and-quick control signal for setting or resetting the highest frequency division stage. The slow-and-fast control signal can be synthesized by performing an exclusive OR processing of

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a timing circuit according to an embodiment of the present invention.
It is a block diagram of a bit logic regulation circuit. The reference signal 1 is input to the advance correction circuit block 2 which is composed of a 1/2 frequency dividing circuit including a storage circuit with a set, and the highest level of logical regulation which is composed of a 1/2 frequency dividing circuit including a memory circuit with reset. The frequency division signal of the lead correction block is input to the input of the delay correction circuit 3 of the stage, and the frequency division output output from the delay correction circuit 3 is further output from the frequency division circuit block 7 as a 1-second signal 8. Output is done. The value of the slow / fast control input 6 which is set from the outside is directly input to the slow / fast control input selection block 4, and the value of L4 ′ is the value of L5 and the exclusive OR gate 10. Input becomes L
4 is input to the slow-and-quick control block 4, and the slow-and-quick operation control signal 5 generated by the slow-and-quick operation control signal generating circuit 9 with the 1-second signal 8 as an input is fed from the slow-and-quick control input selection block 4 at a constant time interval Correction circuit 2
Is input to the set terminal of each frequency divider circuit and the reset terminal of the frequency divider circuit of the delay correction circuit 3. By inputting the slow / fast control signal to the set terminal of the advance correction circuit 2 and the reset terminal of the delay correction circuit 3 at a constant time interval, the frequency division signal output from the correction circuit 3 is corrected for delay or advance, and The signal is output as a corrected one-second signal 8 from the frequency dividing circuit 7 of. When the slow / fast control signal input to the set terminal of the advance correction circuit 2 is "0", the output of the memory circuit continues frequency division output, but when the slow / fast control signal is "1", the output of the memory circuit is "". It is set to the 1 "state, the lead correction for one input signal of each frequency division stage is performed, and the result is input to the delay correction circuit 3. When the slow / fast control signal input to the reset terminal of the delay correction circuit 3 is "0", the output of the storage circuit divides the signal input from the advance correction circuit 2 by 1/2 and outputs it.
When the slow / fast control signal is "1", the output of the memory circuit is "0"
Then, the delay correction circuit corrects the delay of one input signal, and the signal is input to the next frequency dividing circuit 7 to obtain a 1-second signal 8 which is advanced or delayed at regular time intervals.
Table 2 is a list of combinations of the logical slow / fast control inputs for the lead / lag correction of the block diagram of FIG. 1, and the value of L4 which is the value of the exclusive OR of the slow / fast control input L4 ′ and the highest L5 of the slow / fast control inputs. In the case of the logical slow / fast operation with high resolution by the combination of 32 (the slow / fast control is -16 to 15), the operation is realized by changing the value of L4 'to "1" or "0". , 16 (slow / fast control is -8 to 7) in the low-resolution logical slow / fast operation, the value of L4 'is fixed to "0".

[0012]

[Table 2]

In the above embodiment, in addition to the configuration in which the operation result of the exclusive OR of L4 'and L5 is L4, it is also possible to perform a logical operation with L3 or L2, L1 to convert it into a delay advance control input. FIG. 3 shows a block diagram of a configuration in which the calculation result of the exclusive OR of L3 ′ and L5 is L3, which is possible, and the combination of logical regulation in that case is shown in Table 3 below.

[0014]

[Table 3]

In the block diagram of FIG. 3, when the exclusive OR of L4 'and L5 is calculated to be L4, and the exclusive OR of L3' and L5 is calculated to be used as L3 for the speed control input, Table 3 As shown in the logical slow / fast combination, in the logical slow / quick operation in which the low resolution in the combination of 8 (the slow / quick control is -4 to 3) is applied, the values of L4 'and L3' may be fixed to "0" to operate. it can.

Further, in the above-mentioned embodiments, the implementation of the present invention in the 5-bit logical slowing / fastening circuit is mentioned. However, the exclusive OR operation with the uppermost slowing / fastening control input does not depend on the configuration of the input bit. It is also possible to perform the same operation by a logical operation for each of the slow and fast control inputs.

The same mechanism can be applied to the slow / fast control signal input of the frequency divider circuit of the logic slow / fast circuit used in the above-described configuration, regardless of whether it is positive logic or negative logic. Even when the input condition of the memory circuit section of the correction circuit to be input is set or reset, the same operation can be performed.

[0018]

As described above, according to the present invention, the highest frequency division stage (hereinafter referred to as M
SB) is set or reset (hereinafter referred to as MSB signal), and at least one slow control signal other than the MSB signal (hereinafter referred to as MSB-n).
Is used as an input of an exclusive OR (hereinafter referred to as EXO) gate, and the output of the EXO gate is input to the set or reset terminal of the frequency divider circuit of MSB-n.
When the slow-and-fast control input terminal MSB-n that has performed the exclusive OR operation with the value of SB is deviated from the MSB terminal by n stages, the resolution that MSB-n performs the slow-and-fast control is the resolution that the MSB performs the slow-and-fast control. On the other hand, since it is reduced by 2 to the n-th power, the value of MSB-n is fixed to control the logical slowing / fastening operation regardless of whether the combination of slowing / fastening operations with the resolution of MSB-n is delayed or advanced. In addition, if high resolution is required for the output of the timekeeping circuit, detailed settings make it possible to set independent control inputs for all of the input terminals, and the accuracy of the reference signal source is high. Even if the precision control is not required, or if the timing circuit itself does not require high precision, even if the high-precision slow-motion control is not required, the slow-speed control according to the required precision is required. Control By setting only the input terminal,
Similar to the combination of the slow and fast control in the case of the high resolution, it has the effect of performing the slow and fast operation of the delay advance corresponding to the low resolution.

[Brief description of drawings]

FIG. 1 is a block diagram of a logic regulation circuit having a 5-bit resolution of a timing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a logical regulation circuit having a 5-bit resolution of a conventional clock circuit.

FIG. 3 is a timing circuit 5bi in which one input portion of the exclusive OR operation of the slow input / output portion of the present invention is changed from L4 ′ to L3 ′.
FIG. 6 is a block diagram of a logical regulation circuit having t resolution.

[Explanation of symbols]

1 −−−−− Reference signal 2 −−−−−− Lead correction circuit (including 1/2 frequency dividing stage) 3 −−−−− Delay correction circuit (including 1/2 frequency dividing stage) 4 −−− −− Slow-and-fast control input selection block 5 −−−−− Slow-and-fast operation control signal 6 −−−−− Slow-and-fast control input 7 −−−−− Dividing circuit 8 −−−−− 1 second output signal 9 −−−− − Slow and fast operation control signal generation circuit 10 −−−−− Slow / fast control input exclusive OR operation unit

Claims (1)

[Claims] 1. An electronic circuit (hereinafter referred to as a timing circuit) for dividing a signal from a reference signal source to generate one second and timing the one second, wherein the signal from the reference signal source is set or reset. It is connected to the input of the frequency divider circuit connected in series with the 1/2 frequency divider circuit, and the set or reset input of the 1/2 frequency divider circuit corresponds to each frequency division stage at regular time intervals. An electronic circuit (hereinafter referred to as a logic slow / fast circuit) that is set or reset by a slow / fast control input terminal is provided, and a slow / fast control signal that sets or resets the highest frequency division stage of the logic slow / quick circuit, and the highest frequency division. At least one slow / fast control signal other than the slow / fast control signal that sets or resets the stage is used as an input of the exclusive OR gate, and the output of the exclusive OR gate is input to the exclusive OR gate. Counting circuit and wherein the input to the set or reset terminal of the regulation control signals corresponding frequency divider used.