JPH10135821A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the clock generating circuit with less jitter and suitable for circuit integration by switching a frequency division ratio of integers before and after a non-integer at a prescribed switching ratio so as to realize frequency division of the noninteger. SOLUTION: This circuit is made up of a frequency divider circuit 3 that frequency-divides a reference clock signal REF at two frequency division ratios set by a frequency division ratio setting signal COPR to generate an output clock CKO, a frequency division ratio setting circuit 1 that generates a frequency division ratio setting signal denoting a frequency division ratio A and a frequency division ratio (A+1) when a frequency ratio of a basic clock signal REF and the clock signal CKO is A (integer) + b (a number below the decimal point), a frequency division ratio selector 2 that selects either of the two frequency division ratio setting signals based on a selection signal CAR 1 to provide an output of the frequency division ratio setting signal COPR, and a control section 4 that generates the selection signal CAR 1 by using a ratio of frequency division clock numbers of the frequency division ratios A, A+1 as a switching ratio for a period of a greatest common multiple of frequencies of the signals REF and CKO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for obtaining a clock having a frequency whose division ratio is not an integer from a reference clock by digital processing.

[0002]

2. Description of the Related Art Conventionally, this kind of clock generation circuit is constituted by a digital circuit without using VC0 for the purpose of integration. FIG. 5 is a block diagram of a conventional example of this type described in Japanese Patent Application Laid-Open No. 4-207524.

In FIG. 4, an output clock signal CKT is
The reference clock CKST output from the reference clock generation circuit 21 is obtained by extracting a predetermined number of pulses by the switch circuit 22. The switch circuit 22 determines whether the reference clock signal CKST is conductive or non-conductive by the counter circuit 23.
Is controlled by a control signal GS.

[0004] The counter circuit 23 has a preset counter. The counter circuit 23 receives the reference clock signal CKST as a count clock, and also receives the frequency-divided clock signal CKST output from the frequency divider circuit 24 as a preset timing signal. The frequency dividing circuit 24 divides the frequency of the clock signal CKT by a predetermined frequency dividing ratio 1 / N. The preset value of the counter circuit 23 is set by preset data PSD from a preset data output circuit (microprocessor or the like) 25.

Therefore, the counter circuit 23 presets when the frequency-divided clock signal CKN is input, and outputs a control signal GS for turning off the reference clock signal CKST to the switch circuit 22. Continue until a predetermined value is reached. Thereafter, the control signal GS for turning on the reference clock signal CKST to the switch circuit 22 until it is reset again.
Is output. The frequency division ratio 1 / N of the frequency dividing circuit 24 is a value corresponding to the frequency of data processed using the clock signal CKT.

[0006]

As described above, in the conventional example, the output clock signal obtained is a clock of an intermittent pulse train because a predetermined number of pulses are periodically extracted from the continuous pulse train. Therefore, there is a problem that the jitter becomes large when compared with the clock of the continuous pulse train. In particular, there is a problem that the jitter further increases as the number of extracted pulses increases.

[0007]

According to the present invention, there is provided a clock generation circuit which divides a reference clock signal by a division ratio set by a division ratio setting signal to generate an output clock signal; When the frequency ratio between the clock signal and the output clock signal, that is, the frequency division ratio is A (integer) + a (numerals after the decimal point), the frequency division ratio setting signal A and the frequency division ratio A + 1 are set. A frequency division ratio setting circuit for generating a frequency division ratio setting signal A + 1, and the frequency division ratio setting signal A and the frequency division ratio setting signal A + 1 are inputted, and one of them is selected by a selection signal to select the frequency division ratio setting signal. And a control unit that calculates a predetermined switching ratio from the frequency conditions of the reference clock signal and the output clock signal and outputs the selection signal.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating the principle of the embodiment of the present invention.

In FIG. 1, the block generation circuit divides a reference clock signal REF by a frequency division ratio set by a frequency division ratio setting signal C0PR to generate an output clock signal CK0; A division ratio setting signal C0PR1 for setting the division ratio A when the frequency ratio between the clock signal REF and the output clock signal CK0 is A (integer) + a (numerals after the decimal point) and a division ratio for setting the division ratio A + 1 A frequency division ratio setting circuit 1 for generating a setting signal C0PR2, a frequency division ratio setting signal C0PR1 and a frequency division ratio setting signal C0PR2 are input, and one of them is selected by a selection signal CAR1 to output a frequency division ratio setting signal C0PR. A predetermined switching ratio is calculated from the frequency division ratio selector 2 and the frequency conditions of the reference clock signal REF and the output clock signal CK0 to select the selection signal CAR.
1 is constituted by a control unit 4 for outputting the value "1".

The control unit 4 controls the number of output clocks and the dividing ratio A + 1 when the dividing circuit divides by the dividing ratio A during the period of the greatest common divisor of the frequency of the reference clock signal REF and the output clock signal CK0. When the ratio to the number of output clocks when the frequency is divided by B is (integer) + b (number after the decimal point), frequency dividing ratio setting signals C1PR1 and C1PR2 for setting the frequency dividing ratios B and B + 1, respectively; Next, in order to divide the output clock signal CK0 by the ratio of B + b, the ratio of the number of output clocks when dividing by the dividing ratio B to the number of output clocks when dividing by the dividing ratio B + 1 is C (integer). ) + C (number after the decimal point), the division ratio setting signals C2PR1 and C2P for setting the division ratio C and the division ratio C + 1, respectively.
R2, and N sets of frequency division ratio setting signals C1PR similarly calculated and set until the ratio of the number of output clocks becomes an integer.
To CNPR and the frequency division ratio setting signal CN when it becomes an integer
A division ratio setting circuit 41 for generating + 1PR2, and division ratio selectors 421 to 42N for inputting each division ratio setting signal and selecting and outputting one of the division ratio setting signals by a corresponding selection signal CAR. And the output clock signal CK0
Is divided by the division ratio set by the output signal C1PR of the division ratio selector 421 to output the selection signal CAR1 and the divided clock signal CK1, and the divided clock signal CK1 is divided by the division ratio selector 422. The output signal C2PR is divided by the division ratio and the selection signal CA to the division ratio selector 421
A frequency dividing circuit 432 for outputting R2 and a frequency-divided clock signal CK2, and similarly dividing the output clock signal of the front frequency dividing circuit by the frequency dividing ratio of the output signal of the corresponding frequency dividing selector, and Frequency dividing circuits 431 to 43N for outputting a selection signal to the frequency ratio selector and a frequency divided clock signal, and the frequency divided clock signal CKN of the frequency dividing circuit 43N are divided into frequency division ratio setting signals C
A frequency dividing circuit 43N + 1 that divides the frequency by the frequency dividing ratio of N + 1PR and outputs a selection signal CARN + 1 to the frequency dividing ratio selector 42N.

The frequency division ratio setting circuit 41 inputs the frequency conditions of the reference clock signal REF and the output clock signal CK0, automatically calculates each frequency division ratio, and generates the frequency division ratio setting signal C1.
C including the required program that outputs PR to CN + 1PR
A PU may be used.

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram showing the configuration, and FIG. 3 is a time chart for explaining the operation of FIG. FIG.
Shows a configuration when N = 4 in FIG. The specific operation principle and configuration in FIG. 2 will be described below.

Here, the reference clock signal REF is set to 1
7.73475 MHz, output clock signal CK0 is 7
68 kHz, that is, 16 times the audio sampling clock from the frequency four times the PAL subcarrier frequency
This is an example of generating a double frequency. Reference clock signal RE
The greatest common divisor of F and the output clock CK0 is 25 (HZ), and the reference clock signal REF is set to a period of 1/25 = 40 (ms) (that is, a period when the pulses of both pulse trains are arranged at the same position). 177344475/25 = 709
379 clocks, output clock signal CK0 is 76800
0/25 = 30720 clocks will be present. Further, the reference clock signal REF and the output clock signal CK0
Is 173744475/768000 = 23.
091..., And the frequency dividing circuit 3 divides the frequency by 23 or 24.

The frequency dividing circuit 3 is composed of a frequency dividing counter 31 and an address decoder 32.
t is a presettable counter. In this case, the frequency division ratio of the counter is changed by changing the preset value. Set the value to “8”. Therefore, the dividing ratio setting circuit 1 is provided with a dividing ratio selector 2
, The values of “8” and “9” are output, and these selector outputs C0PR are preset input to the frequency division counter 31 and are frequency-divided by 23 or 24. The address output C0ADR of the frequency division counter 31 is
Is output as the output clock signal CK0 whose duty has been adjusted.

Next, the control section 4 for supplying the carry output CARI for controlling the selection of the frequency division ratio selector 2 will be described. 40ms cycle 23 divided output clock CK0 is X _a number in the period, the output clock is peripheral 24 minutes CK0
If there are X _{a + 1} , the following simultaneous quadratic equations hold.

709379 = 23 × X _a + 24 × X _{a + 1} 30720 = X _a + X _{a + 1} X _a = 27901, X _{a + 1} = 2819, and X _a
And the ratio of X _{a + 1} are 27901/2819 = 9, 897 ...
In order to perform the frequency division of this ratio, the frequency dividing circuit 431 switches the frequency division of the frequency dividing ratio of 9 or 10. Since the frequency division counter 441 is a 4-bit presettable counter, in the case of frequency division by 9, the preset value is “6”, 10
In the case of frequency division, the preset value is set to “5”. Therefore, the frequency division ratio setting circuit 41 outputs values “5” and “6” to the frequency division ratio selector 421, and these selector outputs C
1PR is preset input to the frequency division counter 441, and C
The frequency is divided by 9 or 10 using K0 as an input clock. The address output C1ADR of the frequency division counter 441 is decoded by the address decoder 451 and outputs a frequency-divided one clock CK1. Further, select control of the frequency division ratio selector 2 is performed by the carry output CAR1 of the frequency division counter 441.

Next, the divided clock CK1 divided by 9 in the period of 40 ms is _Xb , and the CK1 divided by 10 is X
If there are _{b + 1} , the following simultaneous quadratic equations hold.

X _a = 27901 = 9 × X _b + 10 × X _{b + 1} X _{a + 1} = 2819 = X _b + X _{b + 1} X _b = 289, X _{b + 1} = 2530, and X _{b + 1} and X _b
Is 2530/289 = 8.754..., And the frequency dividing circuit 432 divides the frequency by the dividing ratio 8 or 9.
The frequency division counter 442 receives the selector output C2PR as a preset input and frequency-divides the frequency-divided clock signal CK1 by eight or nine. Further, select control of the frequency division ratio selector 441 is performed by the carry output CAR2.

Next, the divided clock CK2 is X _c number which is divided by 8 to 40ms cycle duration, if the ninth frequency division has been divided clock CK2 is set to X _{c + 1} pieces exist, following simultaneous quadratic equations Holds.

X _{b + 1} = 2530 = 8 × X _c + 9 × X _{c + 1} X _b = 289 = X _c + X _{c + 1} X _c = 71, X _{c + 1} = 218, and X _{c + 1} and X _c The ratio of _c is 218/71 = 3.070...
Then, frequency division by 3 or 4 is performed. Dividing counter 44
Reference numeral 3 designates a preset output of the select output C3PR, and is divided by 3 or 4 by using the output clock CK2 as an input clock. Address output C of frequency dividing counter 443
The 3ADR is decoded by the address decoder 453, and outputs a frequency-divided clock CK3. Also, carry output CA
The selector control of the frequency division ratio selector 422 is performed by R3.

Next, _Xd frequency-divided clocks CK3 divided by 3 during a period of 40 ms, and frequency-divided clocks C divided by 4
If there are X _{d + 1} K3s, the following simultaneous quadratic equations hold.

X _{c + 1} = 218 = 3 × X _d + 4 × X _{d + 1} X _c = 71 = X _d + X _{d + 1} X _d = 66, X _{d + 1} = 5, and X _d and X _{d + 1st} day is 6
6/5 = 13.2, and the frequency dividing circuit 434 performs frequency division of 13 or 14. The division counter 444 receives the preset output of the select output C4PR and outputs the divided clock C
The frequency is divided by 13 or 14 using K3 as an input clock. Address output C4AD of frequency division counter 444
R is decoded by the address decoder 454 and outputs a frequency-divided clock CK4. Further, selection and control of the frequency division ratio selector 423 are performed by the carry output CAR.

[0023] Next 40ms period duration in 14 divided-divided clock CK4 is X _e number were, if 14 divided-by dividing clock CK4 is the X _{e + 1} or present, simultaneous quadratic equations below is established .

_Xd = 66 = 13 × _Xe + 14 × _{Xe + 1 Xd + 1} = 5 = _Xe + _{Xe + 1 Xe} = 4, _{Xe + 1} = 1, and _Xe and _{Xe +} The ratio of ₁ is 4 /
1 = 4, and the frequency dividing circuit 435 performs only frequency division by 4. The frequency division counter 445 has the select output C
5PR is directly preset input, and the frequency dividing counter 445 divides the frequency by 4 using the frequency divided clock CK4 as an input clock.
Further, select control of the frequency division ratio selector 424 is performed by the carry output CAR5 of the frequency division counter 445.

Next, the operation will be supplementarily described with reference to FIGS. The reference clock input signal REF is divided by 23 or 24 to generate an output clock signal CK0. At this time, the division ratio is switched by the division counter 441.
Is controlled by the carry output CAR1. That is, CA
When R1 is "L", the selector output C of the frequency division ratio selector 2
When 0PR becomes "8", the frequency is divided by 24 by the frequency dividing counter 31, and when CAR1 is "H", the selector output C0PR is output.
Becomes "9" and is divided by 23. Similarly, the output clock signal CK0 is frequency-divided by 9 or 10 by the frequency division counter 441, and the frequency-divided clock signal CK1 of the frequency division circuit 431 is generated. At this time, the switching of the dividing ratio is controlled by the carry output CAR2 of the dividing counter 442. That is, when CAR2 is "L", the selector output C1PR of the frequency division ratio selector 421 becomes "5", the frequency is divided by 10, and
When AR2 is "H", the selector output C1PR becomes "6", and the frequency is divided by nine.

Similarly, the frequency-divided clock signal CK1 of the frequency-divider circuit 431 is frequency-divided by 8 or 9 to generate the frequency-divided clock signal CK2 of the frequency-divider circuit 432. At this time, the division ratio is switched by the carry output CAR of the division counter 443.
3 is controlled. That is, when CAR3 is “L”,
The selector output C2PR of the frequency division ratio selector 422 is "6"
The frequency is divided by 9, and when CAR3 is at "H", the selector output C2PR becomes "7" and the frequency is divided by 8.

Similarly, the frequency-divided clock signal CK 2 of the frequency divider 432 is frequency-divided by three or four to generate a frequency-divided clock signal CK 3 of the frequency divider 433. At this time, the division ratio is switched by the carry output CA of the division counter 444.
Controlled by R4. That is, when CAR4 is "L", the selector output C3PR of the frequency division ratio selector 423 becomes "4" and is divided by three. When CAR4 is "H", the selector output C3PR becomes "3" and becomes four times. Be circulated.

Similarly, the frequency-divided clock signal CK 3 of the frequency dividing circuit 433 is frequency-divided by 13 or 14, and the frequency dividing circuit 434
CK4 is generated. At this time, the switching of the division ratio is controlled by the carry output CAR5 of the division ratio counter 425. That is, CAR5 is “L”
, The selector output C4PR of the frequency division ratio selector becomes “2”, the frequency is divided by 13, and the CAR5 becomes “H”.
In this case, the selector output C4PR becomes "1" and the frequency is divided by 14. The frequency-divided clock signal CK4 of the frequency divider 434 is 4
Only frequency division is performed.

[0029]

As described above, the clock generation circuit of the present invention is realized by switching the frequency of a non-integer frequency dividing ratio by switching two consecutive frequency dividing ratios at a predetermined ratio. Therefore, there is an effect that the jitter of the output clock signal can be suppressed within one clock of the input reference clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific embodiment of FIG.

FIG. 3 is a tie chart showing the operation of FIG. 2;

FIG. 4 is a tie chart following FIG. 3 showing the operation of FIG. 2;

FIG. 5 is a block diagram showing a configuration of a conventional clock generation circuit.

[Explanation of symbols]

 1 division ratio setting circuit 2 division ratio selector 3 division circuit 4 control unit 41 division ratio setting circuit 421 to 42N division ratio selector 431 to 43N, 43N + 1 division circuit 441 to 445 division counter 451 to 454 address counter

Claims (3)

[Claims] A frequency dividing circuit that divides a reference clock signal by a frequency dividing ratio set by a frequency dividing ratio setting signal to generate an output clock signal; and a frequency ratio between the reference clock signal and the output clock signal. When the frequency division ratio is A (integer) + a (numerals after the decimal point), frequency division for generating a frequency division ratio setting signal A for setting the frequency division ratio A and a frequency division ratio setting signal A + 1 for setting the frequency division ratio A + 1 A ratio setting circuit, a frequency division ratio selector that receives the frequency division ratio setting signal A and the frequency division ratio setting signal A + 1, selects one of the signals by a selection signal, and outputs the selected signal as the frequency division ratio setting signal, A clock generation circuit comprising: a control unit that calculates a predetermined switching ratio from each frequency condition of a signal and the output clock signal and outputs the selection signal. 2. The control unit according to claim 2, wherein the number of output clocks when the frequency divider divides the frequency by the frequency division ratio A in a period of the greatest common divisor of the frequencies of the reference clock signal and the output clock signal. The ratio to the number of output clocks when dividing by the dividing ratio A + 1 is B (integer) + b (number after decimal point)
The first division ratio setting signal for setting the division ratios B and B + 1, respectively, and the output clock signal obtained by dividing the reference clock signal by the division ratio A + a are then divided by the ratio of B + b. The ratio of the number of output clocks when dividing by the dividing ratio B to the number of output clocks when dividing by the dividing ratio B + 1 is C (integer) + c (the number after the decimal point). A second frequency division setting signal for setting the frequency division ratio C and the frequency division ratio C + 1, respectively, and a first frequency division clock obtained by dividing the output clock signal by the frequency division ratio B + b. Similarly, the signals are calculated in the same manner, and the first to N-th N sets of frequency division ratio setting signals calculated and set until the ratio of the number of output clocks becomes an integer and the (N + 1) th division ratio when the integer is reached. Division ratio setting circuit for generating the division ratio setting signal A first to an N-th division ratio selector, which receives the first to N-th division ratio setting signals, selects and outputs one of the division ratio setting signals by a corresponding selection signal, and A first frequency dividing circuit for dividing a clock signal by a frequency dividing ratio of an output signal of the first frequency dividing selector and outputting the selection signal and the first frequency divided clock signal; and the first frequency dividing circuit A second frequency divider for dividing a clock signal by a frequency division ratio of an output signal of the second frequency division ratio selector and outputting a selection signal to the first frequency division ratio selector and a second frequency divided clock signal Similarly to the circuit, the output clock signal of the front frequency dividing circuit is frequency-divided by the frequency division ratio of the output signal of the corresponding frequency dividing ratio selector, and the selection signal to the front frequency dividing ratio selector and the frequency-divided clock signal are output. To N-th divider circuit and divided clock signal of N-th divider circuit 2. The (N + 1) th frequency divider circuit for dividing the frequency by the frequency division ratio of the (N + 1) th frequency division ratio setting signal and outputting a selection signal to the Nth frequency division ratio selector. Clock generation circuit. 3. A required program for inputting frequency conditions of the reference clock signal and the output clock signal, automatically calculating the frequency conditions of the reference clock signal and the output clock signal, and outputting the first to N + 1 frequency division ratio setting signals. The clock generation circuit according to claim 3, further comprising a CPU.