JPH09307411A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock single generation circuit of high procession which can produce an optional phase-shifter clock signal against a reference clock signal and also has high follow-up performance to the reference clock signal. SOLUTION: The delay signals S1 , S2 ...Sk-2 and Sk-1 which are switched to the logical high levels from trailing edges of the 1st, 2nd...(k-1)-th clock signals by the delay circuits W1 , W2 ...Wk-2 and Wk-1 are produced against a clock signal dlo which is obtained by supplying the (L×M) multiplication (L, M = integers) to a reference clock signal. The ANDs are generated between the delay singles and the signal dlo by AND gates AGT1 , AGT2 ...AGTk-2 and AGTk-1 , undergo the M-multiplication by a programmable division circuit 41 and are selectively outputted by a selection circuit 42. As a result, a phase shift can be optionally set to the signal dlo and therefore a highly precise clock signal having high follow-up performance can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit capable of arbitrarily setting a phase shift of a clock signal.

[0002]

2. Description of the Related Art For a certain reference clock signal, πN /
Often, two clock signals that are out of phase are generated. Here, N = 1, 2, and 3. Generally, π /
A method is used in which a delay of two phases is generated by a delay circuit, and a clock signal having a phase shift of πN / 2 is generated by combining the delay circuits.

FIG. 5 is a waveform diagram showing an example of a case where a clock signal having a phase shift of π / 2, π and 3π / 2 with respect to the reference clock signal is generated in this way. As shown in FIG. 5, with respect to the reference clock signal (Sref), π
A clock circuit with a phase shift of π / 2 is generated by a delay circuit that generates a delay of time T _D corresponding to a phase shift of / 2. Then, by connecting two or three delay circuits that generate the same delay time T _D in series, π, 3π / 2
The clock signals with the phase shift of 1 are generated respectively.

[0004]

By the way, the accuracy of the above-described conventional method of generating a clock signal with a phase shift is limited. For example, the accuracy of the generated phase-shifted clock signal is determined by the accuracy of the delay circuit, and the accuracy is further reduced by using many delay circuits. In addition, the delay circuit generation method has a poor trackability with respect to the frequency change of the reference clock signal. If an attempt improve the capability, only PLL for generating the delay time T _D (Pha
se Locked Loop) circuit, etc.
ineffective. Further, the method of generating the delay time T _D has a problem that only the phase-shifted clock signal in a fixed range can be generated.

The present invention has been made in view of the above circumstances, and an object thereof is to generate a highly accurate phase-shifted clock signal with respect to a reference clock signal and to follow the fluctuation of the frequency of the reference clock signal. It is an object of the present invention to provide a clock generation circuit that is good and can set the phase shift arbitrarily.

[0006]

In order to achieve the above object, the present invention relates to a phase comparison circuit for comparing the phases of an input signal and a reference clock signal and outputting a control signal according to the comparison result, and the above control. A frequency multiplication circuit that receives a signal and outputs a frequency-multiplied signal that is frequency-multiplied by a frequency-multiplied number defined by a real number M;
Output the divided signal to the above phase comparison circuit, and
A signal generation circuit for generating at least one delay signal by delaying the multiplied signal with a preset delay time, and generating a signal obtained by dividing the delay signal with an arbitrary frequency division ratio.

In the present invention, the real number M is preferably set according to an input signal from the outside. further,
A selection circuit is provided which selects from the generated divided signals based on the selection control signal and outputs the selected signal.

According to the present invention, the phase comparison circuit compares the phases of the reference clock signal and the frequency-divided signal from the M frequency division circuit, and the frequency multiplication circuit determines the frequency of the reference clock signal according to the comparison result. A multiplication signal multiplied by the multiplication factor defined by M is generated. Then, the signal generation circuit generates a divided signal obtained by dividing the multiplied signal by M and feeds it back to the phase comparison circuit. As a result, a multiplied signal that follows the reference clock signal and is always in phase with the reference clock signal is obtained. Further, in the clock generation circuit, the multiplied signal is delayed by an arbitrary period, for example, by a delay circuit, and then divided based on a real number arbitrarily set by the frequency dividing circuit, and a selection control signal is selected from among the divided signals. In accordance with the above, at least one divided signal is selected and output.

As a result, it is possible to generate a clock signal having a phase shift arbitrarily set with respect to the reference signal, the generated clock signal has high accuracy, and the followability to the reference signal is good.

[0010]

1 is a circuit diagram showing an embodiment of a clock generation circuit according to the present invention. In FIG.
10 is a phase comparator, 20 is a counter, 30 is a frequency multiplier, 40 is a programmable mask generation circuit, 50 is a programmable frequency divider, and T _fin is an input terminal of the reference clock signal fin.

The phase comparator 10 compares the phases of the reference clock signal fin input from the input terminal T _fin and the frequency-divided signal S50 from the programmable frequency divider 50, and the up / down control signal S10 corresponding to the comparison result. Counter 20
Output to For example, when the phase of the divided signal S50 is advanced with respect to the reference clock signal fin, the control signal S10 instructing the countdown is output to the counter 20, and in the opposite case, the control signal S10 instructing the countup is output. Is output to the counter 20.

The counter 20 counts up or counts down the counter value according to the up / down control signal S10 from the phase comparator 10, for example, (l +
The m) bit counter value S20 is set and output to the frequency multiplier 30.

The frequency multiplier 30 determines the oscillation frequency based on the counter value S20 from the counter 20, and multiplies the input reference clock signal fin by L × M (where L and M are real numbers). The signal dlo is generated and output to the programmable mask generation circuit 40. Here, the real number L is set by the 1-bit frequency division control signal SL input to the programmable frequency divider 50, and the real number M is set by the m-bit frequency division control signal SM input to the programmable mask generation circuit 40. It is set.

The programmable mask generation circuit 40 receives the clock signal dlo from the frequency multiplier 30, divides it by M to generate a clock signal f ₀ , outputs it to the programmable frequency divider 50, and outputs the clock signal dlo in advance. Multiple clock signals delayed by the set time f ₀₁ '
˜f _0k-1 ′ are generated, and these clock signals f ₀₁ ′ to f _0k-1 ′ are generated according to the frequency division control signal SM input from the outside.
Of the clock signals f ₀₁ 'to f _0k-1 ' divided by M according to the n-bit selection control signal SN input from the outside. Output. Here, the value of k is set according to the selection control signal SN and is (k = 2 ⁿ ).

The programmable frequency divider 50 receives the clock signal f ₀ from the programmable mask generation circuit 40, and in response to an external 1-bit frequency division control signal SL.
The clock signal f ₀ from the programmable mask generation circuit 40 is divided by L based on the real number L set by the division control signal SL to generate a divided signal S50, which is output to the phase comparator 10.

As shown, the phase comparator 10, the counter 20, the frequency multiplier 30, the programmable mask generation circuit 40, and the programmable frequency divider 50 allow the PLL to
A circuit is configured, and this PLL circuit generates a 2πN / M phase-shifted clock signal with respect to the input reference clock signal, and the programmable mask generation circuit 40 selectively outputs it.

FIG. 2 shows a programmable mask generation circuit 40.
It is a circuit diagram which shows one structural example. As shown in the figure, the programmable mask generation circuit 40 has k AND gates AG
T ₀ , AGT ₁ , AGT ₂ , ..., AGT _k-2 , AGT
_k−1 , (k−1) delay circuits W ₁ , W ₂ , W ₃ , ...,
It comprises W _k-2 and W _k-1 , a programmable frequency dividing circuit 41, and a selecting circuit 42.

AND gates AGT ₀ , AGT ₁ , AGT
₂ , ..., AGT _k-2 , AGT _k-1 are two-input AND gates, and one input terminal of these AND gates is connected to the input terminal T _dlo of the clock signal dlo.
The other input terminal of the AND gate AGT ₀ is connected to the power supply voltage V _CC.
Of the AND gates AGT ₁ and AGT
_{2, ..., AGT k-2} , AGT k-1 of the other input terminal is the delay circuits of _{W 1, W 2, ...,} W k-2, W k-1 of the delayed signal S _1, S _2, ..., Output terminals sel of S _k-2 and S _k-1
It is connected to the.

Then, the output signal of the AND gate AGT ₀ is frequency-divided by M via the programmable frequency dividing circuit 41 and output as the clock signal f ₀ . The clock signal f ₀ is in phase synchronization with the clock signal dlo input to the programmable mask generation circuit 40. This clock signal f
₀ is output to the programmable frequency divider 50 as shown in FIG.

AND gates AGT ₁ , AGT ₂ , ..., A
The output signals of GT _k-2 and AGT _k-1 are frequency _- divided by the programmable frequency divider 50, and further selected by the selection circuit 42 according to the selection control signal SN input from the outside and output.

FIG. 3 is a circuit diagram showing an example of the configuration of the delay circuit.
is there. The delay circuit W shown in FIG. ₁, W_Two,…, W
_k-2, W_k-1All have similar configurations, so here
Then, the delay circuit W_iIs illustrated as an example.

As shown in FIG. 3, the delay circuit W_iIs Inva
Data INV₁, AND gate AGT _W1, AGT_W2, RS
Flip-flop RSF_W1, RSF_W2 Composed by
Have been. in is a clock signal input terminal, reset
Is a reset signal input terminal, and sel is a delayed signal S_iOut of
Input terminal, clk is a clock signal input terminal, and out is a delay
The output terminals of the extended clock signal are shown respectively.

The input terminal in of the clock signal is the input terminal of the inverter INV ₁ and the RS flip-flop RSF.
Connected to the set signal input terminal S of _W1 and connected to the inverter IN
The output terminal Q of the output terminal and the RS flip-flop RSF _W1 of V ₁ was being respectively connected to the input terminals of the AND gates AGT _W1, the output terminal of the AND gate AGT _W1 is connected to the set signal input terminal S of the RS flip-flop RSF _W2 Has been done.

RS flip-flops RSF _W1 , RSF _W2
Reset signal input terminal R of the reset signal input terminal re
It is commonly connected to set. The output terminal Q of the RS flip-flop RSF _W2 is connected to the output terminal sel of the delay signal S _i , and further connected to one input terminal of the AND gate AGT _W2 . The other input terminal of the AND gate AGT _W2 is connected to the clock signal input terminal clk.

The operation of the delay circuit W _i will be described below. Before the delay circuit W _i starts its operation, the reset signal input terminal re
For example, a high-level reset signal is input to the set from the outside. In response to this, the RS flip-flop R
SF _W1 and RS F _W2 are reset, and a low level signal, for example, a ground potential GND level signal is output to the output terminal Q.

After the reset signal is switched to the low level, the delay circuit W _i starts operating. Input terminal i
At the rising edge of the clock signal input to n, the output signal of the output terminal Q of the RS flip-flop RSF _W1 is switched to the high level, for example, the power supply voltage V _CC level. In addition, the clock signal input to the input terminal in is inverted by the inverter INV ₁ , and the AND gate AGT _W1 generates a logical product with the signal output to the output terminal Q of the RS flip-flop RSF _W1.
It is output to the flip-flop RSF _W2 . That is, A
The ND gate AGT _W1 outputs a clock signal (inversion signal) delayed by a half cycle from the clock signal input to the input terminal in.

In the RS flip-flop RSF _W2 ,
A high level signal is output to the output terminal Q from the rising edge of the clock signal from the AND gate AGT _W1 . Therefore, the delay signal S _i that switches to the high level after being delayed by a half cycle of the clock signal from the clock signal input to the input terminal in is output to the output terminal sel. Further, the AND gate AGT _W2 generates a logical product of the delayed signal and the clock signal from the clock signal input terminal clk, and outputs the logical product to the output terminal out.

In the circuit diagram of the programmable mask generation circuit 40 shown in FIG. 2, the clock signal input terminal in of the delay circuit W ₁ is connected to the input terminal T _dlo of the clock signal dlo. Also, the delay circuits W ₁ , W ₂ , ..., W
The clock signal input terminals clk of _k-2 and W _k-1 are all connected to the input terminal T _dlo of the clock signal dlo, and the reset signal input terminals reset are all connected to the input terminal T _{RS T} of the system reset signal RST. . further,
The output terminal out of the delay circuit W _{i in} the front stage is connected to the clock signal input terminal in of the delay circuit W _{i + 1 in} the rear stage.

The operation of the programmable mask generation circuit 40 having such a configuration will be described below with reference to the waveform chart shown in FIG. Note that FIG. 4 shows an operation example of the programmable mask generation circuit 40, for example, L = 1,
The waveform of the output signal in the case of M = 4 and N = 3 is shown.

Before the clock generation circuit starts operating, for example, a high level system reset signal RST is generated, and in response to this, each delay circuit W ₁ , W ₂ , ...,
W _k-2 and W _{k- 1} are reset, and these delay circuits output delay signals S ₁ , S ₂ , ..., S _k-2 , S _{k-1 of} low level, for example, the ground potential GND level. To be done.

After the system reset signal RST is released, for example, after switching to the low level, the input terminal T
_The clock signal dlo is input from dlo. As shown in the waveform diagram of FIG. 4, the clock signal dlo multiplied by 4 is phase-synchronized with the reference clock signal fin and the frequency multiplier 3
0, and the programmable mask generation circuit 40
Is input to In the programmable mask generation circuit 40, the input clock signal dlo has the AND gate A
The GT ₀ outputs the clock signal f ₀ ′ in phase with the GT ₀ . The clock signal f ₀ 'is frequency-divided by M by the programmable frequency dividing circuit 41 to obtain the clock signal f ₀ as shown in FIG.
It is output to the programmable frequency divider 50 shown in.

Delay circuits W ₁ , W ₂ , ..., W _k-2 , W _k-1
Thus, with respect to the clock signals input to the respective clock signal input terminals in, the delay signal S ₁ , which switches to the high level at the falling edge of the first clock signal,
S ₂ , ..., S _k-2 , S _k-1 are output. These delayed signals are respectively AND gates AGT ₁ , AGT ₂ ,.
It is input to AGT _k-2 and AGT _k-1 .

Therefore, the AND gate AGT _i
For the clock signal dlo, i (i = 1, 2, ..., K-
The clock signal f _0i ′ synchronized with the clock signal dlo is output with a delay of 1, k−2) cycles. Then, by the programmable frequency dividing circuit 41, these clock signals f ₀₁ '
~ F _0k-1 'is _divided by M, for example, 4. Clock signals f ₀₁ , f ₀₂ , which are divided by four by the selection circuit 42,
, F _0k-2 , f _0k-1 are selected and output according to the input selection control signal SN. Therefore, the clock signal f _0i clock signal f _0, which is selected, i /
It has a phase shift of M cycles.

As described above, the programmable mask generation circuit 40 sets 0 for one cycle to the reference clock signal.
A clock signal whose phase is shifted by (M-1) / M is generated. Further, depending on the selection control signal SN, 2πN / M
The phase-shifted clock signal is selected and output.

The operation of the entire clock generation circuit shown in FIG. 1 will be described below. As described above, this clock generation circuit is composed of the PLL circuit. In the clock signal generation circuit, the system reset signal RST is generated before the operation is started, whereby the entire circuit is reset. Then, the m-bit frequency division control signal SM and the n-bit selection control signal SN are input to the programmable mask generation circuit 40, and the programmable frequency divider 50 is further input.
The 1-bit frequency division control signal SL is input to.

After the system reset signal RST is released, the clock generation circuit starts operating. Phase comparator 10
As a result, the reference clock signal fin input from the input terminal T _fin and the frequency-divided signal S from the programmable frequency divider 50 are input.
The phases of 50 are compared, and the up / down control signal S10 is output to the counter 20 according to the comparison result. Then, the counter value is set by the counter 20 according to the up / down control signal S10 from the phase comparator 10, and is output to the frequency multiplier 30.

In the frequency multiplier 30, the counter 20
A clock signal dlo that is L × M multiplied with respect to the reference clock signal fin is generated according to the counter value from
It is output to the programmable mask generation circuit 40. In the programmable mask generation circuit 40, a clock signal f _{0 in} phase with the reference clock signal fin is generated based on the clock signal dlo and output to the programmable frequency divider 50. Also, with respect to the reference clock signal fin,
A clock signal with a phase shift of 2πN / M is generated, and one or more clock signals are selected and output according to the selection control signal.

Then, the programmable mask generation circuit 4
In response to the clock signal f 0 from ₀ , the programmable frequency divider 50 generates a frequency-divided signal S50 divided by L, and outputs the frequency-divided signal S50 to the phase comparator 10. In this way, the clock signal dlo from the frequency multiplier 30 is frequency-divided and fed back to the phase comparator 10, so that the clock signal dlo output by the frequency multiplier 30 follows the reference clock signal fin and is always Phase synchronization is maintained. As a result, the phase-shifted clock signal generated by the programmable mask generation circuit 40 follows the frequency fluctuation of the reference clock signal fin.

In this example, the digital PLL
Although the clock generating circuit is configured by the circuit, the present invention is not limited to this, and the clock generating circuit may be configured by an analog PLL circuit, for example. That is, an analog phase comparator is used instead of the phase comparator 10, a low-pass filter is used instead of the counter 20, and a VCO (voltage controlled oscillation) circuit is used instead of the frequency multiplier 30, and a phase difference signal is obtained by the analog phase comparator. Output,
The low frequency component is extracted by the low pass filter and
Output to the circuit to control the oscillation frequency of the VCO circuit. V
The CO circuit generates the clock signal dlo, and in response to this, the programmable mask generation circuit 40 similar to that of the present embodiment is used to generate a clock signal having a phase shift arbitrarily set with respect to the reference clock signal fin. .

As described above, according to this embodiment, the clock signal d obtained by multiplying the reference clock signal by L × M is used.
Based on lo, delay circuits W ₁ , W ₂ , ..., W _k-2 , W
_{By k-1} , delay signals S ₁ , S ₂ , ..., S _k-2 , S _k-1 that switch from the falling edge of the 1, 2, ..., K-1th clock signal to the high level are generated. , AND gates AGT ₁ , AGT ₂ , ..., AGT _k-2 , AGT _k-1 generate a logical product of the delay signal and the clock signal dlo, and the programmable frequency dividing circuit 41 divides it by M, and the selecting circuit 42 Since they are selected and output, it is possible to generate a clock signal having a phase shift of 2πN / M with respect to the reference clock signal, and to follow the reference clock signal well, and to obtain a highly accurate phase shift clock signal.

[0041]

As described above, according to the clock generation circuit of the present invention, it is possible to generate a phase-shifted clock signal with high accuracy with respect to the reference clock signal and to follow the fluctuation of the frequency of the reference clock signal. Good, there is an advantage that the phase shift can be set arbitrarily.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a clock generation circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a programmable mask generation circuit 40.

FIG. 3 is a circuit diagram showing a configuration of a delay circuit.

FIG. 4 is a waveform diagram of a clock generation circuit.

FIG. 5 is a waveform diagram of a general phase-shifted clock generation circuit.

[Explanation of symbols]

10 ... Phase comparator, 20 ... Counter, 30 ... Frequency multiplier, 40 ... Programmable mask generation circuit, 50 ... Programmable frequency divider, T _fin ... Reference clock signal input terminal, AGT ₀ , AGT ₁ , AGT ₂ , , AGT _k-2 ,
AGT _k-1 ... AND gate, W ₁ , W ₂ , W ₃ , ..., W
_k-2 , W _k-1 ... Delay circuit, 41 ... Programmable frequency _dividing circuit, 42 ... Selection circuit, V _CC ... Power supply voltage, 1 ... Power supply voltage V
_CC supply line, GND ... Ground potential.

Claims (6)

[Claims] 1. A phase comparison circuit for comparing the phases of a signal to be compared with a reference clock signal and outputting a control signal according to the comparison result; and a phase comparison circuit which receives the control signal and has a multiplication factor defined by a real number M. A frequency multiplication circuit that outputs a frequency-multiplied signal and a frequency-divided signal that receives the frequency-multiplied signal and frequency-divides the frequency-multiplied signal by M and outputs the frequency-compensated signal to the phase comparison circuit as the compared signal. And a signal generation circuit that generates at least one delayed signal by delaying the delayed signal at different preset times and generates a signal obtained by dividing the delayed signal with an arbitrary frequency division ratio. 2. The clock generation circuit according to claim 1, wherein the real number M is set according to an input signal from the outside. 3. The M divided signal of the signal generating circuit is divided between the signal generating circuit and the phase comparing circuit by a dividing ratio defined by a real number L, and the divided signal is used as the compared signal. 2. The clock generation circuit according to claim 1, further comprising a second frequency dividing circuit for inputting to the phase comparison circuit. 4. The clock generation circuit according to claim 3, wherein the real number L is set according to an input signal from the outside. 5. The clock generation circuit according to claim 1, wherein the signal generation circuit includes a selection circuit which selects and outputs at least one frequency division signal from the frequency division signals generated based on the selection control signal. 6. The signal generation circuit includes at least one delay circuit for delaying an input signal by a predetermined period and outputting the delayed signal, wherein the first stage delay circuit receives the multiplied signal and the second and subsequent stages. 2. The clock generation circuit according to claim 1, wherein the output signal of the preceding stage is input to the delay circuit.