JPH0753313Y2 - A / D conversion circuit - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention is an A / D used in a digital television or the like.
Regarding the conversion circuit.

[Prior Art and its Problems] In a digital television such as a liquid crystal television using a liquid crystal display element in a display unit, an A / D conversion circuit having a configuration shown in FIG. 2 has been conventionally used. The figure shows a MOS type IC.
It shows a 4-bit A / D conversion circuit configured by the. The analog input signal In has 15 stages of comparators 1a to 1o.
Is input to each. Reference voltages Vr1 to Vr15, which are resistance-divided by resistors 2a to 2o connected in series, are input to these comparators 1a to 1o, respectively, and both inputs are compared according to sampling clocks φ21 and φ11, and the comparison is performed. The result is sent to the latch circuit 3 at the next stage as digital output data of logic "1" or "0" level.
According to the latch clock input to this latch circuit 3,
When the digital data from 1a to 1o is output to the encoder 4, the encoder 4 sends this to the 4-bit digital data D1.
.. to D4, and sends it to a processing circuit in the next stage (not shown).

Here, each of the comparators 1a to 1o has a circuit configuration as shown in FIG. The figure shows the above comparator
1 shows a circuit configuration of one of 1a to 1o. The analog input signal In input via the gate circuit 11 and the reference voltage Vrn input via the gate circuit 12 are superimposed at point a and sent to the capacitor 13. This capacitor 13
Then, the signal is transmitted to the inverter 14 through the point b. The inverted output of the inverter 14 is output via the point c, and is fed back from the point c to the point b via the gate circuit 15. Here, the sampling clock φ21 is input to the gate circuit 11 and the clock φ11 obtained by inverting the sampling clock φ21 by the inverter 16 is input to the gate circuits 12 and 15 as gate control clocks. The signal levels at the clocks φ21, φ11 and points b and c are all logic "1" or "0" level.

FIG. 4 shows the signal waveforms of the above respective parts, and it is assumed that signals having the waveforms shown in FIG. 4 (1) have been input as the analog input signal In and the reference voltage Vrn. On the other hand, when the sampling clock φ21 becomes “1” as shown in FIGS.
The discharge period is when 11 becomes “1”. a
The signal sampled at the point as shown in FIG. 4 (4) is sent to the point b via the capacitor 13. Since feedback is applied to the point b by the output of the inverter 14 of the next stage, the potential at the point b becomes the threshold level of the inverter 14 as shown in FIG. 4 (5).

Therefore, the P-channel and N-channel of the transistors forming the inverter 14 may be turned on at the same time, and a large amount of current may flow through the inverter 14. Therefore, there is a disadvantage that the battery life is shortened particularly in a pocket television or the like using a battery whose power consumption is limited as a power source. It is also possible to turn on / off the power supply of the entire A / D conversion circuit as needed to save power, but this causes a problem that noise is likely to occur.

[Object of the Invention] The present invention has been made in view of the above circumstances. The circuit configuration of the comparator of the A / D conversion circuit for sampling the video signal has been improved to reduce power consumption and to cause malfunctions and noise. It is an object of the present invention to provide an A / D conversion circuit that suppresses as much as possible.

[Summary of the Invention] In order to achieve the above object, the present invention includes a comparator of an A / D conversion circuit for sampling a video signal, a first analog switch for turning an input signal on and off with a first clock signal, A second analog switch that turns on and off the comparison voltage with a second clock signal whose phase is inverted from that of the first clock signal; and a capacitor to which a combined output of the first and second analog switches is input. An output of the capacitor and a predetermined timing signal generated during the blanking period of the video signal are supplied, and a NOR circuit for making the output of the capacitor conductive by the timing signal and an output of the NOR circuit for the second clock. The output of the NOR circuit is combined with the output of the capacitor through a third analog switch which is turned on / off by a signal. The output of the NOR circuit is fixed to "0" during the blanking period of the video signal.
It is characterized in that a through current is prevented from flowing.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of one of the multi-stage comparators that constitute the A / D conversion circuit. An analog input signal In input via the gate circuit 21 operated by the sampling clock φ21 and a reference voltage Vr input via the gate circuit 22 operated by the same clock φ11
n and n are superimposed at point d and sent to the condenser 23. The signal through the capacitor 23 is then input to the NOR gate 24 through the point e. The chip enable signal CE is also input to the NOR gate 24, and the logical output thereof is output via the point f, and from the point f, via the gate circuit 25 operated by the clock φ11, Feedback is given to point e. An inverter (not shown) outputs a sampling clock φ21 to the gate circuit 21 and a sampling clock φ21 to the gate circuits 22 and 25.
The clock φ11 inverted at is input as the gate control clock. The signal levels of the clocks φ21, φ11, the points d and e, and the chip enable signal CE are logic "1" or "0" level.

In such a configuration, the "1" level signal is input to the NOR gate 24 as the chip enable signal only when the received video signal is in the vertical and horizontal blanking periods. This input causes the NOR gate 24 to stop operating regardless of the level of the signal input via the point e. In addition, except the above vertical and horizontal blanking periods,
A "0" level signal is input to the NOR gate 24 as a chip enable signal. With this input, NOR gate 24
Output "0" level when the signal input through point e is "1" level, and output "1" level when the input signal is "0" level. Then, this output is sent to the latch circuit (not shown) at the next stage via point e.

As described above, according to the present invention, the comparator of the A / D conversion circuit for sampling the video signal, the first analog switch for turning on / off the input signal with the first clock signal, A second analog switch that turns on and off the comparison voltage with a second clock signal whose phase is inverted from that of the first clock signal; and a capacitor to which a combined output of the first and second analog switches is input. An output of the capacitor and a predetermined timing signal generated during the blanking period of the video signal are supplied, and a NOR circuit for making the output of the capacitor conductive by the timing signal and an output of the NOR circuit for the second clock. The output of the NOR circuit is combined with the output of the capacitor through a third analog switch that is turned on / off by a signal, and the output of the NOR circuit is combined. Since it is supplied to the switch circuit, the output of the NOR circuit can be fixed to "0" during the blanking period of the video signal, so that no through current flows, resulting in low power consumption and malfunction. A / that minimizes the occurrence of noise and noise
A D conversion circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of a conventional A / D conversion circuit, and FIG. 3 is a detailed circuit diagram of the comparator of FIG. FIG. 4 is a block diagram showing the configuration, and FIG. 4 is a timing chart showing each signal waveform of FIG. 1a to 1o …… Comparator, 3 …… Latch circuit, 4 …… Encoder, 11,12,15,21,22,25 …… Gate circuit, 14,16…
… Inverter, 24 …… Noah gate.

Claims (1)

[Scope of utility model registration request] 1. A video signal for sampling a video signal including a plurality of stages of comparators to which an input video signal and a comparison voltage are input, a latch circuit for latching the output of the comparator, and a decoder for decoding the output of the latch circuit. In the A / D conversion circuit of, the comparator has a first analog switch for turning on / off the input signal with the first clock signal, and a second clock whose comparison voltage has a phase inverted from that of the first clock signal. A second analog switch that is turned on / off by a signal, a capacitor to which the combined output of the first and second analog switches is input, and a predetermined timing signal generated during the blanking period of the output of this capacitor and the video signal. And a NOR circuit for making the output of the capacitor conductive by the timing signal, and the NOR circuit The output is combined with the output of the capacitor through a third analog switch that turns on and off with the second clock signal, and the output of the NOR circuit is supplied to the latch circuit. Inside is an A / D conversion circuit characterized in that the output of the NOR circuit is fixed at "0" so that a through current does not flow.