JPH01151349A - Dtmf circuit - Google Patents

Abstract

PURPOSE:To obtain a highly accurate DTMF signal by a low basic clock frequency by providing a clock input control circuit to change the frequency dividing ratio of a frequency dividing circuit in a period detected by a correction interval detecting circuit to detect a specific D/A converting period. CONSTITUTION:The title circuit is provided with down counters 1 and 11, n-adic counters 2 and 12, decoders 4 and 14, D/A converters 5 and 15, a synthesizing circuit 6, first and second correction interval detecting circuits 8 and 18 to decode the outputs of the n-adic counters 2 and 12 and to detect the correction interval and first and second clock input control circuits 7 and 17 to control a clock input and to change the frequency dividing ratio of the frequency dividing circuit concerning a basic clock CLK in the period of the outputs of the correction interval detecting circuits 8 and 18. Thus, since the correction interval detecting means 8 and 18 and the frequency dividing ratio changing means 7 and 17 are provided, the highly accurate synthetic (DTMF) signal of two frequencies can be obtained by the low basic clock.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a DT in a 1-n dial system of a telephone.
This invention relates to a DTMF circuit that generates an MF signal.

[Conventional technology]

FIG. 6 shows a conventional DTMF circuit, in which 1.
11 is a down counter with preset that presets preset data Nl and N2 and counts down according to the clock signal CLK; 2°12 is a down counter 1, 1
3 and 13 are n-ary counters 2 and 13; sine waveform generating circuits that output analog values and output sine waveforms according to each count value of n-ary counters 2 and 12; 4;
゜14 is a decoder for outputting an analog value corresponding to each count value of the n-ary counters 2 and 12, and 5゜15 is a D-A for converting the output value of the decoder 4.14 into an analog value.
A converter 6 synthesizes the outputs of the D-A converters 5 and 15 and converts them into D.
This is a synthesis circuit that outputs a TMF signal.

Next, the operation will be explained.

FIG. 8 shows the correspondence between keys on the telephone keyboard and frequencies. When a key is pressed, frequencies corresponding to the two rows and columns are generated separately, and a signal (DTMF
signal) to the telephone line. The frequency deviation of the DTMF signal is standardized to be within ±1.5%. Since there is a standard that the frequency deviation is within ±1.5%, 3.58 MHz is generally used as the basic clock, and 3.58 MHz will be used in the description of the conventional example.

Further, the explanation will be made assuming that the value of n of the n-ary counter is 14.

When the field key is pressed, a 697Hz signal and 1209H
Generate the z signal, combine the two signals, and convert the DTMF
Outputs the signal to the telephone line. When the key is pressed, the preset value of the down counter with preset (N1=
368. N2 = 212) is output from the control circuit (not shown), and the down counter 1.11 with preset outputs 3.58 MHz, 3.58 MHz, and 3.58 MHz, respectively.
Hz 3.58MHzN2 2
12 Start frequency division. Down counter with precent 1゜11
The outputs of are input to hexadecimal counters 2 and 12, respectively. The output of the hexadecimal counters 2 and 12 is sent to the decoder 4.14.
DA converter 5.1 corresponding to the count value input to
5 is converted into a digital value that becomes the input to the D-A converter 5.
．． 15, it is converted into an analog value, and a sine waveform as shown in FIG. 7 is output. Therefore, the D-A converter 5.15
The frequency of the sine waveform output from each is 68X1
4, which is ±1 of the frequency standard 697Hz and 1209Hz.
．． An output that satisfies the frequency deviation within 5% can be obtained. D
- The outputs of the A converters 5 and 15 are combined in a combining circuit 6,
A DTMF signal is output.

Similar operations are performed for the other keys, and the output frequency of the DA converter 5.15 is as follows. Next, Table 2 shows the relationship between the keys and preset values Nl and N2.

Table 2 [Problems to be solved by the invention] Since the conventional DTMF circuit is configured as described above, it is necessary to increase the fundamental frequency in order to obtain a high-precision predetermined frequency, and it is difficult to integrate the circuit. However, there were problems such as increased power consumption.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a DTMF circuit that can generate a highly accurate DTMF signal at a low fundamental frequency.

[Means for solving problems]

The DTMF circuit according to the present invention includes a correction interval detection means for detecting a specific D-A conversion period, and a frequency division ratio change for controlling the detected period and clock input to change the frequency division ratio of the frequency divider circuit. The means are provided.

[Effect]

Since the DTMF circuit according to the present invention is provided with the correction interval detection means and the frequency division ratio changing means, it is possible to obtain a highly accurate DTMF signal with a low basic clock.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a DTMF circuit according to an embodiment of the present invention. In the figure, 1 and 11 are down counters, 2 and 12 are n-ary counters, 4.14 is a decoder, and 5.
15 is a D-A converter, 6 is a synthesis circuit, and 8 and 18 are first . A second correction interval detection circuit 7.17 converts the basic clock CLK into a period of the output of the correction interval detection circuit 8.18.
The first circuit controls the clock input and changes the division ratio of the frequency divider circuit.
．． A second clock input control circuit, also Nl.

N2 is preset value, AI, A2 is down counter 1,
11, Sl and N2 are set values, and C1 and C2 are outputs of the correction interval detection circuit 8.18.

Figure 2 is shown in Figure 1 above. Second clock input control circuit 7, 1
In the figure, 20.21 is a flip-flop, 22 is an AND gate, 23 is a NOR gate, and C
LK is a clock, and a is the output of the clip-flop 21.

3 is a circuit diagram showing an example of the n-ary counter 2 and the first correction interval detection circuit 8, and FIG. 4 is a circuit diagram showing an example of the n-ary counter 12 and the second correction interval detection circuit 18. In the figure, FF is a flick flop, NAND is a Nant gate, INV is an inverter, AND is an AND gate, and NOR is a NOR gate.

Next, the operation will be explained.

The basic clock frequency is 400KHz, and the n of the n-ary counter is
The following explanation assumes that the value is 14. When the field key on the telephone keyboard is pressed, the control circuit (not shown) outputs N1=41.
．． N2=23. SL multiplication signal 0" and N2 signal "1" are output. When ci and C2 are "0", the same operation as in the conventional example is performed, and the down counters 1 and 11 with presets output them, and 14 It is output to hexadecimal counters 2 and 12. The count value of hexadecimal counter 2 is "0".

7'', C1 becomes “1” and is input to the clock input control circuit 7. In the clock input control circuit 7, one pulse of the basic clock is prohibited. Therefore, the count value of the hexadecimal counter 2 is “0”. In the periods of and "7", the down counter 1 with preset performs frequency division.Similarly, the down counter 11 with preset
In this case, the numbers of the hexadecimal counter 12 are 5", 6",
7″ mBm, sg”, “12”, “13” IIQ”
, "1", and '2', the frequency is divided by 23+1, resulting in the frequency. Therefore, the frequencies output from the DA converter 5.15 are: =694.4 Hz =1204. 8Hz. Perform the same operation for other keys.゛5th
The figure shows a timing diagram of the clock input control circuit 7.17.

Table 1 shows the correspondence between keys, Nl and N2, and the frequency calculation formula.

Table 1 [Effects of the Invention] As described above, according to the present invention, there is a correction interval detection circuit that detects a specific D-A conversion period, and a clock that changes the detected period and the frequency division ratio of the frequency divider circuit. Since an input control circuit is provided, high precision DTM can be achieved with a low basic tarok frequency.
By obtaining the F signal and lowering the clock frequency, it is possible to reduce power consumption when integrating the DTMF circuit into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DTMF circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a clock input control circuit, and FIG.
4 are circuit diagrams of an example of the correction interval detection circuit, FIG. 5 is a timing diagram of the circuit of FIG. 2, FIG. 6 is a circuit diagram of a conventional DTMF circuit, and FIG. The output waveform diagram of the converter, FIG. 8, is a diagram showing the relationship between the keyboard of the telephone and the frequency. 1.11 is down counter with precent, 2゜12 is n
4.14 is a decoder, 5.15 is a DA converter, 6 is a synthesis circuit, 7.17 is a clock signal control circuit, and 8.18 is a correction interval detection circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Equipped with a frequency dividing circuit that divides the clock input, a counter that counts the frequency divided output of this frequency dividing circuit, and a DA converter that converts the output of this counter from D to A, A DTMF circuit that generates a DTMF signal includes a correction interval detection means that receives the value of the counter as an input and detects a specific D-A conversion period, and a frequency division ratio of the frequency division circuit for the period detected by the detection means. A DTMF circuit characterized in that it is equipped with a dividing ratio changing means for changing the frequency division ratio.