JPH02224558A - Dtmf generating circuit - Google Patents
Dtmf generating circuitInfo
- Publication number
- JPH02224558A JPH02224558A JP4613589A JP4613589A JPH02224558A JP H02224558 A JPH02224558 A JP H02224558A JP 4613589 A JP4613589 A JP 4613589A JP 4613589 A JP4613589 A JP 4613589A JP H02224558 A JPH02224558 A JP H02224558A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- dtmf
- preset value
- circuit
- frequency division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
この発明は、電話器を構成するＩＣに於けるＤｕａｌ
Ｔｏｎｅ Ｍｕｌｔｉ Ｆｒｅｇｕｅｎｃｙ（以
下ＤＴＭＦとする）発生回路に関する。[Detailed Description of the Invention] [Industrial Application Field 1] This invention is applicable to dual
The present invention relates to a Tone Multi Frequency (hereinafter referred to as DTMF) generation circuit.
［発明の概要Ｊ
この発明は、ＤＴＭＦ発生回路に於て、Ｄ−Ａ変換回路
の入力信号即ち分周回路の出力信号の一部をプリセッタ
プルカウンタにフィードバックさせ、ＤＴＭＦのそれぞ
れの周波数の一周期の内でプリセット値を変化させ、基
準クロックから見て非整数分の−の分周ができるように
した物である。[Summary of the Invention J This invention provides a DTMF generation circuit that feeds back a part of the input signal of the DA converter circuit, that is, the output signal of the frequency divider circuit, to a presetter pull counter, and generates one cycle of each frequency of the DTMF. It is possible to change the preset value within the standard clock to perform frequency division by a non-integer when viewed from the reference clock.
〔従来の技術］ 従来のＤＴＭＦ発生回路を第２図に示す。[Conventional technology] A conventional DTMF generation circuit is shown in FIG.
基準クロックＣＬＩ、Ｃｌ３とはプリセッタプルカウン
タ２と６の端子１０と１７にそれぞれ入力され、ＤＴＭ
Ｆに対応した比で分周される。その出力信号は、分周回
路３と７に入力される６分周回路３と７の出力は、Ｄ−
Ａ変換回路３０に入力され、Ｄ−Ａ変換される。The reference clocks CLI and Cl3 are input to terminals 10 and 17 of presetter pull counters 2 and 6, respectively, and the DTM
The frequency is divided by a ratio corresponding to F. The output signal is input to the frequency divider circuits 3 and 7.The output of the 6 frequency divider circuits 3 and 7 is D-
The signal is input to the A conversion circuit 30 and subjected to DA conversion.
〔発明が解決しようとしている課題１
しかし、従来のＤＴＭＦ発生回路は、プリセッタプルカ
ウンタ２と６の分周比によってきまる周波数が、最終的
に得たいＤＴＭＦに合わない場合には、基準クロックの
周波数を高くして、精度を上げる以外に方法がなかった
。[Problem to be Solved by the Invention 1] However, in the conventional DTMF generation circuit, when the frequency determined by the division ratio of the presetter pull counters 2 and 6 does not match the desired DTMF, the frequency of the reference clock is There was no other way but to increase the accuracy by increasing the value.
〔課題を解決するための手段］
そこで、この発明は、従来のこのような欠点を克服する
ため１分周回路３と７の出力信号をデコーダ４と８を用
いてデコードしその出力信号をプリセッタプルカウンタ
２と６にフィードバックしＤＴＭＦのそれぞれの周波数
の一周期内で、プリセッタプルカウンタの分周比を変え
、比整数分の−の分周を行わせるようにしたものである
。[Means for Solving the Problems] Therefore, in order to overcome these conventional drawbacks, the present invention decodes the output signals of the divide-by-one circuits 3 and 7 using decoders 4 and 8, and presets the output signals. Feedback is made to the tuple counters 2 and 6, and the frequency division ratio of the presetter pull counter is changed within one cycle of each frequency of the DTMF, so that the frequency is divided by an integer of the ratio.
〔作用］
上記のように構成されたＤＴＭＦ発生回路に於て、ＤＴ
ＭＦに対応したプリセット値をプリセッタプルカウンタ
にセットし基準クロック信号をプリセッタプルカウンタ
に入力すると、セットされた値の分周を行った後にキャ
リィ信号が、分周回路に入力され、分周回路の各桁の出
力が、Ｄ−Ａ変換回路に入力される。この時、分周回路
の出力値は１つのＤＣレベルに対応し、結局、プリセッ
トカウンタのプリセット値がＤＴＭＦの周波数を決める
。そこで、分周回路の出力値をデコードした信号でプリ
セット値を変える事により、プリセックプルカウンタに
比整数分の−の分周を行なわせると、基準クロックを整
数分の−で分周した以上の精度のＤＴＭＦを得られる。[Operation] In the DTMF generation circuit configured as described above, DT
When a preset value corresponding to MF is set in the presetter pull counter and a reference clock signal is input to the presetter pull counter, the carry signal is input to the frequency divider circuit after the set value is divided. The output of each digit is input to the DA conversion circuit. At this time, the output value of the frequency dividing circuit corresponds to one DC level, and the preset value of the preset counter ultimately determines the frequency of the DTMF. Therefore, by changing the preset value with a signal obtained by decoding the output value of the frequency divider circuit, the presec pull counter can be made to divide by a negative fraction of an integer. Accurate DTMF can be obtained.
［実施例〕 以下に、この発明の実施例を図面に基づいて説明する。[Example〕 Embodiments of the present invention will be described below based on the drawings.
第１図に於いて、選択されたＤＴＭＦに対応した値がプ
リセット値設定回路１と５によりプリセッタプルカウン
タ２と６にセットされる。In FIG. 1, values corresponding to the selected DTMF are set in presetter pull counters 2 and 6 by preset value setting circuits 1 and 5.
プリセッタプルカウンタ２と６のキャリィは、分周回路
３と７に入力され、分周回路３と７の出力は、Ｄ−Ａ変
換回路９とデコーダ４と８に入力される。デコーダ４と
８の出力は、プリセット値設定回路ｌと５に入力されプ
リセット値を変える。The carries of presetter pull counters 2 and 6 are input to frequency divider circuits 3 and 7, and the outputs of frequency divider circuits 3 and 7 are input to DA conversion circuit 9 and decoders 4 and 8. The outputs of decoders 4 and 8 are input to preset value setting circuits 1 and 5 to change the preset values.
たとえば、Ｄ−Ａ変換回路の入力を５ｂｉｔとし、８９
４．８９ＫＨｚを分周して１６３３Ｈ，を得ようとする
場合、１７．１２５分の１に分周する必要があるが、こ
の場合分周回路の出力をデコードした信号により、プリ
セックプルカウンタの分周比を１７分の１にするか、１
８分の１にするが変え、８回分周する内、１回は１８分
の１分周、７回は、１７分の１分周するようにすれえば
、平均で、１７．１２５分周した事になり、望みの周波
数が得られるのである。For example, if the input of the D-A conversion circuit is 5 bits, 89
When dividing 4.89KHz to obtain 1633H, it is necessary to divide the frequency by 1/17.125, but in this case, the signal decoded from the output of the frequency divider circuit is used to divide the presec pull counter. Set the circumferential ratio to 1/17 or 1
If you change the frequency to 1/8, and divide the frequency 1/18 out of 8 times, and 1/17 the 7th time, the average frequency will be 17.125. As a result, the desired frequency can be obtained.
［発明の効果］
この発明は、以上説明したように、分周回路の出力値を
デコードした信号でプリセッタプルカウンタのプリセッ
ト値を変えるだけで、ＤＴＭＦの周波数精度をあげる効
果がある。[Effects of the Invention] As explained above, the present invention has the effect of increasing the frequency accuracy of DTMF by simply changing the preset value of the presetter pull counter using a signal obtained by decoding the output value of the frequency dividing circuit.
第１図は、この発明にがかるＤＴＭＦ発生回路のブロッ
ク図、第２図は、従来のＤＴＭＦ発生回路のブロック図
である。
１ 、５
２、６
３、７
４、８
９ ・
プリセット値設定回路
プリセッタプルカウンタ
分周回路
デコーダ
Ｄ−Ａ変換回路
（」
〜４FIG. 1 is a block diagram of a DTMF generation circuit according to the present invention, and FIG. 2 is a block diagram of a conventional DTMF generation circuit. 1, 5 2, 6 3, 7 4, 8 9 ・Preset value setting circuit Presetter pull counter Frequency divider circuit Decoder DA converter circuit (''~4
Claims (1)
プルカウンタと、前記プリセッタプルカウンタのキャリ
ィを一定の値で分周する分周回路と、前期分周回路の出
力信号をＤ・Ａ変換するＤ・Ａ変換回路とから成って、
前期分周回路の出力信号を前記プリセッタプルカウンタ
にフィードバックさせる事を特徴としたＤＴＭＦ発生回
路。A presetter pull counter that divides the reference clock in accordance with DTMF, a frequency divider circuit that divides the carry of the presetter pull counter by a constant value, and a D/A converter that converts the output signal of the previous frequency divider circuit. Consists of an A conversion circuit,
A DTMF generation circuit characterized in that the output signal of the first frequency divider circuit is fed back to the presetter pull counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4613589A JPH02224558A (en) | 1989-02-27 | 1989-02-27 | Dtmf generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4613589A JPH02224558A (en) | 1989-02-27 | 1989-02-27 | Dtmf generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02224558A true JPH02224558A (en) | 1990-09-06 |
Family
ID=12738538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4613589A Pending JPH02224558A (en) | 1989-02-27 | 1989-02-27 | Dtmf generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02224558A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0360255A (en) * | 1989-07-28 | 1991-03-15 | Rohm Co Ltd | Selective signal generating circuit |
| US5578968A (en) * | 1991-10-17 | 1996-11-26 | Shinsaku Mori | Frequency converter, multistage frequency converter and frequency synthesizer utilizing them |
| CN1101990C (en) * | 1997-02-18 | 2003-02-19 | 盛群半导体股份有限公司 | Alternately sampling dual-tone complex frequency generating method and arrangement |
-
1989
- 1989-02-27 JP JP4613589A patent/JPH02224558A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0360255A (en) * | 1989-07-28 | 1991-03-15 | Rohm Co Ltd | Selective signal generating circuit |
| US5578968A (en) * | 1991-10-17 | 1996-11-26 | Shinsaku Mori | Frequency converter, multistage frequency converter and frequency synthesizer utilizing them |
| CN1101990C (en) * | 1997-02-18 | 2003-02-19 | 盛群半导体股份有限公司 | Alternately sampling dual-tone complex frequency generating method and arrangement |
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