JPH114162A - Clock dividing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock dividing device which can optionally adjust the dividing ratio, duty and phase and can generate a dividing clock. SOLUTION: The count value of a counter 1 is compared with the Hi and Low set values inputted from the terminals 7 and 8 respectively. Then a synchronous RS flip-flop circuit 5 is controlled to acquire a divided clock that has the optional duty and phase. Meanwhile, the count value of the counter 1 is compared with the reset value inputted from a terminal 9 to control the resetting of the counter 1. Thus, a divided clock having an optional dividing ratio is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus which divides and uses a clock in a communication system, for example. It is used for.

[0002]

2. Description of the Related Art Conventionally, a circuit for ^dividing a clock by 1 / ²ⁿ using a binary counter has been often used for ^dividing a clock. Further, as disclosed in Japanese Patent Application Laid-Open No. 4-287208, there has been a configuration in which the frequency division number and the duty can be arbitrarily set.

[0003]

However, in the above-mentioned prior art, only a frequency-divided clock having a fixed phase can be generated.

[0004] The present invention solves the above problems,
It is an object of the present invention to provide a clock frequency divider capable of generating a frequency-divided clock by arbitrarily adjusting a frequency division number, a duty, and a phase.

[0005]

In order to achieve the above object, a clock frequency divider according to the present invention comprises means for setting parameters for determining a frequency division number, a duty, and a phase. Has a function of outputting a frequency-divided clock according to.

[0006]

The invention according to claim 1 of the present invention comprises means for setting a parameter for arbitrarily determining a frequency division number, and means for setting a parameter for arbitrarily determining a duty. Means for setting a parameter for arbitrarily determining a phase, means for controlling a frequency dividing counter and an output flip-flop according to the set parameter, and means for outputting a frequency-divided clock corresponding to the set parameter. , Whereby a divided clock according to the set parameters can be obtained.

According to a second aspect of the present invention, a counter which operates in synchronization with an original clock, determines a timing of a device reset by a reset signal input, and operates in synchronization with an original clock. , Hi when the set terminal is input, and L when the reset terminal is input Hi.
a synchronous RS flip-flop circuit that outputs a frequency-divided clock set to ow, and compares the output value of the counter with a preset Hi set value, and when they match, the synchronous RS flip-flop circuit And a first comparator that sends a Hi signal to a set terminal of the synchronous RS flip-flop circuit, and compares the output value of the counter with a preset Low set value. A second comparator for transmitting a signal, the output value of the counter is compared with a preset reset value, and when they match, a Hi terminal is connected to the reset terminal of the counter.
This is a clock frequency divider provided with a third comparator for transmitting a signal, whereby a frequency-divided clock according to a set parameter can be obtained.

(Embodiment) Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 shows a configuration of a clock frequency dividing device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a counter for determining the timing of the clock frequency dividing device, which operates in synchronization with the original clock input from the original clock input terminal 6, and is reset to 0 by a reset signal input. Reference numeral 2 denotes a first comparator which compares the output value of the counter 1 with the Hi set value given to the Hi set value input terminal 7 and, when they match, a synchronous R
The Hi signal is sent to the set terminal of the S flip-flop circuit 5. Reference numeral 3 denotes a second comparator, which compares the output value of the counter 1 with the Low set value given to the Low set value input terminal 8 and outputs a Hi signal to the reset terminal of the synchronous RS flip-flop circuit 5 when they match. Is sent. 4 is 3rd
The comparator compares the output value of the counter 1 with the reset set value given to the reset set value input terminal 9 and sends out a Hi signal to the reset terminal of the counter 1 when they match. 5 is a synchronous RS flip-flop circuit,
It operates in synchronization with the original clock input from the original clock input terminal 6, and when Hi is input to the set terminal, Hi
Is set to Low when Hi is input to the reset terminal. Reference numeral 6 denotes a master clock input terminal for inputting a master clock from outside the apparatus. 7 is H
An i setting value input terminal for inputting a Hi setting value from outside the apparatus. Reference numeral 8 denotes a Low setting value input terminal for inputting a Low setting value from outside the apparatus. Reference numeral 9 denotes a reset setting value input terminal for inputting a reset setting value from outside the apparatus. Reference numeral 10 denotes a divided clock output terminal for outputting the output of the synchronous RS flip-flop circuit 5 as a divided clock to the outside of the device.

The operation of the clock frequency divider constructed as described above will be described with reference to the timing chart of FIG. Here, in the present embodiment, the frequency division number is 16 or less, and the counter 1 is a 4-bit binary counter.
In addition, it is assumed that 3 is set for the Hi setting value, 7 is set for the Low setting value, and 12 is set for the reset setting value from outside the apparatus. The source clock 21 is connected to the source clock input terminal 6
This device operates in synchronization with the original clock input from the device. The counter value 22 is the output value of the counter 1. The flip-flop set signal 23 is an output signal of the comparator 2 and is input to the set terminal of the synchronous RS flip-flop circuit 5. The flip-flop preset signal 24 is an output signal of the comparator 3 and is input to a reset terminal of the synchronous RS flip-flop circuit 5. The counter reset signal 25 is an output signal of the comparator 4 and is input to the reset terminal of the counter 1. The divided clock 26 is an output signal of the synchronous RS flip-flop circuit 5 and is output from the divided clock output terminal 10 to the outside of the device.

When the counter reset signal 25 becomes Hi, the counter value 22 is reset to 0 at the next rising edge of the original clock 21, and thereafter, is incremented by one at every rising edge of the original clock 21. The counter value 22 and Hi input from the Hi set value input terminal 7
The comparator 2 compares the set value with the set value. When the set values match, the flip-flop set signal 23 becomes Hi. When the flip-flop set signal 23 becomes Hi, the synchronous RS flip-flop circuit 5 is set to Hi at the next rising edge of the original clock 21, and the frequency-divided clock 26 becomes Hi. The counter value 22 is compared with the Low set value input from the Low set value input terminal 8 by the comparator 3, and when they match, the flip preset signal 24 becomes Hi. When the flip-flop preset signal 24 becomes Hi, the synchronous RS flip-flop circuit 5 is set to Low at the next rising edge of the original clock 21, and the frequency-divided clock 26 becomes Low. The counter value 22 is compared with the reset setting value input from the reset setting value input terminal 9 by the comparator 4, and when they match, the counter reset signal 25 becomes Hi. When the counter reset signal 25 becomes Hi, the counter 1 is reset to 0 at the next rising edge of the original clock 21, and the counter value 22 becomes 0. Thereafter, the above operation is repeated.

As described above, according to the present embodiment, by appropriately setting the reset set value from the reset set value input terminal 9, and by setting the Hi set value input terminal 7 to Hi
By appropriately setting the set value and the Low set value from the Low set value input terminal 8, a divided clock having an arbitrary division number, duty, and phase can be synchronized with the synchronous RS.
It can be output from the flip-flop circuit 5.

In the above embodiment, the frequency division number is one.
Since the number is 6 or less, the counter 1 has 4 bits, but the same clock frequency division can be performed by using a counter having a size corresponding to an arbitrary frequency division number. In the above embodiment, the Hi set value is 3, Low.
Although the set value is set to 7 and the reset set value is set to 12, any value that can be represented by the number of bits of the counter 1 can be set.

[0013]

As described above, according to the present invention,
Since means for setting parameters for determining the frequency division number, duty, and phase are provided, the frequency division number, duty, and phase of the frequency-divided clock with respect to the original clock can be freely set.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock frequency divider according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter 2 1st comparator 3 2nd comparator 4 3rd comparator 5 Synchronous flip-flop circuit 6 Original clock input terminal 7 Hi set value input terminal 8 Low set value input terminal 9 Reset set value input terminal 10-divided clock output pin

Claims (2)

[Claims] 1. A means for setting a parameter for arbitrarily determining a frequency division number, a means for setting a parameter for arbitrarily determining a duty, and a means for setting a parameter for arbitrarily determining a phase And a means for controlling a frequency dividing counter and an output flip-flop according to set parameters, and means for outputting a divided clock corresponding to the set parameters. 2. A counter that operates in synchronization with the original clock and determines the timing of a device that is reset by a reset signal input, and a counter that operates in synchronization with the original clock and Hi is input to the set terminal. A synchronous RS flip-flop circuit that is set to Low when Hi is input to the reset terminal and outputs a frequency-divided clock;
A first comparator for comparing an output value of the counter with a preset Hi set value, and sending a Hi signal to a set terminal of the synchronous RS flip-flop circuit when they match, an output value of the counter; And a preset Low setting value, and when they match, a second signal for sending a Hi signal to the reset terminal of the synchronous RS flip-flop circuit
And a third comparator for comparing the output value of the counter with a preset reset value and sending a Hi signal to a reset terminal of the counter when they match with each other. apparatus.