JPH1013925A - Circuit for changing transmission and reception timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission and reception timing changing circuit which is easy to process and also inexpensive. SOLUTION: This circuit is provided with a transmission and reception timing generating counter 7 which creates transmission and reception timing and a delay counter 5 which outputs a reset signal to the counter 7 at the timing, which is delayed only by a set value from a reference signal that is supplied by a wire network. Then, the circuit inhibits supply of a reset signal to the counter 7, changes oscillation frequency of a master clock generation frequency variable oscillator 4 for a prescribed time, returns it to original frequency, sets a set value of the reset signal whose timing is corrected, which corresponds to a delay time from the reference signal whose supply is resumed in the counter 5, and allows inputting of the reset signal to the counter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for performing wireless communication between a wireless base station and a terminal, in particular, a PHS system, which changes the transmission / reception timing of the wireless base station without disconnecting the line under communication. The present invention relates to a transmission / reception timing change circuit.

[0002]

2. Description of the Related Art As shown in the block diagram of FIG. 4, a system for wireless communication between a wireless base station connected to a wired network and a terminal, such as a PHS system, has a terminal 1a.
1c generally communicates with the transmission / reception timings of the wireless base stations 2a to 2c, respectively. In many cases, the wireless base stations 2a to 2c obtain a reference signal from the wired network 3 connecting the wireless base stations and generate transmission / reception timing of the own station. Further, for the purpose of avoiding interference between the wireless base stations or realizing roaming of the terminals 1a to 1c (maintaining communication even when the terminals 1a to 1c move from a certain area to an adjacent area), the wireless base station It is common practice to synchronize the transmission and reception timing between the stations.

In such a system, some trouble occurs in the wired network 3 connecting the wireless base stations,
For example, when the reference signal supplied to the wireless base station 2a is temporarily interrupted, the wireless base station 2a cannot guarantee synchronization with the other wireless base stations 2b and 2c. When the supply of the signal is restored, it is necessary to resynchronize with the other radio base stations 2b and 2c.

However, at this time, if the transmission / reception timing of the radio base station is rapidly changed to a desired timing, if a terminal communicating with the radio base station exists, the radio base station and the terminal There is a problem that the possibility that the communication between them is cut off is very high.

[0005] Regarding this problem, for example, RCR STD-28, which is a PHS standard, stipulates that the transmission jitter of CS (base station) should be 1/8 symbol or less. That is, if it is possible to change the transmission / reception timing of the radio base station at a speed within the range of this standard, it should be possible to achieve synchronization between radio base stations without disconnecting the line under communication. Conventionally, as means for changing the transmission / reception timing of a radio base station within the range of this standard, a period of a clock (master clock) which is a basic operation of the radio base station is at least 1/8 symbol time or less. There has been a method of shifting the timing of the entire operation of the wireless base station using a clock.

[0006]

However, the above-described method of changing the transmission / reception timing of the radio base station has a disadvantage that a high-speed clock is required and the circuit configuration becomes complicated. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the purpose of the present invention is to make it easy and inexpensive.
An object of the present invention is to provide a structure of a transmission / reception timing change circuit capable of changing transmission / reception timing of a radio base station without interrupting communication between a radio base station and a terminal.

[0008]

In order to achieve the above object, a transmission / reception timing changing circuit according to the present invention is connected to a wired network and performs wireless communication between a terminal and a wireless base station which obtains a reference signal from the wired network. A transmission / reception timing change circuit that corrects a transmission / reception timing shift between the radio base stations due to temporary inability to supply a reference signal in the system, wherein a master clock is supplied from a master clock generation frequency variable oscillator. A transmission / reception timing generation counter for generating transmission / reception timings of a predetermined number of transmission / reception frames, and a master clock supplied from the master clock generation frequency variable oscillator, and delayed by a predetermined set value from a reference signal supplied from the wired network. And a delay counter that outputs a reset signal to the transmission / reception timing generation counter at the timing. The supply of the reset signal to the transmission / reception timing generation counter was prohibited, and after changing the oscillation frequency of the master clock generation frequency variable oscillator for a predetermined time, the oscillation frequency was returned to the original frequency, and the timing was corrected. After setting a set value corresponding to a delay time from a reference signal whose supply has been restarted to the delay counter, input of a reset signal to the transmission / reception timing generation counter is permitted. It is assumed that.

The transmission / reception timing changing circuit according to the present invention has a configuration (variable oscillator for master clock generation, delay counter,
A transmission / reception timing generation counter) is diverted, and a simple circuit for controlling the supply of a reset signal to the transmission / reception timing generation counter is added, and set values are set in these components, or these components are controlled. This is a circuit that changes the transmission / reception timing by changing the software. Therefore, it is not necessary to newly provide a complicated dedicated circuit, and the cost can be reduced. Further, since the transmission / reception timing change operation is realized by software processing, a flexible transmission / reception timing change method can be provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a transmission / reception timing changing circuit according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a transmission / reception timing changing circuit provided in a radio base station. However, only the configuration related to the present invention is illustrated. In the drawing, reference numeral 4 denotes a voltage-controlled type master clock generation frequency variable oscillator (master clock generation VC-TCXO), which is configured to generate a master clock which is a basic of all operations of the radio base station;
A master clock is also supplied to a delay counter and a transmission / reception timing generation counter, which will be described later.

Here, the reason why the variable frequency oscillator is employed for generating the master clock is that the oscillation frequency of the oscillator for generating the master clock provided in each radio base station varies due to the dispersion of components and the like. Since a deviation of the frequency (period) of the master clock between the radio base stations is not allowed, a reference signal is supplied from a wired network, and the frequency (period) of the master clock is adjusted by each radio base station based on the signal. It is necessary.

Next, 5 is a delay counter which determines the amount of delay from the reference signal to the reference point of the transmission / reception timing when generating the transmission / reception timing based on the reference signal supplied from the wired network. The counter value is C
When the value becomes equal to the value set by the PU 6, a reset signal is supplied to the transmission / reception timing generation counter 7 described later. That is, there is a function of setting a reference point (counting start point) of the counter value of the transmission / reception timing generation counter 7 for generating transmission / reception timing, which will be described later, to a time point delayed by a desired value from a reference signal supplied from the wired network. doing.

Further, a transmission / reception timing generation counter 7
Generates a basic count value (transmit / receive frame number) of the transmission / reception timing of the radio base station based on the master clock. The point in time at which the reset signal is supplied from the delay counter 5 is defined as a reference value of the counter value. As a point (counting start point), a predetermined number of transmission / reception frames are generated (output of a predetermined number of transmission / reception frame numbers) during one cycle of the reference signal. 8 is CPU
6, reset signal input control means for controlling the supply of the reset signal to the transmission / reception timing generation counter 7. The CPU 6 is configured to set or control set values for each block described above.

The reset signal input control means 8 includes, for example,
It can be easily realized by a two-input AND gate. That is, the control signal (ON / OFF signal) of the CPU 6 is input to one input of the AND gate, and the reset signal output by the delay counter 5 is input to the other input of the AND gate, and the output of the AND gate is transmitted and received. By outputting the reset signal to the timing generation counter 7, the supply of the reset signal to the transmission / reception timing generation counter 7 can be controlled.

An embodiment of the transmission / reception timing of each block described above will be described with reference to the timing chart of FIG. FIG. 2 shows a state in which the reference signal is supplied from the wired network, and the transmission / reception timing generation counter 7 generates 20 transmission / reception frames (frame numbers 0 to 19) within one cycle of the reference signal. It is a thing.

When the reference signal from the wired network is normally supplied to the radio base station, the reset signal input control means 8
Is controlled by the CPU 6 to permit the supply of the reset signal to the transmission / reception timing generation counter 7, and the delay counter 5 delays the transmission / reception timing generation counter 7 at a timing delayed by a predetermined set value from the rise of the reference signal. To output a reset signal. In synchronization with the reset signal, the transmission / reception timing generation counter 7
Within approximately the same time as one cycle of the reference signal, 20 transmission / reception frames shown in the figure are generated.

Next, it is assumed that the reference signal to be supplied from the wired network is not supplied to the radio base station due to, for example, disconnection of the line of the wired network. In this case, a signal to be used as a reference when counting is not supplied to the delay counter 5, so that the delay counter 5
Stops outputting a reset signal to the transmission / reception timing generation counter 7.

On the other hand, the transmission / reception timing generation counter 7
Means that the counter operation is continued based on the master clock and the generation of the transmission / reception timing is continued even if the reset signal is not supplied, but the transmission / reception timing generation counter 7 generates the transmission / reception timing when the reference signal is not normally supplied. The transmitted / received timing does not guarantee any normal operation.

Thereafter, the transmission / reception timing generation counter 7
Even when the supply of the reference signal to the reference signal is restored, the timing at which the newly supplied reference signal is input is different from the input timing of the reference signal that was supplied before the reference signal was interrupted. In most cases. In this state, if the operation of the wireless base station is continued,
Since no synchronization is obtained with the other radio base stations, the normal operation of the system is hindered. Therefore, it is indispensable to synchronize the transmission / reception timing of the wireless base station, for which the supply of the reference signal has been temporarily interrupted, with the transmission / reception timing of another wireless base station. At this time, if the transmission / reception timing is suddenly changed to a desired position, if there is a terminal communicating with the wireless base station, the communication cannot be continued. . Therefore, in the transmission / reception timing changing circuit of the present invention, the transmission / reception timing is changed by changing the oscillation frequency of the master clock generation frequency variable oscillator 4 by the CPU 6 for a predetermined time.

An embodiment of the operation of the transmission / reception timing changing circuit (transmission / reception timing changing procedure) of the present invention will be described below with reference to the explanatory diagram of FIG. First, a difference (necessary timing correction amount) between the transmission / reception timing of the radio base station (own station) whose transmission / reception timing is changed and the transmission / reception timing of another radio base station (other station) is obtained. For example, a value of a deviation (timing correction amount) of transmission / reception timing of the own station may be obtained from a master base station monitoring radio transmission / reception timings of a plurality of radio base stations via a wired network. May be configured. However, the method for obtaining the timing correction amount is not particularly limited.

Next, the reset signal output from the delay counter 5 to the transmission / reception timing generation counter 7 is stopped by the control of the reset signal input control means 8 (the reason will be described later).

Thereafter, in response to an instruction from the CPU 6, the oscillation frequency of the master clock generation frequency variable oscillator 4 (master clock generation VC-TCXO) is changed for a predetermined time and then returned to the original frequency. Regarding the amount of frequency change in this case, for example, in PHS, the absolute accuracy of the transmission rate is ± 5p in RCRSTD-28 which is a standard.
pm or less, the voltage value applied to the master clock generation frequency variable oscillator 4 is controlled so that a frequency satisfying this is obtained.

Further, when adjusting the transmission / reception timing of the own station to the transmission / reception timing of another station, there are two correction directions, that is, advance or delay of the transmission / reception timing of the own station. The direction in which the frequency of the master clock generation frequency variable oscillator 4 is changed is determined depending on whether the frequency is adopted. That is, when it is desired to advance the transmission / reception timing of the own station, the frequency of the master clock generating frequency variable oscillator 4 is increased, and conversely,
If it is desired to delay the control, the frequency of the master clock generating frequency variable oscillator 4 is controlled to be lowered.

Further, regarding the length of time for changing the frequency of the master clock generating frequency variable oscillator 4,
It can be calculated based on the required amount of timing correction and the allowable frequency accuracy (absolute accuracy of the transmission speed). For example, in a PHS (transmission speed 384 kHz) system,
If you want to correct only one bit time (2.6 μs),
Assuming that the allowable frequency accuracy is 5 ppm, 1 /
By changing the frequency for a time (duration: (384 kHz × 5 ppm) ≒ 520.83 ms), a desired correction can be realized.

Further, at the time when the calculated duration has elapsed, the master clock generating frequency variable oscillator 4
Is returned to the frequency before the change, and the set value of the delay counter 5 is changed to the newly supplied reference signal,
The value is reset to a value corresponding to the time difference from the count reference point (count start point) of the transmission / reception timing generation counter 7.

Finally, the reset signal input control means 8
The control by the PU 6 is performed to restart the supply of the reset signal from the delay counter 5 to the transmission / reception timing generation counter 7. According to the procedure described above, the transmission / reception timing of the radio base station can be changed to a desired timing.

Variable frequency oscillator 4 for generating master clock
The supply of the reset signal to the transmission / reception timing generation counter 7 is stopped during the period from the time when the frequency is changed to the time when the setting of the set value to the delay counter 5 is completed. Is supplied to the transmission / reception timing generation counter 7, the timing correction is canceled each time the reset signal is input, and the transmission / reception timing cannot be changed. For example, when the cycle of the reference signal is shorter than the duration, the reset signal input control means 8 is indispensable in order to prevent the timing correction from being canceled.

[0028]

According to the transmission / reception timing changing circuit of the present invention, the configuration of the frequency variable oscillator or the like provided in the radio base station from the beginning can be used without providing a new complicated dedicated circuit, and the software processing can be performed. By making the change, the transmission / reception timing is changed, so that the cost can be reduced. Further, since the transmission / reception timing change operation is realized by software processing, a flexible transmission / reception timing change method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a transmission / reception timing change circuit of the present invention.

FIG. 2 is a timing chart showing an embodiment of the transmission / reception timing of the transmission / reception timing changing circuit of the present invention.

FIG. 3 is an explanatory diagram for describing an embodiment of an operation (transmission / reception timing change procedure) of the transmission / reception timing change circuit of the present invention.

FIG. 4 is a configuration diagram illustrating a configuration of a system that performs wireless communication between a terminal and a wireless base station connected to a wired network;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Terminal 2 Wireless base station 3 Wired network 4 Variable frequency oscillator for master clock generation 5 Delay counter 6 CPU 7 Transmission / reception timing generation counter 8 Reset signal input control means

Claims (1)

[Claims] 1. A wireless base station connected to a wired network and performing wireless communication between a terminal and a wireless base station that obtains a reference signal from the wired network, the wireless base station being caused by a temporary inability to supply a reference signal. A transmission / reception timing change circuit that corrects a transmission / reception timing shift between the transmission and reception timing generator, the transmission / reception timing generation counter generating a transmission / reception timing of a predetermined number of transmission / reception frames, supplied with a master clock from a master clock generation frequency variable oscillator; A master counter is supplied from the clock variable frequency oscillator, and a delay counter that outputs a reset signal to the transmission / reception timing generation counter at a timing delayed by a predetermined set value from a reference signal supplied from the wired network, Prohibiting the supply of a reset signal to the transmission / reception timing generation counter, After changing the oscillating frequency of the star clock generating variable frequency oscillator for a predetermined time, the oscillating frequency is returned to the original frequency, and the reset signal whose timing is corrected corresponds to a delay time from the reference signal whose supply is resumed. A transmission / reception timing changing circuit configured to permit input of a reset signal to the transmission / reception timing generation counter after setting a set value in the delay counter.