JPH0661807A - Digital duty factor adjustment circuit - Google Patents

Abstract

PURPOSE:To attain a stable operation of the circuit against power supply fluctuation and temperature fluctuation by setting a duty factor through the use of a reference clock and one of N-sets of pulses for duty factor setting purpose. CONSTITUTION:A reference clock CK1 is subject to 1/N frequency-division by a 1/N frequency divider circuit 10 resulting in obtaining an output clock CK2. In this case, an N-phase pulse generating circuit 20 generates N-phase pulses whose phases differ from each other by 1/N each. A toggle circuit 50 is set by a leading edge of the reference clock CK1 and reset one of outputs of the N-phase pulse generating circuit 20 selected by a pulse selection circuit 30 to adjust the duty factor of the output clock CK2 to an optional value through digital setting. Thus, the digital duty factor adjustment circuit operated stably against power supply fluctuation and temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for digitally adjusting a duty factor when an output clock having a predetermined frequency is generated by dividing a reference clock by 1 / N.

In various electronic devices and communication devices, duty factors of signals generally used are specified. However, the duty factor is specified as 50%, and even if the duty factor of the input signal is 50%, the duty factor may be affected by the delay on the signal line, the influence of the setup time / hold time of the gate circuit, the fluctuation of the power supply, etc. May change.

There is a demand for a duty adjusting circuit which stably receives a signal having an arbitrary duty factor and receives such a signal whose duty factor is not constant.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram for explaining a conventional example. The figure is an example of a 1/2 ⁿ divider circuit of a conventional example, which is configured by using n 1/2 divider circuits 111 to 11n.

In the configuration shown in the figure, the reference clock CK1 is divided by ½ by the ½ divider circuits 111 to 11n in sequence, and ½ division is performed n times to obtain 1 of the reference clock CK1. An output clock CK2 having a frequency of / 2 ⁿ is obtained. The duty factor of the output clock CK2 at this time is about 50%.

FIG. 7 shows a diagram for explaining a conventional duty factor adjusting circuit. As shown in FIG. 6, when n half divider circuits are connected and the required output clock CK2 is obtained, the duty factor cannot be adjusted, and the duty factor becomes about 50%. .

Therefore, when a duty factor other than 50% is required, adjustment is performed by the circuit of FIG. 71 and 72 are FF circuits, 73 and 74 are OR circuits, 7
5 is analog unipolar / bipolar
ar hereinafter referred to as U / B) circuit, and 76 is a resistor.

In the figure, the FF circuits 71 and 72 match the phases of the + side NRZ signal and the-side NRZ signal with the clock, and the OR circuits 73 and 74 convert the NRZ signal into an RZ signal and output it. The U / B circuit 75 converts the unipolar signal into a bipolar signal and outputs it.

At this time, if the resistor 76 is not provided, the output pulse is output with a width of approximately a clock. When it is desired to change the pulse width, the output duty factor can be adjusted by changing the voltage applied to the OR circuits 73 and 74 through the resistor 76.

FIG. 8 is a diagram for explaining an example of a conventional multiplexing device. The figure shows the demultiplexer of the multiplexer. Reference numeral 61 is a separation circuit for separating high-order group signals, 62 is a memory for changing clocks with a phase comparator, 63 is a filter for converting the phase comparison result into a control voltage of a voltage controlled oscillator (shown as VCXO in the figure), Reference numeral 64 denotes a voltage controlled oscillator that oscillates at N times the frequency for phase comparison, and 65A converts the frequency of the voltage controlled oscillator to a frequency for phase comparison 1
/ N frequency divider circuit, 66 is a code rule that defines the transmission path, for example, a coder that converts into a B8ZS signal for the primary group signal of North America, 67A is a U / B conversion circuit that converts from a unipolar signal to a bipolar signal. is there.

The U / B conversion circuit 67A shown in FIG.
In the configuration described in Section 1, the unipolar signal is converted into a bipolar signal and the duty factor is adjusted at the same time.

[0012]

In the above-mentioned conventional example, when adjusting the duty factor, the OR circuit 7 is used.
An arbitrary duty factor is set by adjusting the voltage applied to 3, 74 with the resistor 76.

However, this adjustment requires delicate adjustment in the vicinity of the threshold voltages of the OR circuits 73 and 74, and requires a long time work by a skilled worker. Furthermore, since the duty factor is set in the analog circuit, it may fluctuate from the set duty factor due to power supply fluctuations and temperature fluctuations.

The present invention is intended to realize a digital duty factor adjusting circuit capable of digitally setting a duty factor.

[0015]

FIG. 1 is a block diagram for explaining the principle of the present invention. 10 in the figure is a reference clock C
Reference numeral 20 denotes a 1 / N frequency dividing circuit that divides K1 into 1 / N, and 20 generates an N-phase pulse whose frequency is 1 / N of the reference clock CK1 and whose phase is 1 / N different with respect to the reference clock CK1. The N-phase pulse generating circuit 30 is a pulse selecting circuit for selecting one of the N-phase pulses generated by the N-phase pulse generating circuit 20.

Reference numeral 40 is an OR circuit for ORing the reference clock CK1 and the output of the pulse selecting means 30.
Reference numeral 50 is a toggle circuit that performs an inverting operation by the output of the OR circuit 40. An output clock CK2 obtained by dividing the reference clock CK1 by N rises at the rising edge of the reference clock CK1 and falls at the rising edge of the selected N-phase pulse. .

[0017]

The reference clock CK1 is set to 1 by the 1 / N frequency dividing circuit 10.
/ N to generate output clock CK2
The phase pulse generation circuit 20 generates N-phase pulses whose phases differ by 1 / N.

Here, the toggle circuit 50 is set to the reference clock C.
At the rising edge of K1, the pulse selection circuit 30 is turned on.
By turning off one of the outputs of the N-phase pulse generation circuit 20 selected in step 1, the duty factor of the output clock CK2 can be adjusted to an arbitrary value by digital setting.

[0019]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
The figure shows 1.544 from the reference clock of 49, 408 MHz.
This is an example of generating an output clock of MHz.

The 1 / N frequency dividing circuit 10 described in the principle diagram is a 32 frequency dividing circuit here, and an inverter (hereinafter referred to as INV) is used.
110) and 1/2 frequency dividing circuits 111 to 115, and the N-phase pulse generating circuit 20 is composed of OR circuits OR and AN.
An OR circuit 41, which is composed of a D circuit A and serves as an OR circuit,
The toggle circuit is composed of a 1/2 divider circuit 51.

FIG. 3 is a time chart of the embodiment of the present invention. The operation of the embodiment of FIG. 2 will be described with reference to the time chart of FIG. A Reference clock.

This is a clock obtained by inverting the reference clock A in B INV 110. The outputs of the C to G 1/2 frequency dividing circuits 111 to 115 are shown. F1 to F32 are 32 duty factor setting pulses generated from the OR circuit OR. For example, from the first OR circuit OR shown in the figure, the ½ frequency divider circuit 111
Outputs "1" when all the outputs of ~ 115 are "0", and outputs 2
The first OR circuit OR outputs "1" when the output of the 1/2 divider circuit 111 is "1" and the outputs of the 1/2 divider circuits 112 to 115 are "0". By such an operation, 32 outputs from the outputs of the five 1/2 divider circuits 111 to 115 are obtained.
Generate a book pulse.

AND the logical product of this output and the reference clock
The circuit A takes the pulse width and outputs it according to the width of the reference clock. (A) shows the case where the duty factor is 50%.

The 16th pulse F in the pulse selection circuit 30
16 is selected and the logical sum of the reference clock F1 and F
You get 16 '. By operating the 1/2 divider circuit 51 with this signal, a D of 50% duty factor is obtained.
50 is output.

(B) shows the case where the duty factor is the lowest. The selection circuit 30 selects the second pulse F2 and takes the logical sum with the reference clock F1 to obtain F2 '. By operating the 1/2 divider circuit 51 with this signal, the clock Dmin having the lowest duty factor is output.

FIG. 4 is a diagram for explaining another embodiment of the present invention. The figure shows 32 as the 1 / N frequency dividing circuit 10 of the principle diagram.
It is composed of a binary counter 10A and a load value setting circuit 10B.
And a load value setting circuit 20B, and
It is composed of an inverter INV, NOR circuits 42 and 43, an OR circuit 41, and a toggle circuit 51.

In the case where the operation is divided by 32 as in the case of FIG. 2, if the load value of the counter 10A is set to "0" by the load value setting circuit, the counter 10A outputs a carry out every 32 counts, and this carry out Becomes a reference clock divided by 32.

Next, the counter 20A has a counter 10
The carry out output from A is input as a load signal, the load value output from the load value setting circuit 20B is loaded, and then counting is started with the load value as an initial value. . For example, since the counter 20A is a 32-ary counter, loading "31" causes F2 in FIG. 3 to change to "0".
Can be loaded to obtain F32 in FIG.

Then, the reference clock output from the counter 10A and the duty factor setting pulse output from the counter 20A are input to the NOR circuits 42 and 43, respectively, to have a width of one clock, and then input to the OR circuit 41. By operating the toggle circuit 51 with the output, an output clock with an arbitrary duty factor can be generated.

In FIG. 2, 32 pulses for duty factor setting are generated and one of them is selected by the pulse selection circuit 30, but in FIG. 4, it is necessary by the counter 20A. Since only one pulse for setting the duty factor is generated, the pulse selection circuit 30 can be eliminated.

FIG. 5 is a diagram for explaining an example of the multiplexer according to the embodiment of the present invention. Separation circuit 61, memory 62, filter 63, voltage controlled oscillator 64, coder 66 shown in the figure.
Is the same as that described in FIG. In FIG. 5, the 1 / N frequency dividing circuit 65 has the duty factor adjusting circuit described in FIG. 2 built therein, and the U / B converting circuit 67 does not have a duty factor adjusting function. With such a configuration, it becomes possible to easily adjust the duty factor of the output signal of the multiplexer.

[0032]

According to the present invention, the duty factor can be set by a digital circuit by setting the duty factor from one of N pulses for setting the duty factor and the reference clock. ,
The stability with respect to fluctuations in external conditions such as power supply voltage fluctuations and temperature fluctuations becomes high, and it becomes possible to perform duty factor adjustment work and test work in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a diagram for explaining another embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a multiplexer according to an embodiment of the present invention.

FIG. 6 is a block diagram illustrating a conventional example.

FIG. 7 is a diagram illustrating a conventional duty factor adjustment circuit.

FIG. 8 is a diagram illustrating an example of a multiplexing device according to a conventional example.

[Explanation of symbols]

10 1 / N frequency divider circuit 10A, 20A counter 10B, 20B
Load value setting circuit 20 N-phase pulse generation circuit 30 Pulse selection circuit 40 OR circuit 42, 43 NOR circuit 50 Toggle circuit 61 Separation circuit 62 Memory 63 Filter 64 Voltage controlled oscillator 65, 65A 1 / N frequency divider circuit 66 Coder 67, 67A U / B conversion circuit 71, 72 FF circuit 75 Analog U / B circuit 76 Resistor 110, INV inverters 111 to 11n, 51 1/2 divider circuit OR, 41, 73, 74 OR circuit A AND circuit

Claims (2)

[Claims] 1. A circuit for digitally adjusting a duty factor of a clock generation circuit for generating an output clock (CK2) having a predetermined frequency by dividing a reference clock (CK1) into 1 / N. CK1) is divided by 1 / N, and the frequency is 1 / N of the reference clock (CK1) and the phase is different by 1 / N with reference to the reference clock (CK1). N-phase pulse generation circuit for generating N-phase pulse (20)
A pulse selection circuit (30) for selecting one of the N-phase pulses generated by the N-phase pulse generation circuit (20); the reference clock (CK1) and the pulse selection means (3).
0) is provided with a logical sum circuit (40) for taking the logical sum of outputs, and a toggle circuit (50) that performs an inverting operation by the output of the logical sum circuit (40), and the reference clock (CK1) is 1 / An output clock (CK2) divided into N rises at the rising edge of the reference clock (CK1) and falls at the rising edge of a selected N-phase pulse. 2. The digital duty factor adjusting circuit (100) according to the preceding paragraph, wherein the 1 / N frequency dividing circuit (10) comprises a counter (10A) and a load value setting circuit (10B), and the N-phase pulse generation is performed. The circuit is composed of a counter (20A) and a load value control circuit (20B), and an output clock (CK2) obtained by dividing the reference clock (CK1) by 1 / N rises at a carry-out of the counter (10A), A digital duty factor adjusting circuit characterized in that it falls by a carry-out of a counter (20A).