JPS57118426A - Frequency multiplying circuit - Google Patents

Frequency multiplying circuit

Info

Publication number
JPS57118426A
JPS57118426A JP480781A JP480781A JPS57118426A JP S57118426 A JPS57118426 A JP S57118426A JP 480781 A JP480781 A JP 480781A JP 480781 A JP480781 A JP 480781A JP S57118426 A JPS57118426 A JP S57118426A
Authority
JP
Japan
Prior art keywords
signal
terminal
counter
clock
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP480781A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Kihara
Kazuharu Shiragami
Koji Matsushima
Shiro Tsuji
Taiji Shimeki
Misao Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP480781A priority Critical patent/JPS57118426A/en
Publication of JPS57118426A publication Critical patent/JPS57118426A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Abstract

PURPOSE:To receive no limitation of the frequency range and the value of the multiple of an input signal, by detecting the frequency ratio between a digital input signal and a clock signal through a down-counter and using the value of the frequency ration as a dividing ratio of a program counter. CONSTITUTION:A digital input signal Di is supplied to the clear terminal of a flip-flop 21 as well as to the clock terminal of a latch 23. At the same time, a reference clock signal DS of a certain frequency is supplied to the clock terminal of program counters 24 and 25, respectively. The counter 25 delivers a clock signal DS' obtained by applying 1/N to the signal DS by the set value given to the data input terminal from outside by feeding a carry-out signal back to the load terminal. The signal DS' is supplied to the preset terminal of the flip-flop 21 as well as to the clock terminal of a down-counter 22.
JP480781A 1981-01-13 1981-01-13 Frequency multiplying circuit Pending JPS57118426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP480781A JPS57118426A (en) 1981-01-13 1981-01-13 Frequency multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP480781A JPS57118426A (en) 1981-01-13 1981-01-13 Frequency multiplying circuit

Publications (1)

Publication Number Publication Date
JPS57118426A true JPS57118426A (en) 1982-07-23

Family

ID=11594027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP480781A Pending JPS57118426A (en) 1981-01-13 1981-01-13 Frequency multiplying circuit

Country Status (1)

Country Link
JP (1) JPS57118426A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633994B1 (en) 2000-02-22 2003-10-14 International Business Machines Corporation Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105432A (en) * 1979-02-07 1980-08-13 Hitachi Ltd Frequency-voltage converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105432A (en) * 1979-02-07 1980-08-13 Hitachi Ltd Frequency-voltage converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633994B1 (en) 2000-02-22 2003-10-14 International Business Machines Corporation Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds

Similar Documents

Publication Publication Date Title
JPS577634A (en) Frequency dividing circuit
JPS53149076A (en) Digital frequency detecting circuit
JPS57118426A (en) Frequency multiplying circuit
JPS55123239A (en) Programmable divider
JPS5718128A (en) Frequency dividing circuit
JPS54154964A (en) Programable counter
JPS6484333A (en) Divider
JPS57194378A (en) Test circuit of electronic clock
JPS5441060A (en) Multivibrator
JPS523353A (en) Integrated logic circuit
JPS5396657A (en) Digital frequency divider circuit
JPS567527A (en) High speed frequency division circuit
JPS5693424A (en) Pulse generating circuit
JPS55128188A (en) Electronic watch
JPS5386273A (en) Electronic timepiece
JPS5516587A (en) Programmable divider
JPS551703A (en) Programmable pulse generator
JPS5374068A (en) Time control system
JPS5286758A (en) High accurate digital delay circuit
JPS5426772A (en) Operational system
JPS5476266A (en) Electronic watch with alarm function
JPS54109361A (en) Variable-ratio-frequency multiplier circuit
JPS5611440A (en) Exposure time control circuit
JPS547380A (en) Measuring circuit of propagation delay tine
JPS5333626A (en) Cinecamera