JPH0360255A - Selective signal generating circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a ratio counter and to reduce the circuit by using an address of a sine wave ROM so as to generate a ratio for frequency divider ratio change timing. CONSTITUTION:A ratio generating circuit 80 receiving an address of a ROM address counter 62 is inputted is provided to the selection signal generating circuit. The ratio generating circuit 80 receives an address of the ROM address counter 62 being a counter to designate the address of the SIN wave ROM 84 and generates a switch changeover timing accordingly. Thus, the count of the ROM address counter 62 is used as it is to decide the changeover timing of the switch 80 without individual provision of the ratio counter. Thus, no ratio counter is required and the circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a selection signal generation circuit that generates a selection signal in response to dialing of a telephone, and particularly to a selection signal generating circuit that generates a selection signal in response to dialing of a telephone.
MF (Dual Tone Multi Frequency)
ency) Pertaining to something that generates a signal.

[Prior Art] In currently used telephones, there are two types of selection signals: dial pulse signal format and DTMF signal format. For dial pulse signal format,
It is a method that has been used for a long time, and connects the line on and off at predetermined intervals and uses this as a signal. And D.T.
The MF signal format uses operation keys for dialing (1 to
Each key (corresponding to each dial number such as 0) is associated with a combination of two types of specific frequency signals having different frequencies.

In normal cases, a high frequency clock signal output from an oscillator that oscillates a high frequency signal is frequency-divided to create a predetermined frequency signal.

Here, in the current standard, this DTMF signal is
They are created by selecting one each from the low group frequencies (R1-R4) and the high group frequencies (C1-C4) as shown in FIG. That is, 4 rows (R□w), 4 columns (Co 1 u
Each of the 16 signals obtained by the matrix mn) is made to correspond to one operation key.

Then, the signal obtained by frequency division is set to the standard frequency F in the same figure.
s (Hz), the oscillation frequency F of the oscillator
is set to a high frequency of 3.579545 MHz, and this is divided by a predetermined number of stages N.

By such frequency division, it is possible to obtain a signal with a frequency substantially close to the standard frequency Fs, as shown in the figure.

Here, in the figure, ΔF is an error between the standard frequency Fs and the frequency obtained by frequency division, and is calculated by the following equation.

ΔF-((F/N)/Fs) ・100 (%)
) Also, it is better for this error ΔF to be as small as possible, and there is currently a regulation that this error ΔF must be within a range of ±1.5%.

On the other hand, if a DTMF signal is created by directly dividing the signal emitted from a high-frequency oscillator as described above, the number of elements that switch at high frequencies will be extremely large, and the current consumption of the entire circuit will correspondingly increase. turn into. That is, if the cycle counted by a counter or the like becomes smaller, for example, a certain amount of through current will inevitably flow every time the state changes, and the current consumption will increase accordingly. When the current consumption increases, there is a problem in that it becomes difficult to directly supply the power for operating these circuits from the telephone line.

Also, as mentioned above, the error ΔF when frequency division is performed using a 3.579545 MHz oscillator is quite small, but
Errors may be added due to initial errors in the oscillator externally attached to the IC, errors due to aging, and deviations in the oscillation frequency due to temperature changes. Therefore, there is a desire to further reduce the error ΔF.

Therefore, in order to meet such demands, the present applicant proposed a high-precision DT
We proposed a selection signal generation circuit that can obtain an MF signal.

That is, in this proposed circuit, signals obtained by two frequency division ratios are combined and decimal point frequency division is performed to obtain a signal with an accurate frequency.

Here, the proposed selection signal generation circuit will be explained based on FIG. 5. A high frequency pulse signal (for example, 3.579545 MHz) from an oscillation circuit (not shown)
357.9545k obtained by dividing the frequency of the signal by 10
Hz signal) is first input to the ROW frequency division counter 10. This ROW frequency division counter 10 is composed of, for example, five T-type flip-flops, and can count from 0 to 31 (32 pieces).

A signal regarding the count result of the ROW frequency division counter 10 is supplied to the ROW frequency division circuit 12 and the ROW frequency division ratio 2 circuit 14. That is, the ROW frequency division counter 10 can supply 32 signals regarding the count result, but it only needs to be able to output four signals in order to generate the DTMF signal. Therefore, ROW frequency division frequency division diagram 1 circuit 12OW frequency division frequency division ratio 2e circuit 1
Each of the four AND circuits has four AND circuits, one of which is activated by a predetermined count value of the ROW frequency division counter 10.

The timing of output is determined by the DTM corresponding to the operation key.
The ROW frequency division diagram 1 circuit 12 is determined by the frequency division ratio determined according to the F signal and selected by this signal.
is output from one AND circuit of the ROW frequency division frequency division ratio 2-er path 14.

That is, when decimal point frequency division is not performed, one frequency division ratio circuit is provided, and the count value of the frequency division counter 10 is equal to the frequency division ratio N.
When the count value corresponds to , the frequency division ratio circuit becomes active, outputs an output corresponding to this, and resets the frequency division count using this output signal. However,
In this proposed method, in order to perform decimal point frequency division, 1
Change the division ratio within two sine waves. Therefore, two frequency division ratio circuits, a frequency division ratio 1 circuit 12 and a frequency division ratio 2 circuit 14, are provided to output signals with different frequency division ratios, and these are switched.

For example, if the division ratio is 17 and 16, ROW
One AND circuit in the frequency division ratio circuit 12 has a count value of 1.
It is only necessary to set it so that an output is performed at a count value of 7, and one AND circuit of the two ROW frequency division ratio circuits outputs at a count value of 16.

To accomplish such switching, the ROW divider circuit 12 OW divider ratio 2 path 14 is connected to the switch 16 . This switch 16 is for selecting one of the output signals of the ROW frequency division frequency division circuit 12OW frequency division frequency division ratio 2E circuit 14, and sends a signal based on this selection result to the ROM address counter 18. supply

Then, the ROM address counter 18 counts up the signal output from the switch 16 and sends it to S
This is used as an address signal for the IN wave ROM 20. That is, S
The IN wave ROM 20 stores wave height values corresponding to sine waves according to input address values. Therefore, for example, if this peak value is Y-axis data corresponding to 32 X-axis data, 32 digital values of a predetermined sine curve will be output in response to the input signal changing from 0 to 31. I can do it.

The output from this SIN wave ROM 20 is a D/A
The signal is supplied to a (digital-to-analog) converter 22 where it is converted into an analog signal to obtain an alternating current signal for the DTMF signal. The analog output from this D/A converter 22 has a predetermined sine curve, and its frequency is R
OW frequency division Frequency division diagram 1 Circuit 12 is ROW frequency division Frequency division ratio 2E path 1
The frequency is one period when 32 outputs of 4 are obtained. Therefore, by setting the timing at which each of the four AND circuits in the ROW frequency division frequency division diagram 1 circuit 12OW frequency division frequency division ratio 2E circuit 14 is turned on, the signal with the frequency of R1-R4 described above can be obtained. .

Note that the ROW frequency division counter 10 must be reset to 0 when it reaches the desired value, so the switch 1
The output from 6 is fed back and is reset when this output goes high.

On the other hand, the ROW frequency division frequency division diagram 1 circuit 12OW frequency division frequency division ratio 2E path 14 output value is also supplied to the ratio counter 24. This ratio counter 24 is for determining the switching timing of the switch 16, and is composed of four T-type flip-flops capable of counting, for example, 16 pieces. Then, output values of 0 to 15 are supplied to the ROW ratio generation circuit 26.

This ROW ratio generating circuit 26 has four AND circuits, and when the count value of the ratio counter 24 reaches a predetermined value, each corresponding AND circuit outputs a high level. Then, this output signal is supplied to the switch 16,
The switch 16 is switched by this output signal.

In other words, a signal with a predetermined frequency division ratio is output in response to a dialing signal from an operation key, but in this conventional example, when forming one sine wave, the frequency division ratio is switched midway through. . Therefore, although the output sine wave is not a perfect sine wave, since the frequency division ratio can be set to a value with a decimal point, a wave with a very precise frequency can be obtained. For example, if a sine wave is formed from 32 digital data, two of them are divided by a frequency division ratio of 1.
If the remaining 30 pieces of data are configured with a frequency division ratio of 17, the frequency division ratio will be L6.9375. If the frequency division ratio is 1B, 9375, the output frequency can be set to 696.41 for a signal with a frequency of 357.9545kHz, and the error is -0.08
It can be made as small as %. In this way, the signal frequencies for the four DTMF signals can be made very accurate.

[Problems to be Solved by the Invention] As described above, according to the previously proposed selection signal generation circuit,
The division ratio can be determined as a value with a decimal point,
Accurate frequency signals can be obtained.

However, in this circuit, the ratio counter 24
, a new ROW ratio generation circuit 26 is required. In the above explanation, only the ROW side was explained, but in reality, it is also necessary to form four frequency signals on the COLUMN side.

Therefore, it is necessary to provide another set of circuits that are exactly the same as those on the ROW side. Therefore, the ratio counter 24, ROW
Another set of ratio generating circuits 26 is also required. In the circuit configuration of an IC, a flip-flop such as the ratio counter 24 occupies a relatively large area and also consumes a large amount of power. Therefore, there is a desire to reduce the number of counters provided inside the IC as much as possible.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a selection signal generation circuit that can obtain a decimal point frequency divided output with a relatively simple circuit configuration.

Here, circuit design, layout, etc. in the IC are performed for each functional block to improve efficiency. Therefore, a circuit for generating a sine wave and a circuit for frequency division, which have completely different purposes, are designed completely separately. Therefore, it is very difficult to think about sharing circuits between these separate functional blocks. However, in the process of actually manufacturing the proposed selection signal generator, the inventor conducted various studies to improve manufacturing efficiency, and found that the ROM address counter and ratio counter operate equally. This discovery led to the completion of this invention.

[Means for Solving the Problems] The selection signal generation means according to the present invention is a selection signal generation circuit that outputs a selection signal of a corresponding frequency in accordance with an input signal inputted from an operation key, and the selection signal generation means outputs a selection signal of a corresponding frequency. An oscillation circuit that oscillates a signal, a first frequency division circuit that divides the signal from the oscillation circuit at a first frequency division ratio, and a second frequency division circuit that divides the signal from the oscillation circuit at a first frequency division ratio. The second frequency is divided by the frequency ratio.
A switch that selects one of the signals from the frequency divider circuit and the 11th and second frequency divider circuits, and a switch that counts the signals from the switch and resets the count value every time the count value reaches a predetermined value. ROM address counter to
a sine wave ROM that outputs digital data corresponding to a predetermined sine wave according to an address value from a ROM address counter; a key input control circuit that determines a frequency division ratio according to an input signal from an operation key; The present invention is characterized in that it includes a ratio generation circuit that switches the switch at a switching timing corresponding to an address value output from a ROM address counter and a frequency division ratio obtained by a key input control circuit.

[Operation] The selection signal generation circuit according to the present invention has the above-described configuration, and the address value from the ROM address counter is supplied to the ratio generation circuit.

This ratio generating circuit is supplied with a signal regarding switching timing corresponding to the frequency division ratio obtained by the key input control circuit.

Therefore, this ratio generating circuit can generate switching timing using the output from the ROM address counter. Since the switch is changed according to the switching timing of this ratio generating circuit, a ratio counter is not required, the circuit configuration can be simplified, and the efficiency of the entire IC can be improved.

[Embodiment] A selection signal generation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of the embodiment, and an oscillation circuit 50 outputs a pulse signal with a frequency of 3.579545 MHz. The output of this oscillation circuit 50 is divided by 10 by the 10 frequency divider 52, and is 357.9545.
It is converted into a signal with a frequency of kHz.

The output signal from this 10 frequency division circuit 52 is supplied to a frequency division counter 54 (ROW frequency division counter 54a and COL frequency division counter 54b).

Here, since the ROW side and the COL side each have the same configuration, they are denoted by symbols a and b in the figure, and in the following description, they are denoted by symbol a.

b is omitted.

The frequency division counter 54 is the conventional ROW frequency division counter 10.
It has the same configuration as , and consists of five T-type flip-flops. Therefore, the frequency division counter 54 is set to 0 to
It can output 31 signals.

Then, frequency division ratio 1 circuit 56 frequency division ratio 2 circuit 58, switch 60, ROM address counter 62, SIN wave ROM 6
4. The D/A converter 66 includes the ROW frequency division frequency division ratio 1 path 12 OW frequency division frequency division ratio 2 path 14 switch 16, ROM address counter 18, sine wave ROM 20, and D/A converter 66, which are explained in the conventional example. It has the same configuration as the converter 22.

Therefore, it is possible to output a DTMF signal of a predetermined frequency according to the input dialing signal. Note that the dialing signal is input to the key input control circuit 72 when an operation key on the keypad 70 is pressed, and in response to this, R1, R2° R3, R4 and C1, C2, C3, C
A high output is output from one of the signal lines 4, and the corresponding AND circuits of the frequency division ratio 1 circuit 56 and the frequency division ratio 2 circuit 58 are in a state where they can be turned on. And the division ratio is 1
The circuit 56 and the frequency division ratio 2 circuit 58 output a high level when the count value from the frequency division counter 54 reaches a predetermined value, and when this is outputted via the switch 60, the frequency division counter 54 outputs a high level. Perform a reset. Therefore, either one of the frequency division ratio 1 circuit 56 and the frequency division ratio 2 circuit 58 switches the switch 60 at a timing corresponding to a predetermined frequency division ratio.
A pulse signal will be output via the .

Here, the characteristic feature of the present invention is that the ratio generating circuit 80 receives the address value of the address counter 62.
It is to have the following. The ratio generating circuit 80 receives the address value of the ROM address counter 62, which is a counter for specifying the address of the SIN wave ROM 64, and
Create switch switching timing that corresponds to this.

Therefore, according to the present invention, the switching timing of the switch 60 can be determined by directly using the count value of the ROM address counter 62 without providing a separate ratio counter.

Next, the operation will be explained based on FIG. 2.

In this embodiment, in the sine wave ROM 64, 0
A sine wave is formed by 32 digital data of 31 to 31. That is, as shown in FIG. 2(a), it has digital data in the height direction in the figure corresponding to addresses 0 to 31. And this θ~
The address data generation timing for one cycle up to 31 is controlled by the outputs from the frequency division ratio 1 circuit 56 and the frequency division ratio 2 circuit 58.

For example, when performing frequency division to generate the first low group frequency signal (ROWI), the timing of the first two (0°■) is divided by 17, and the timing of the remaining 30 (2 to 31) is divided by 17. The timing is determined by frequency division by 16. In this case, R
In the OW frequency division ratio 1 circuit 56a, the AND circuit corresponding to R1 outputs high when the count value in the ROW frequency division counter 54a reaches 17.
is supplied to the ROM address counter 62 via the ROM address counter 62.

Then, when the count value in the ROM address counter 62 reaches 2 (address value 1), the ROW ratio generating circuit 80a receives the R signal from the keypad 70.
The AND circuit to which the high voltage is supplied is turned on, and the switch 60a is switched by the output from this AND circuit. Then, the output of the ROW frequency division ratio 2 circuit 58a is supplied to the ROM address counter 62a via the switch 60a. Then, this ROW frequency division ratio 2 circuit 58a
In this case, when the output value from the ROW frequency division counter 54a reaches 16, a high output is made.

Therefore, when the switch 60a is switched to the ROW frequency division ratio 2 circuit 58a side, frequency division with a frequency division ratio of 16 is performed.

Therefore, the frequency division ratio of the sine wave output from the sine wave ROM 64a is N-(17x2+16x30)/32-16,0e25, and decimal point frequency division can be performed. According to this frequency division ratio 1B, 0625, the output frequency is 896.41 as shown in FIG. This means that the error ΔF is -0
, 08%, which means that a highly accurate frequency signal can be obtained.

Decimal point frequency division can be performed in the same way for other signals, and the third
As shown in the figure, a signal with a very small frequency division error ΔF can be obtained.

[Effects of the Invention] As described above, according to the selection signal generation circuit according to the present invention, the address value of the sine wave ROM is used to generate the ratio for the frequency division ratio change timing. Therefore, ratio generation can be performed without providing a separate ratio counter, eliminating the need for two counters and significantly reducing the circuit size.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the selection signal generation circuit according to the present invention; FIG. 2 is an explanatory diagram for explaining the frequency division ratio and the configuration of the sine wave in the embodiment; FIG. 4 is a table showing output frequency errors, etc. in the same embodiment, FIG. 4 is a table showing output frequency errors, etc. in the conventional example, and FIG. 5 is a block diagram showing the configuration of the conventional example. 50... Oscillation circuit 54... Frequency division counter 56... Frequency division ratio 1 circuit 58... Frequency division ratio 2 circuit 50... Switch 62... ROM address counter 64...
SIN wave ROM 72... Key input control circuit 80...
Ratio generation circuit

Claims (1)

[Claims] (1) A selection signal generation circuit that outputs a selection signal of a corresponding frequency in response to an input signal input from an operation key, the circuit comprising an oscillation circuit that oscillates a high-frequency pulse signal, and a first input signal from the oscillation circuit. a first frequency divider circuit that divides the frequency at a frequency division ratio of; a second frequency divider circuit that divides the signal from the oscillation circuit at a second frequency division ratio different from the first frequency division ratio; a switch that selects one of the signals from the second frequency divider circuit; a ROM address counter that counts the signals from the switch and resets the count value every time the count value reaches a predetermined value; A sine wave ROM that outputs digital data corresponding to a predetermined sine wave according to an address value from an address counter, a key input control circuit that determines a frequency division ratio according to an input signal from an operation key, and a ROM. A selection signal generation circuit comprising: a ratio generation circuit that switches the switch according to switching timing corresponding to an address value output from an address counter and a frequency division ratio obtained by a key input control circuit.