JP2659361B2 - DTMF type dialer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DTMF dialer that generates a selection number in response to a dial operation of a telephone, and more particularly to a DTMF (Dual Tone Modulated Frequency) signal as a selection signal. About occurrence.

[Conventional technology]

The DTMF type dialer is roughly divided into a selection signal to be transmitted and a DTMF signal type.The DTMF signal type transmits a reference clock signal output from a reference oscillation circuit to an operation key. DTMF signal representing the operation key by changing to match the standardized frequency (standard frequency) for each row and column where it is located, obtaining the frequency signal corresponding to each row and column, and combining them Is what you get.

[Problems to be solved by the invention]

By the way, since such a DTMF dialer is directly supplied with power from a telephone line, it is required to operate with low power consumption and low voltage. 1 to meet such demands
As one means, it has been practiced to suppress the current consumption during operation by suppressing the frequency of the reference oscillation to be low, and to enable low-voltage operation. When a DTMF signal is obtained by such a DTMA-type dialer, means for obtaining a frequency standardized corresponding to an arbitrary key include: (a) As shown in FIG. By alternately switching the dividing ratios N ₁ and N ₂ for each rising or falling step to obtain an integer dividing ratio of 0.5 to the decimal place of 0.5 (b) As shown in FIG. As described above, there is a method of finely adjusting the sine wave frequency by inserting several reference oscillation pulses into the apexes a and b of the simulated sine wave obtained by the frequency division output.

However, in the case of (a), only the frequency division ratio up to 0.5 below the decimal point is obtained, and the frequency deviation from the standard frequency becomes large. In the case of (b), since the frequency is adjusted by adding a pulse to only a part of the sine waveform, the waveform distortion is disadvantageously increased.

Therefore, an object of the present invention is to provide a DTMF-type dialer in which the frequency deviation is suppressed and the accuracy of the DTMF signal is improved.

[Means for solving the problem]

As shown in FIG. 1, the DTMF dialer of the present invention comprises a key input logic circuit (4), an oscillation circuit (8), a first frequency divider (O), and a second frequency divider. (P) and the first
Waveform generation circuit (Q) and second waveform generation circuit (R)
And a selection signal generating circuit (6) having an adder (48), wherein the first frequency dividing circuit (O) includes a first COLUMN frequency dividing counter (12) and a first COLUMN frequency dividing circuit. Ratio memory circuit (16)
A second COLUMN division ratio storage circuit (18), a switch circuit (20), a second COLUMN ratio counter (22), and a third
COLUMN ratio storage circuit (24), and receives a designated signal from the key input logic circuit (4), thereby the first CO
A first column-side integer division ratio from the LUMN division ratio storage circuit (16),
The second column-side integer division ratio is read from the second COLUMN division ratio storage circuit (18), and the third column-side integer division ratio is read from the third COLUMN ratio storage circuit (24). The frequency dividing counter (12) is connected to the first circuit selected by the switch circuit (20).
The reference signal from the oscillation circuit (8) is divided according to the column-side integer division ratio or the second column-side integer division ratio, and the divided output is stored in the first COLUMN division ratio storage circuit (16). ) Or / and the second CO
The second column ratio counter (22) inputs the first column side division ratio or the second column side division ratio output from the switch circuit (20) to the LUMN division ratio storage circuit (18). The frequency is divided, and the frequency-divided output is added to a third COLUMN ratio storage circuit (24).
And the third column-side integer division ratio is added to the switch circuit (20) to select the first column-side integer division ratio or the second column-side integer division ratio. As a result, a high group pulse is generated, and the second frequency dividing circuit (P)
A frequency dividing counter (14) and a first ROW frequency dividing ratio storage circuit (2
8), a second ROW division ratio storage circuit (28), a switch circuit (30), a second ROW ratio counter (32), and a third R
An OW ratio storage circuit (34), and receiving a designation signal from the key input logic circuit (4), thereby causing the first ROW
From the frequency division counter (14), the first row-side integer frequency division ratio, the second
A second row-side integer division ratio from the ROW division ratio storage circuit (28),
The third row-side integer division ratio is read from the third ROW ratio storage circuit (34), and the first ROW division counter (14) reads the first row-side integer selected by the switch circuit (30). The reference signal from the oscillation circuit (8) is divided according to the division ratio or the second row-side integer division ratio, and the divided output is stored in a first ROW division ratio storage circuit (26) and / or The second row ratio counter (32) is input to the second row division ratio storage circuit (28), and the first row-side integer division ratio or the second row side is output from the switch circuit (30). Divides the integer division ratio and outputs the divided output to the third
The third row-side integer division ratio is read out in addition to the ROW ratio storage circuit (34), and the third row-side integer division ratio is added to the switch circuit (30) to obtain the first row-side integer division ratio. Generating a low group pulse by selecting a ratio or a second row-side integer division ratio;
The first waveform generating circuit (Q) receives a high-group pulse from the first frequency dividing circuit (O), generates a first waveform output, and generates a second waveform output.
The waveform generator (R) receives the low-level pulse from the second frequency divider (P) to generate a second waveform output, and the adder (48) outputs the first waveform generator (Q). ) And the second waveform output from the second waveform generation circuit (R) are input, the two are added, and a key input logic circuit (4) is added.
A selection signal representing a number or symbol corresponding to the keyboard (2) input to the keyboard (2) is generated.

[Action]

In the DTMF dialer of the present invention, the reference clock signal is frequency-divided by a frequency frequency dividing means capable of selectively switching a plurality of integer frequency dividing ratios, and the divided output is added to the ratio counting means and counted. An arbitrary integer dividing ratio is selected for the frequency dividing means according to the output, and the decimal point dividing is realized.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a DTMF dialer according to the present invention.

In FIG. 1, a keyboard 2 provided as data input means for selection signal data comprises a numeric keypad and a plurality of symbol keys such as *, #, A, B, C, and D keys which are attached to the keyboard. In this case, the arrangement and the number of keys of the keyboard 2 are constituted by a total of 16 keys in 4 rows and 4 columns.
In the keyboard 2, numeric keys and other keys are used for inputting numerical values such as a destination telephone number and a password. The input data of the operated key is composed of position information COLUMN1,2,2,4 on the horizontal axis and position information ROW1,2,3,4 on the vertical axis of each key, and each position information COLUMN1, 2,
3,4 and ROW1,2,3,4 are applied to the key input logic circuit 4 of the selection signal generation circuit 6.

After the hook switch (HOOK SW) linked to the operation of the handset or the like is turned on, the key input logic circuit 4 specifies the designated signal R ₁ , which is the basis of the DTMF signal representing the operated specific key.
R ₂ , R ₃ , R ₄ , C ₁ , C ₂ , C ₃ , C ₄ and various reset signals RESET, ROW-RESET, COL-RESET are output. It is added to the first frequency dividing circuit O and the second frequency dividing circuit P to be formed.

The selection signal generation circuit 6 includes a key input logic circuit 4, an oscillation circuit 8, a first frequency divider O, a second frequency divider P, a first waveform generator Q, a second waveform generator R, and an adder. 48 and a buffer circuit 50. The clock pulse CP of the reference oscillation frequency fr of the oscillation circuit 8 is divided by a division ratio set based on various signals from the key input logic circuit 4, and the divided output is obtained. Are combined to obtain a DTMF signal as a selection signal corresponding to the operation key.

In the selection signal generating circuit 6, the reference oscillation frequency fr of the oscillation circuit 8 is set by the oscillator 10, and the oscillation operation is reset by the reset signal RESET from the key input logic circuit 4. The clock pulse CP of the reference oscillation frequency fr output from the oscillation circuit 8 is applied to the first COLUMN frequency division counter 12 of the first frequency division circuit O on the high group side in which an integer frequency division ratio can be selected. Similarly, the integer dividing ratio is added to the first ROW dividing counter 14 of the second divider circuit P on the low group side from which the integer dividing ratio can be selected, and the frequency is divided by the selected integer dividing ratio.

The frequency-divided output of the COLUMN frequency division counter 12 together with the COLUMN frequency-division counter 12 constitutes a first group frequency dividing means on the high side.
And the second of the installed COLUMN division ratio memory circuit as storage means _{(C-ROM 1, C-} ROM 2) is added to 16, 18. Each C-ROM ₁ 16, the C-ROM ₂ 18, designating signal as the position data obtained in accordance with the key input logic circuit 4 in the operation key
Added as _{C 1, C 2, C 3} , any of the read signal of C _4, C-ROM ₁ 16 and C-ROM ₂ integral dividing ratio corresponding position data from 18 NC _1, NC ₂ is read . Any one of the division ratios is selected from the read division ratio output by the switch circuit 20 provided as division ratio selection means, and the selected integer division ratio is displayed on the COLUMN division counter 12. The output is applied as a reset input R, and this division ratio output is also applied to a second COLUMN ratio counter 22.

COLUMN ratio counter 22 constitutes a part of a ratio setting means of the dividing ratio, a plurality of minute obtained from C-ROM ₁ 16 and C-ROM ₂ 18 in accordance with the count output of the COLUMN frequency dividing counter 12 The output representing the division ratio, in this embodiment the two division ratios NC ₁ and NC ₂ , is counted, and the counted output together with the COLUMN division counter 12 constitutes a third part of the division ratio ratio setting means. It is added to a COLUMN ratio storage circuit (C-ROM ₃ ) 24 constituting storage means. C-ROM ₃ to 24, designated signal C ₁ as the position data corresponding to the operation key from the key input logic circuit 4, C _2,
C ₃ and C ₄ are applied as read signals. This gives C
-ROM ₃ 24 is the dividing ratio NC ₃ in accordance with the position data from the read, the division ratio NC _3, since added as a switching signal for selecting the division ratio to the switch circuit 20, switch circuit 20 Are alternately switched to the contact x, y side, and the conduction time of each contact x, y side is changed by the ratio NC ₃ , and the two division ratios NC ₁ are supplied to the COLUMN dividing counter 12 and the COLUMN ratio counter 22. , NC ₂ are set alternately and for an arbitrary set period.

On the low group side, the divided output of the ROW dividing counter 14 is stored in the ROW dividing counter 14 together with the ROW dividing counter 14 provided as the first and second storage means constituting the low group side frequency dividing means. the ratio memory circuit _{(R-ROM 1, R-} ROM 2) is added to 26. Each _{R-ROM 1 26, R-} ROM 2 28, those from the key input logic circuit 4 operation designation signal as the position data obtained in accordance with the key _{R 1, R 2, R 3} , any R ₄ It added as a read signal, integral dividing ratio corresponding to the position data from the R-ROM ₁ 26 and _{R-ROM 2 28 NR 1,} NR 2 is read. One of the division ratios is selected from the read division ratio output by the switch circuit 30 provided as division ratio selection means, and the selected integer division ratio is stored in the ROW division counter 14. The indicated output is applied as a reset input R, and this division ratio output is also applied to a second ROW ratio counter 32.

ROW ratio counter 32 constitutes a part of a ratio setting means of the dividing ratio, a plurality of minute obtained from R-ROM ₁ 26 and R-ROM ₂ 28 in accordance with the count output of the ROW frequency dividing counter 14 The output representing the frequency division ratio, in this embodiment the two frequency division ratios NR ₁ and NR ₂ , is counted, and the counted output together with the ROW frequency division counter 14 constitutes a third part of the frequency division ratio ratio setting means. It is added to a ROW ratio storage circuit (R-ROM ₃ ) 34 constituting storage means. The R-ROM ₃ 34, the designation signal R ₁ as position data corresponding to the operation key from the key input logic circuit _{4, R 2, R 3,} R 4 is added as a read signal. Thus, R-ROM ₃ 34
, The frequency division ratio NR ₃ corresponding to the position data is read out, and the frequency division ratio NR ₃ is added to the switch circuit 30 as a switching signal for selecting the frequency division ratio. While switching to the y side alternately, the conduction time of each contact x, y side is changed by the ratio NR ₃ , and the two division ratios NR ₁ and NR ₂ are supplied to the ROW division counter 14 and the ROW ratio counter 32. They are set alternately and for an arbitrary set period.

Then, the high group pulse PH obtained through the switch circuit 20 of the first frequency dividing circuit O is applied to the first waveform generating circuit Q. That is, the high group pulse PH is applied to the COLUMN sine wave counter 36 and counted, and the counted output is applied as a waveform read signal to a COLUMN sine wave storage element (ROM) 38 as waveform storage means. This COLUMN sign wave ROM38
The digital sine wave read from the
The signal is converted into an analog sine wave by an analog converter (DAC) 40. Also, the switch circuit 30 of the second frequency dividing circuit P
The low group pulse PL obtained through the second waveform generating circuit R
Is added to That is, the low group pulse PL is applied to the ROW sine wave counter 42 and counted, and the counted output is applied as a waveform read signal to a ROW sine wave storage element (ROW) 44 as a waveform storage means. The digital sine wave read from the ROW sine wave ROM 44 is converted into an analog sine wave by a digital / analog converter (DAC) 46. The sine wave outputs of the high group and the low group are combined by an adder 48, which is a signal combining means, and represent operation keys.
A DTMF signal is formed. This DTMF signal is sent to the buffer circuit
An output terminal 52 sends out a standard telephone line (not shown) to the exchange via an output terminal 52.

Therefore, in this DTMF type dialer, a plurality of integral dividing ratios selectively switchable frequency component set COLUMN frequency division counter as division means _{12, C-ROM 1 16,} C-ROM 2 1
8, in addition to the reference clock signal CP to the ROW frequency dividing counter _{14, R-ROM 1 26,} R-ROM 2 28 divides, adds the divided output to the switching circuits 20 and 30, these switching circuits 20 and 30 set the frequency division ratio _{NC 1, NC 2, NR 1} , COLUMN ratio counter 22 and C-ROM ₃ 24 of the NR ₂ as a ratio setting means, ROW ratio counter 32 and R-ROM ₃ 34 obtained from these by switching the switch circuit 20 or 30 by the ratio NC _3, NR ₃ obtained from the ratio setting means, COLUMN frequency dividing counter 12 as a frequency dividing unit, C-ROM ₁ 16, C-
ROM ₂ 18, ROW frequency dividing counter _{14, R-ROM 1 26,} R-ROM 2 28
, An arbitrary integer division ratio is selected, and a decimal point division is obtained.

Next, FIG. 2 shows the selection signal generating circuit 6 shown in FIG.
2 shows a specific circuit configuration example of the first half circuit portion of FIG.

(A) Oscillation circuit 8 The oscillation circuit 8 includes a resistor 54 and a capacitor 5 as oscillation elements.
6 and 58, and an oscillator 10 for setting the reference oscillation frequency fr.
Gate conditions are regulated. Therefore, when the reset signal RESET is at a low level (L), the clock pulse CP
And the clock pulses CP,
The inverted clock pulse ▲ ▼ is extracted from the inverter 64.

(B) COLUMN frequency division counter _{12, C-ROM 1 16,} C-ROM 2
18 and a switch circuit 20 The COLUMN frequency dividing counter 12 is composed of T-flip-flop circuits (hereinafter, referred to as T-FF) 66, 68, 70, 72, and a clock pulse CP, A high group pulse PH is applied from the output side of the switch circuit 20 to the reset input R of each of the T-FFs 66, 68, 70, 72, and the inverted output of the previous stage is output as a divided output to the timing input T of the next stage. Has become. And T-FF66, 68, 70,
72 inverted output and non-inverted output Q are respectively C-RO
It is added to the M ₁ 16 and C-ROM ₂ 18. In this embodiment, the C-ROM ₁ 16 is 13 (12) as an integer division ratio, 12 (1
1), 11 (10), stores the 10 (9), also, C-ROM ₂ 18
Have integer division ratios of 12 (11), 11 (10), 10 (9), 9
(8) is stored. The division ratio shown in parentheses indicates an auxiliary division ratio corresponding to the switching of the division ratio.

Then, C-ROM ₁ 16, as shown in FIG. 3, the T-
Non-inverted outputs Q _{1 to} Q ₄ and inverted outputs ₁ to ₄ from FF66, 68, 70, 72 and a designation signal C ₁ from the key input logic circuit 4
NAND of the wire matrix circuit 74 for selecting and -C ₄
Established the circuit 76, 78, 80, 82, to obtain a division ratio output NC ₁ by adding the outputs of the NAND circuits 76-82 to the negative logic OR circuit 84.
Further, C-ROM ₂ 18 also non-inverted output from the T-FF66~72
And Q ₁ to Q ₄ and the inverted output _1-4, the NAND circuit 88, 90, 92, 94 placed against the wire matrix circuit 86 for selecting a designation signal C ₁ -C ₄ from the key input logic circuit 4 , Each NA
The output of the ND circuit 88 to 94 in addition to the negative logic OR circuit 96 to obtain the frequency division ratio output NC _2.

Then, the frequency division ratio outputs NC ₁ and NC ₂ are applied to NAND circuits 98 and 100 of the switch circuit 20 as shown in FIG.
On the D circuit 98 side, the inverted output of the frequency division ratio output NC ₁ and the ratio output NC ₃ from the 24 C-ROMs ₃ by the inverter 102 and the NAND are taken. On the NAND circuit 100 side, the frequency division ratio output NC ₁ is divided. The NAND of the output NC ₂ and the ratio output NC ₃ is taken. As a result, the period of the frequency division ratio NC _1, selected and each division ratio NC ₂ NC _1, NC ₂ is set by the ratio output NC _3. And each NAND circuit 9
The outputs of 8 and 100 are added to a negative logic OR circuit 104 to take a logical sum, and the logical output is a data input D of a D-flip-flop circuit (hereinafter referred to as D-FF) 106. The inverted clock pulse の obtained by the inverter 64 is applied to the clock input CK of the D-FF 106, and the non-inverted output Q established by both inputs is a NAND circuit.
The logical AND with the clock pulse CP obtained from the inverter 62 in addition to 108 is taken. The output of the NAND circuit 108 is applied to the negative logic OR circuit 110, and the logical sum of the reset signal COL-RESET obtained by the key input logic circuit 4 and the inverted reset signal ▲ ▼ is obtained, and the high group pulse PH Is obtained.

Accordingly, in such a COLUMN frequency dividing counter 12 and the switch circuit 20, when the COL ₂ and the frequency division ratio NC ₁ keyboard 2 is selected by the key operation, the oscillation circuit 8 from the key input logic circuit 4 4 The reset signal RESET and the negative logic OR circuit 110 shown in FIG.
Inverted signal of reset signal COL-RESET shown in ▲
When ▼ is added, a clock pulse CP shown in FIG. 4C is output from the inverter 62. As a result, T
The non-inverted output Q ₁ shown in FIG. 4D from −FF66, the non-inverted output Q ₂ shown in FIG. 4E from T-FF68, the non-inverted output Q ₃ shown in FIG. T-FF 72 non-inverted output Q ₄ shown in G of FIG. 4 can be obtained from a given _{C-ROM 1 16, C-} ROM 2
Added to 18. From this _{case, C-ROM 1 16, C} -ROM 2 division ratio obtained from 18 NC _1, NC ₂ and C-ROM ₃ ratio output NC ₃ obtained from 24 side, NAND circuits 98, 100 and the negative Logical OR
The pulse shown at H in FIG. 4 obtained through the circuit 104 is D
Applied to data input D of FF106. And D
-The inverted clock pulse ▲ is applied to the clock input CK of the FF106.
Since ▼ has been added, the D-FF 106 is I in FIG.
A high-group pulse PH shown in FIG. 4J is obtained.

(C) COLUMN ratio counter 22 and C-ROM ₃ 24 COLUMN ratio counter 22 is T- flip-flop circuit is constituted by (hereinafter referred to as T-FF) 112, 114, 116 and 118, the timing of T-FF112 input T The reset signal COL-RESET is applied from the key input logic circuit 4 to the high group pulse PH and the reset input R of each of the T-FFs 112 to 118, so that the inverted output of the previous stage becomes the divided output and the timing of the next stage. The input is T. Then, the inverted output and non-inverting output Q of the T-FF112~118 is added to C-ROM ₃ 24. In this embodiment, C-ROM ₃ 24, the two ROM
Are composed of, and stores the 15,11,9,9 as an integer division ratio NC ₅ with 0,0,0,0 an integer division ratio NC _4.

Then, C-ROM ₃ 24, as shown in FIG. 5, the T-
NAND with respect to the wire matrix circuit 120 for selecting the non-inverted outputs Q _{1 to} Q ₄ and the inverted outputs ₁ to ₄ from the FFs 112, 114, 116, 118 and the designation signals C ₁ to ₄ from the key input logic circuit 4. set up circuit 122, to obtain the ratio output NC ₄ from the output of the NAND circuit 122 via the inverter 124. In addition, the NAND circuits 126, 128, 130, OR
A circuit 131 and a negative logic OR circuit 132 are installed, and each NAND circuit 12
To obtain the ratio output NC ₅ by adding an output of 6-130 negative logic OR circuit 132.

As shown in FIG. 2, each ratio output NC ₄ , NC ₅ is an AND of a logic circuit 134 installed to control the switch circuit 20.
In addition to the circuits 136 and 138, the AND circuit 136 outputs the ratio output
The logical product of NC ₄ and the inverted signal of the high group pulse PH by the inverter 140 is calculated. Similarly, the AND circuit 138 also performs the logical product of the ratio output NC ₅ and the inverted signal of the high group pulse PH by the inverter 140. And the outputs of the AND circuits 136 and 138 are applied to NOR circuits 142 and 144 forming a flip-flop circuit. In this case, the NOR circuit 142 has a reset signal
COL-RESET is added as a gate signal, the ratio output NC ₃ from the NOR circuit 142 is obtained.

Therefore, for example, when COL ₁ is selected by a key operation, the reset input R of each of the T-FFs 112 to 118 includes:
A reset signal COL-RESET shown in FIG.
A high group pulse PH shown in FIG. 6B, which is the same as J in FIG. 4, is applied to the timing input T of the T-FF 112. As a result, the non-inverted outputs Q ₁ , T ₁ shown in FIG.
The non-inverted output Q ₂ shown in FIG.
The non-inverted output Q ₃ shown in FIG. 6E and the non-inverted output Q ₄ shown in FIG. 6F are obtained from the T-FF 118, and these non-inverted outputs Q _{1 to} Q ₄ and inverted outputs ₁ to ₄ are It is added to the C-ROM ₃ 24. Then, C-ROM ₃ of FIG. 6 obtained from 24 G, the ratio output NC ₄ shown in H, NC ₅ and high group pulse PH from the ratio shown in I of FIG. 6 obtained by the logic circuit 134 outputs NC _By means of ₃ , as shown in FIG.
The division ratio of the integers 13 and 12 is set at a fixed ratio.

(D) ROW dividing counter _{14, R-ROM 1 26,} R-ROM 2 28
And the switch circuit 30 ROW dividing counter 14 has T-FFs 146, 148, 150, 152, 154
A clock pulse CP for a timing input T of the T-FF 146 and a low group pulse PL from the output side of the switch circuit 30 for a reset input R of each of the T-FFs 146 to 154.
Is added, and the inverting peripheral force of the preceding stage is used as the frequency dividing output to be the timing input T of the next stage. And T-FF14
Inverting output and non-inverting output Q of 6,148,150,152,154 are respectively added to the _{R-ROM 1 26, R-} ROM 2 28. In this embodiment, the R-ROM ₁ 26 is 23 as integral dividing ratios (22), 21 (20), 19 (18), stores the 16 (15), also in R-ROM ₂ 28 Is 22 (2
1), 20 (19), 18 (17), 17 (16) are stored. The division ratio shown in parentheses indicates an auxiliary division ratio corresponding to the switching of the division ratio.

_{Then, R-ROM 1 26, R} -ROM 2 28 , as shown in FIG. 7, the non-inverting output Q ₁ to Q ₅ and the inverted output ₁ from the T-FF146,148,150,152,154 _5, the NAND circuit 158, 160, 162 and 164 placed against the wire matrix circuit 156 for selecting and designating signal R ₁ to R ₄ from the key input logic circuit 4, the output of each NAND circuit 158 to 164 in addition to the negative logic OR circuit 166 to obtain a frequency division ratio output NR _1. Also, R-ROM ₂ 28
The wire matrix circuit 168 for selecting the non-inverted outputs Q _{1 to} Q ₅ and the inverted outputs ₁ to ₅ from the respective T-FFs 146 to 154 and the designation signals R _{1 to} R ₄ from the key input logic circuit 4 The NAND circuits 170, 172, 174, and 176 are installed, and each NAND circuit 17
The outputs of 0 to 176 are added to the negative logic OR circuit 178 to output the frequency division ratio output NR ₂
Have gained.

Each of the frequency division ratio outputs NR ₁ and NR ₂ is applied to NAND circuits 180 and 182 of the switch circuit 30 as shown in FIG.
The 0 side, the ratio output from the division ratio output NR ₁ and R-ROM ₃ 34 side
The inverted output of the inverter 184 of the NR ₃ and the NAND are obtained, and the NAND circuit 182 obtains the NAND of the frequency division ratio output NR ₂ and the ratio output NR ₃ . As a result, the ratio output N
Selection of the division ratios NR ₁ and NR ₂ by R ₃ and the respective division ratios NR ₁ and N
Period R ₂ is set. Then, the outputs of the NAND circuits 180 and 182 are added to a negative logic OR circuit 186 to take a logical sum,
The logical output is the data input D of D-FF188. The clock input CK of this D-FF188 is connected to the inverter 6
The inverted clock pulse ▲ ▼ obtained by step 4 is applied, and the non-inverted output Q established by both inputs is NA
The logical AND with the clock pulse CP obtained from the inverter 62 by being applied to the ND circuit 190 is obtained. This NAND circuit
The output of 190 is applied to a negative logic OR circuit 192 to perform a NOR operation on the reset signal ROW-RESET obtained by the key input logic circuit 4 and the inverted reset signal ▲ ▼ to obtain a low group pulse PL. Can be

Therefore, in such a configuration of the ROW frequency dividing counter 14 and the switch circuit 30, when the ROW _{1 of the} keyboard 2 and the frequency dividing ratio NR ₁ are selected by the key operation, the key input logic circuit 4 sends the oscillating circuit 8 The reset signal RESET shown in FIG. 8A and the inverted signal of the reset signal ROW-RESET shown in FIG.
When ▼ is added, the inverter 62
The clock pulse CP shown in FIG. As a result, the non-inverted outputs Q ₁ , T ₁ shown in FIG.
Non-inverted output Q ₂ to which the -FF148 shown in E of Figure 8, T-FF150
From the non-inverted output Q ₃ shown in FIG. 8F, the non-inverted output Q ₄ shown in FIG. 8G from the T-FF 152, and the non-inverted output Q ₅ shown in FIG. 8H from the T-FF 154. each output is R-ROM ₁ 26,
It added to R-ROM ₂ 28. In this case, R-ROM ₁ 26, R-
From ROM ₂ division ratio obtained from 28 NR _1, NR ₂ and R-ROM ₃ ratio output NR ₃ obtained from 34 side, first obtained through a NAND circuit 180, 182 and the negative logic OR circuit 186 8 The pulse shown at I in the figure is applied to the data input D of D-FF188.
Since the inverted clock pulse パ ル ス is applied to the clock input CK of the D-FF 188, the D-FF 188 generates the non-inverted output Q shown in J of FIG. The low group pulse PL shown in K is obtained.

(E) ROW ratio counter 32 and R-ROM ₃ 34 ROW ratio counter 32 is T-FF194,196,198 is composed of, T-FF194 low group pulse PL with respect to the timing input T of each T-FF194 , 196, and 198, the reset signal ROW-RESET is applied from the key input logic circuit 4, and the inverted output of the previous stage is the frequency-divided output and is the timing input T of the next stage. And T-FF194-1
Inverting output and non-inverting output Q of 98 is added to the R-ROM ₃ 34. In this embodiment, the R-ROM ₃ 34, as a 0,0,0,0 and integral dividing ratio as an integer division ratio 3,2,3,3
Is stored.

Also, R-ROM ₃ 34, as shown in FIG. 9, the T-FF
Non-inverted outputs Q _{1 to} Q ₃ and inverted outputs ₁ to 194 to 198
₃ and a NAND circuit 202 for the wire matrix circuit 200 for selecting the designated signals R _{1 to} R ₄ from the key input logic circuit 4.
And the ratio output NR ₄ is obtained from the output of the NAND circuit 202 via the inverter 203. Further, the NAND circuits 204, 206 and OR circuit 208 is placed against the wire matrix circuit 200, to obtain the ratio output NR ₅ by adding the outputs of the NAND circuits 204 and 206 to the negative logic OR circuit 210.

Then, the respective ratio outputs NR ₄ and NR ₅ are added to the AND circuits 214 and 216 of the logic circuit 212 installed for controlling the switch circuit 30, as shown in FIG. The logical product of the ratio output NR ₄ and the inverted signal of the low group pulse PL by the inverter 218 is obtained. Similarly, the AND circuit 216 also obtains the logical product of the ratio output NR ₅ and the inverted signal of the low group pulse PL by the inverter 218. The outputs of the AND circuits 214 and 216 are output to NOR circuits 220 and 22 that constitute a flip-flop circuit.
2 has been added. In this case, the NOR circuit 220, the reset signal ROW-RESET is added as a gate signal, the ratio output NR ₃ from the NOR circuit 220 is obtained.

Therefore, for example, when ROW ₁ is selected by a key operation, the reset input R of each of the T-FFs 194 to 198 includes:
A reset signal ROW-RESET shown in FIG.
To the timing input T of the T-FF 194, a low group pulse PL shown in FIG. 10B, which is the same as K in FIG. 8, is applied. As a result, the non-inverted outputs Q ₁ , T ₁ shown in FIG.
Non-inverted output Q ₂ to which the -FF196 shown in D of FIG. 10, T-FF198
From the non-inverting output Q ₃ is obtained as shown in E of FIG. 10, these non-inverted output Q ₁ to Q ₃ and the inverted output _1-3, R-ROM ₃
34 has been added. Then, F of FIG. 10 obtained from the R-ROM ₃ 34, by the ratio output NR _4, NR ₅ and Teigun pulse PL logic circuit 212 from that shown in G, the ratio output NR ₃ shown in H of FIG. 10 As a result, as shown in FIG. 10I, for example, the division ratios of integers 22 and 23 are set alternately.

(F) First waveform generating circuit Q, second waveform generating circuit R, adder 48 and buffer circuit 50 shown in FIG. 1 FIG. 11 shows COLUMN sine wave counter 36, ROW sine wave counter 42, COLUMN sine Wave ROM38, ROW sine wave ROM4
4, a specific circuit configuration example of the DACs 40 and 46, the adder 48, and the buffer circuit 50 is shown.

In FIG. 11, the COLUMN sine wave counter 36 is T-FF
224, 226, 228, 230, 232, T-FF224
The high-group pulse PH obtained by the switch circuit 20 with respect to the timing input T, and the reset signal COL-RESET with respect to the reset input R of each of the T-FFs 224 to 232 are added as the inverted output divided output of the preceding stage. It is the timing input T of the next stage. Then, the inverted outputs ₁ to ₅ of the T-FFs 224 to 232 are output.
Is applied as a read signal to the COLUMN sine wave ROM 38 storing the COLUMN sine wave data. Each inverted output
_{According to 1} to ₅ , the sine wave data D _{0 to} D ₄ read from the COLUMN sine wave ROM 38 are D-FF234, 236, 23
8, 240, and 242 are added as data inputs D. Each D-FF234 ~ 242 has a high group pulse PH
After being inverted via 244, it is applied as clock input C. Therefore, the sine wave data obtained at the non-inverted output Q of each of the D-FFs 234 to 242 is applied to the DAC 40 and converted into a sine wave signal represented by an analog amount.

In the case of this embodiment, the DAC 40 is provided with an analog switch composed of a pair of field effect transistors (FETs) 246 and 248 corresponding to the D-FFs 234 to 242.
Non-inverted outputs Q of D-FF234 to 242 are added to the paired gates. The switching output obtained from the middle point of each of the FETs 246 and 248 is connected to a resistance circuit 254 composed of a plurality of resistors 250 and 252.
In addition to the COLUMN sine wave current i _COL . In this case, the reference voltages V _REF1 and V _REF3 are set from the reference voltage setting circuit 256 shown in FIG.
Further, the resistance circuit 254, and the resistance value of each resistor 250 and R _1, the resistance value of each resistor 252 is set to 2R _1. However, for pre-emphasis correction of COLUMN sine wave,
The resistances of the resistors 250 and 252 of the DAC 46 on the ROW sine wave side are set to be 1.26 times the resistances 250 and 252 of the DAC 40 on the COLUMN side.

The ROW sine wave counter 42, the D-FFs 234 to 242, and the DAC 46 have exactly the same configuration as the circuit on the COLUMN side.

The COLUMN sine wave current i _COL obtained by the DAC 40 and the ROW sine wave current i _ROW obtained by the DAC 46 are combined by an adder 48 formed by coupling current paths, and then constitute a buffer circuit 50. It is applied to the inverting input terminal (-) of the operational amplifier 257. In this case, the operational amplifier 257
A non-inverting input terminal (+) receives a reference voltage V _REF2 from a reference voltage setting circuit 256 shown in FIG. 12, and its output terminal and the inverting input terminal (−) have a feedback circuit formed by a resistor 258. The operational amplifier 257 and the resistor 258 constitute a negative feedback amplifier. Therefore, after the respective sine wave currents i _COL and i _ROW are synthesized by the adder 48, the DTMF signal represented by the analog amount by the buffer circuit 50 is output to the output terminal.
Taken out of 52.

In the case of this embodiment, the reference voltage setting circuit 256
As shown in FIG. 12, a resistor 262 is connected to the emitter side of a transistor 260, resistors 264, 266, and 268 for dividing a diode voltage are connected between the base and emitter of the transistor 260, and the base and collector of the transistor 260 are connected to each other. An FET 272 is connected via a resistor 270 therebetween. Therefore, after the inverted reset signal ▲ ▼ of the reset signal RESET obtained from the key input logic circuit 4 is inverted by the inverter 274,
In addition to the gate of ET272, the reference voltage V _REF1 set from the base of the transistor 260 by the resistor 268, the diode voltage between the base and the emitter of the transistor 260 is divided by the resistors 264 and 266, and the reference voltage V _REF2 ,
The reference voltage V _REF3 is taken out from the emitter of the transistor 260 by being set by the resistor 262.

Therefore, in FIG. 11, the reset signal COL-R shown in FIG.
When ESET or ROW-RESET is applied and the high group pulse PH or the low group pulse PL shown in FIG. 13B is applied to the timing input T of the T-FF224, the timing is shown in FIG. 13C from T-FF224. The non-inverted output Q ₁ , the non-inverted output Q ₂ shown in FIG. 13D from the T-FF226, the non-inverted output Q ₃ shown in FIG. 13E from the T-FF228, and the T-FF 230 shown in FIG. Non-inverting output Q ₄ ,
Non-inverting output Q ₅ of the T-FF232 shown in G of FIG. 13 is obtained. Inverted output ₁ of each of these non-inverted outputs Q _{1 to} Q _5
5 , the digital sine wave data D ₀ , D ₁ ,... Corresponding to the inverted outputs ₁ to ₅ are obtained from the COLUMN sine wave ROM 38 or the ROW sine wave ROM 44 as shown by H, J, J, K and L in FIG. D ₂ , D ₃ and D ₄ are read. These digital sine wave data D _{0 to} D ₄ are applied to the gates of the pair of FETs 246 and 248, so that each digital sine wave data D ₀
Each FET246,248 pair in accordance with the level of to D ₄ are selectively switched, shown from the resistor circuit 254 to the M of FIG. 13 COLUM
N sine wave current i _COL or ROW sine wave current i _ROW is obtained.

The COLUMN sine wave current i _COL and the ROW sine wave current i _ROW are combined and output from the buffer circuit 50 as a DTMF signal.

FIG. 14 shows the positional information COL _{1 to} COL _{4 of the} keyboard 2.
Waveform and COLUMN sine wave signal COLUMN ratio counter output NC ₃ obtained in correspondence with, FIG. 15 waveform and ROW of ROW ratio counter output NR ₃ obtained corresponding to the position information ROW ₁ ~ROW ₄ keyboard 2 Represents a sine wave signal.

In this case, the reference oscillation frequency fr set by the oscillator 10 is
When set to 500 kHz, for the COLUMN sine wave signal shown in FIG. 14A, for the COL ₁ shown in FIG. 14B, the COLUMN frequency dividing counter 12 shows the division ratios 12, 13 and C shown in FIG. CO at COL ₂
LUMN frequency dividing counter 12 has frequency dividing ratios 11, 12 as shown in FIG.
In COL ₃ , the COLUMN dividing counter 12 has a dividing ratio of 10, 11, and in COL ₄ shown in FIG. 14E, the COLUMN dividing counter 12 has a dividing ratio of 9,
10 is set at regular time intervals.

In addition, the ROW sine wave signal shown in FIG.
5 In ROW ₁ shown in B of FIG.
23, in the case of ROW ₂ shown in FIG. 15C, the division ratios 20 and 21 are added to the ROW division counter 14, and in the case of ROW ₃ shown in FIG. 15D, the division ratios 18, 19 and 15 In ROW ₄ shown in FIG. 7E, division ratios 16 and 17 are set in the ROW division counter 14 at fixed time intervals.

Therefore, high frequency group f _COL and Teigun frequency f _ROW becomes ^{_{f COL = 5 × 10 5/}} 32 · N COL ... (1) f ROW = 5 × 10 5/32 · N ROW ... (2). However, 5 × 10 ⁵ is the reference oscillation frequency fr (= 500 kHz
z), N _COL represents the average division ratio set in the COLUMN division counter 12, N _ROW represents the average division ratio set in the ROW division counter 14, and 32 represents the number of steps of the sine wave signal.

The average division ratios N _COL and N _ROW are N _COL = (NC ₁ · n ₁ + NC ₂ · N ₂ ) / 32 ... (3) N _ROW = (NC ₁ · n ₃ + NC ₂ · N ₄ ) / 32 ... (4)

However, NC ₁ and NC ₂ are COLUMN frequency division counters 12
Of _{C-ROM 1 16, C-} ROM 2 18 to indicate the set frequency dividing ratio,
n ₁ and n ₂ indicate the number of appearances in the sine wave-period of NC ₁ and NC ₂ respectively. Similarly, NR _1, NR ₂ each represent the division ratio set in the _{R-ROM 1 26, R-} ROM 2 28 of ROW frequency dividing counter 14, n _3, n ₄ is NR ₁ respectively, NR _The number of occurrences in the sine wave-period of ₂ is shown. As an example, when ROW ₁ is selected, since n ₃ = 12 and n ₄ = 20 from the waveform of B in FIG. 15, N _ROW = (23 × 12 + 22 × 20) /32=22.375 (5) Therefore, f _ROW = 5 × 10 ⁵ /22.375×32=698.32 (Hz) (6)

Table 1 shows the frequency obtained by the calculations according to the equations (1) and (2) and the frequency deviation (%) with respect to the standard frequency.

As is clear from Table 1, the original oscillation frequency (oscillator 10
The reference oscillation frequency fr) is set to a low frequency of 500 kHz, and for COL ₁ to COL ₄ and ROW _{1 to} ROW ₄ , the frequency deviation with respect to each standard frequency can be suppressed to within approximately ± 0.2%. It can be seen that a highly accurate DTMF signal can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the reference clock signal is frequency-divided by the frequency dividing means capable of selectively switching a plurality of integer dividing ratios, and the divided output is added to the ratio counting means for counting. In addition to the frequency divider, an arbitrary integer division ratio is selected according to the count output to realize decimal point division.
Since the signal can be obtained, the frequency deviation of the DTMF signal with respect to the standard frequency can be reduced to about 1/2 compared to the conventional one, and the reference oscillation frequency can be lowered, so that current consumption can be reduced. , Because the dividing error is small,
An oscillator having a relatively large variation such as an inexpensive ceramic oscillator can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a DTMF type dialer of the present invention, FIG. 2 is a block diagram showing a first half circuit portion of a selection signal generation circuit in the DTMF type dialer shown in FIG. 1, and FIG. COLU in the selection signal generation circuit shown in FIG.
FIG. 4 is a circuit diagram showing a specific circuit configuration example of the MN frequency division ratio storage circuit. FIG. 4 shows a COLU in the selection signal generation circuit shown in FIG.
FIG. 5 is a timing chart showing the operation of the MN frequency dividing counter. FIG. 5 shows the COLU in the selection signal generating circuit shown in FIG.
FIG. 6 is a circuit diagram showing a specific example of a circuit configuration of the MN ratio storage circuit. FIG. 6 shows a COLU in the selection signal generation circuit shown in FIG.
FIG. 7 is a timing chart showing the operation of the MN ratio counter. FIG. 7 shows the ROW in the selection signal generation circuit shown in FIG.
FIG. 8 is a circuit diagram showing a specific example of a circuit configuration of the frequency division ratio storage circuit. FIG. 8 is a diagram showing a ROW in the selection signal generation circuit shown in FIG.
FIG. 9 is a timing chart showing the operation of the ratio counter. FIG. 9 is a timing chart showing the ROW in the selection signal generating circuit shown in FIG.
FIG. 10 is a circuit diagram showing a specific example of a circuit configuration of the ratio storage circuit. FIG. 10 is a circuit diagram showing a ROW in the selection signal generation circuit shown in FIG.
FIG. 11 is a timing chart showing the operation of the frequency dividing counter. FIG. 11 is a block diagram showing the latter half circuit portion of the selection signal generation circuit in the DTMF type dialer shown in FIG. 1. FIG. 12 is the generation of the selection signal shown in FIG. FIG. 13 is a circuit diagram showing a reference voltage setting circuit of the latter half circuit portion of the circuit, FIG. 13 is a timing chart showing the operation of the latter half circuit portion of the selection signal generating circuit shown in FIG. 11, FIG. 14 and FIG. 16 and 17 are timing charts showing the overall operation of the selection signal generation circuit shown in FIG. 2 and FIG.
FIG. 4 is a diagram illustrating formation of an MF signal. 2 ... keyboard 4 ... key input logic circuit 6 ... selection signal generation circuit 8 ... oscillation circuit O ... first frequency divider P ... second frequency divider Q ... first waveform generator R: second waveform generation circuit 12: first COLUMN frequency division counter 14: first ROW frequency division counter 16: first COLUMN frequency division ratio storage circuit 18: second COLUMN frequency division Ratio storage circuit 20 First switch circuit 30 Second switch circuit 22 Second COLUMN ratio counter 24 Third COLUMN ratio storage circuit 26 First ROW frequency division ratio storage circuit 28 second ROW ratio storage circuit 32 second ROW ratio counter 34 third ROW ratio storage circuit 48 adder

Claims (1)

(57) [Claims] 1. A key input logic circuit (4), an oscillation circuit (8), a first frequency divider (O), a second frequency divider (P), and a first waveform generator ( Q), a second signal generation circuit (6) having a second waveform generation circuit (R), and an adder (48), wherein the first frequency division circuit (O) includes a first COLUMN division circuit. A frequency counter (12), a first COLUMN frequency division ratio storage circuit (16),
COLUMN frequency division ratio storage circuit (18) and switch circuit (20)
A second COLUMN ratio counter (22) and a third COLUMN
A key input logic circuit (4) having a ratio storage circuit (24);
From the first COLUMN frequency division ratio storage circuit (16), the first column-side integer frequency division ratio and the second CO
The second column-side integer division ratio from the LUMN division ratio storage circuit (18),
The third column-side integer division ratio is read from the third COLUMN ratio storage circuit (24), and the first COLUMN division counter (12)
The reference signal from the oscillation circuit (8) is divided according to the first column-side integer division ratio or the second column-side integer division ratio selected by the switch circuit (20), and the divided output is output. First
The COLUMN frequency division ratio storage circuit (16) or / and the second COLUMN frequency division ratio storage circuit (18) are input to the second COLUMN ratio counter (22). The column-side division ratio or the second column-side division ratio is divided, the divided output is applied to a third COLUMN ratio storage circuit (24), and a third column-side integer division ratio is read out. A high-group pulse is generated by adding the third column-side integer division ratio to the switch circuit (20) and selecting the first column-side integer division ratio or the second column-side integer division ratio. The second frequency dividing circuit (P) includes a first ROM frequency dividing counter (1
4), a first ROW division ratio storage circuit (28), and a second ROW
The dividing ratio storage circuit (28), the switch circuit (30), and the second
ROW ratio counter (32) and a third ROW ratio storage circuit (34), and receives a designated signal from the key input logic circuit (4) to generate a first ROW division counter (14).
From the first row-side integer division ratio, from the second ROW division ratio storage circuit (28) to the second row-side integer division ratio, and from the third ROW ratio storage circuit (34) to the third row side. Read out the integer division ratio,
The ROW frequency dividing counter (14) of the first embodiment outputs a reference signal from the oscillation circuit (8) according to the first row-side integer division ratio or the second row-side integer division ratio selected by the switch circuit (30). And the divided output is input to the first ROW division ratio storage circuit (26) and / or the second ROW division ratio storage circuit (28), and the second ROW ratio counter (32) Divides the first row-side integer division ratio or the second row-side integer division ratio output from the switch circuit (30) and stores the divided output in the third ROW ratio storage circuit (34). In addition, a third row-side integer division ratio is read out, and the third row-side integer division ratio is added to the switch circuit (30) to add the first row-side integer division ratio or the second row-side integer division ratio. The first waveform generating circuit (Q) receives the high-group pulse from the first frequency dividing circuit (O) to generate a first waveform output by selecting a frequency ratio. The first The waveform generating circuit (R) receives the low group pulse from the second frequency dividing circuit (P) to generate a second waveform output, and the adder (48) outputs the first waveform generating circuit (Q). First from
And the second waveform output from the second waveform generation circuit (R) are input, the two are added, and the number corresponding to the keyboard (2) input to the key input logic circuit (4) or A DTMF dialer that generates a selection signal representing a symbol.