JP2874415B2 - Digital-to-analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a conversion error correction circuit.

[0002]

2. Description of the Related Art A high-precision digital-to-analog converter (hereinafter referred to as D) adapted to a mixed analog / digital system such as a digital audio system and a precision measurement system.
AC) is commercially available and widely used. These DA
Among the C, DACs incorporated in products for general consumers, such as those for digital audio systems, are subject to great restrictions on product prices and are required to be monolithic. However I
Despite rapid advances in C-related technology, the number of bits per sample value of a digital input signal that can be converted by a conventional monolithic DAC (hereinafter, referred to as D / A conversion accuracy or conversion accuracy) is about 10 bits. Achieving the conversion accuracy has depended on a process that requires individual processing for each semiconductor IC chip, such as laser trimming of a resistance region, which is a component element of the DAC. Therefore, restrictions on productivity are great. In addition, it is inevitable that the precision of the components of the IC chip to be trimmed is deteriorated due to aging. Therefore, even if various processing conditions are optimally selected, the upper limit of the precision is considered to be about 14 bits.

[0003] As means for breaking this upper limit, Maio,
K etc. are "Untrimmed DAC with 14
b Resolution ”(ISSC
CDIGEST OF TECHNICAL PAPE
RS, P24-P25; 1981) proposed a high-precision DAC whose precision was increased to 14 bits without depending on the trimming. "Self-correction method" (Self
The DAC according to the proposed method, also referred to as “compensation technique”, includes a main DAC unit for performing D / A conversion of a digital input signal of 14 bits per sample value, and a DA conversion error generated in a portion corresponding to the upper 5 bits of the main DAC unit. That is, an auxiliary DAC unit for correcting a linearity error is included. The D / A conversion error generated by the main DAC unit is measured in advance and stored in a DAC built-in memory, and a read output from the memory is added to the D / A conversion output of the main DAC unit in reverse polarity by an auxiliary DAC unit. The DA conversion error is canceled. The method according to this proposal is effective for DA conversion error correction, and tends to be widely adopted.

[0004]

The linearity error correction according to the prior art involves reading data from the built-in memory for canceling the conversion error in the auxiliary DAC unit, so that the response speed of the DAC as a whole is slow. Even the DAC with the shortest response time among the DACs of this type that have been marketed so far is only 1.2 μS. About 0.5 μS, which is about half of the response time, is occupied by the data read time from the memory. Even with such a long response time, a DAC that handles a digital signal having a relatively small bit rate, such as a DAC for a digital audio system, does not cause any practical problem. However, high definition television (High Definition Telev)
In a DAC that handles an image signal such as HDTV (i.e., HDTV), the bit rate of an input signal exceeds 50 MHz. In order to respond to such an input digital signal having a high bit rate, it is necessary to reduce the response time to 20 ns or less and the memory read time to 10 ns or less, and particularly to minimize the influence of the memory read time.

Accordingly, it is an object of the present invention to provide a high-accuracy high-speed DAC in which the influence of the read time of a built-in memory storing conversion error data is substantially eliminated.

[0006]

The DAC according to the present invention comprises:
DA of input digital signal supplied in bit parallel
A main DAC unit for performing conversion, and a DA generated between an input digital signal and an output of the main DAC unit accompanying the DA conversion.
An auxiliary DAC for correcting the conversion error, a storage circuit for storing error data corresponding to the previously detected DA conversion error, and the error data read from the storage circuit being output to the output terminal in bit parallel fashion A register circuit for output, and the output of the register circuit in response to a predetermined upper bit of each of a series of digital codewords forming the input digital signal.
Matrix switch means for supplying to the AC unit,
A DA conversion output in which the D / A conversion error is eliminated is generated.

[0007]

1 and 2 show a DAC according to a first embodiment of the present invention. This DAC 100 is connected to a first power supply terminal 5 connected to a power supply of a voltage _Vcc , and to a ground power supply. that a second power supply terminal 6, an input terminal 147 to 152 for receiving a supply of 6 bits (D ₀ ~D ₅₎ codeword input digital signal in bit parallel as a string of these 6 bits (D ₀ to D ₅ ), The input terminals 147 and 148 receive the input of the upper two bits D ₅ and D _4.
, A first latch circuit group 171 including latch circuits 136 to 138 connected to the output of the decoder 135, and the 6 bits (D ₀ to D ₀ ).
D ₅ ), a second latch circuit group 17 composed of latch circuits 139 to 143 connected to input terminals 149 to 152 receiving the lower 4 bits (D _{3 to} D ₀ ), respectively.
And 2.

The DAC further includes a control signal generating circuit 12 connected to a control signal input terminal 16 for receiving a control signal φ ₀ , and a power switch (not shown).
A reset signal generating circuit 11 which receives an output of a power-on-clear circuit 50 which generates a clear pulse in response to the application of _Vcc accompanying the output signal through an output terminal 53 and an input terminal 15;
Output signal T _R and the control signal generating circuit 1 of the circuit 11
A pulse counter 13, an input signal one of the output signals phi ₂ of 2 a pair of digital output signals A ₁ and A ₀ of the counter 13 as an input signal generates a stop signal T _S of the control signal generating circuit 12 and the counter 13 And a data transfer control circuit 10 having a set signal generation circuit 14 for performing the operation.

This DAC further uses an EPROM 17 having a 16-bit storage capacity using 2-bit parallel output signals (A ₁ , A ₀ ) from the counter 13 as address signals.
When, with the register 20-23 to hold the four digital code words of the parallel 4-bit control signal output or a parallel 4-bit code words of EPROM17 in response to the output signal phi ₁ from the generator 12 (E ₀ ~ E
A register circuit 18 which captures the _3), the semiconductor switch 24 to which is controlled by the upper two bits D ₅ and D ₄
And a matrix switch circuit 19 for selecting output signals (R _{00 to} R ₃₃ ) of the register circuit 18 by these semiconductor switches 24 to 27 to output the selected code signals (S _{0 to} S ₃ ). This semiconductor switch 24
For example, 1-4 selectors can be used as -27. The number of bits of the code word per sample value of the input digital signal in this embodiment and the number of bits of the "high-order bit" are assumed for the sake of explanation. For a practical product, the former is 14 bits. To about 16 and the latter to about 5.

[0010] Referring also to FIG.
The AC unit 155 includes the main DAC unit 153 and the auxiliary DAC unit 1
54. Switch element 11 of main DAC section 153
Reference numerals 2 to 118 denote control signals (S _{4 to} S ₁₀ ) from the first and second latch circuit groups 171 and 172 (FIG. 2).
The N / OFF control is performed, and the switch elements 119 to 122 of the auxiliary DAC unit 154
It is controlled by control signals (S _{0 to} S ₃ ) from FIG.

Referring to FIG. 3, main DAC section 153 includes resistance elements 123, 124, 12 having a resistance value R, respectively.
6, 128, 130, and 131 and resistance elements 125, 127, and 129 each having a resistance value of 2R are connected in a ladder shape, and among these resistance elements, resistance elements 123, 12
5, 174, 129 and 131 each having one end connected to power supply terminal 132 of voltage _Vcc.
And the first and second latch circuit groups 171 and 1
72 (FIG. 2), each bit (S ₄ -S
_The movable contact is connected to each of the constant current sources 101 to 107 having the current value I, one of the fixed contacts is connected to the power supply terminal 132 and the other is connected to the resistance element group 174.
Switch elements 112 to 118 respectively connected to the connection points of the resistance elements.

On the other hand, the auxiliary DAC unit 154 is turned on / off in response to the bit-parallel code words (S _{0 to} S ₃ ) of the matrix switch circuit 19 (FIG. 2), and the movable contact has the current value I. Are connected to the constant current sources 108 and 109, and the constant current sources 110 and 111 having the current values I / 2 and I / 4, respectively. One of the fixed contacts is connected to the power supply terminal 132 and the other is connected to the contact of the resistance element group 174, respectively. Switch elements 119 to 132 provided.

The DA conversion output terminal 13 connected to the connection point between the resistance element 123 and the resistance element 124 connected in series
3 is an output terminal of the DAC unit 155, that is,
00 output terminals are formed.

Referring to FIG. 4 showing that each of the switch elements 112 to 122 is formed on a common IC chip with other constituent elements, the switch element 112 illustrated in FIG. 4 has an emitter-coupled logic (ECL). circuit)
It has connected bipolar transistors T1 and T2. The collector of the transistor T1 is connected to the power terminal 132,
Base connected to the output signal S ₁₀ of the first latch circuit group 171, the collector of the transistor T2 to the DA conversion output terminal 133, the base is connected to the reference potential V _REF. The emitters of these transistors T1 and T2 are commonly connected to a constant current source 101. This circuit configuration of the switch element 112 is different from that of the other switch element 1.
13 to 122 are common. Points (A), (B) and (C) on the circuit of FIG. 3 are points (A) and (B) of FIG.
And (C) respectively.

Referring now to FIG. 5, EPROM 17 stores codewords (A ₁ , A ₁ ) from counter 13 (FIG. 2).
A ₀ ) and a decoder 241 for decoding the address (0,
A memory cell array 240 having a capacity of 4 × 4 bits ranging from (0) to (3,3) is provided (in the figure, the memory addresses (x, y) are P _xy and are indicated as P _{00 to} P ₃₃ . .).

When the input codeword (A ₁ , A ₀ ) is (0, ₀ ), the decoder 241 operates the memory cell array 2
Select column 0 of 40 _{(P 00, P 10, P} 20, P 30), the codeword (A _1, A ₀₎ is (0,1), (1, 0) and (1, 1) When the first column (P ₀₁ , P ₁₁ , P ₂₁ , P
_31), selects the second column _{(P 02, P 12, P} 22, P 32) and third column _{(P 03, P 13, P} 23, P 33) , respectively. The EPROM 17 outputs read outputs (E _{0 to} E ₃ ) from the 0th row to the 3rd row. The register circuit each comprising a register 20 to 23 4-bit configuration 18 and the codeword _{(R 00, R 01, R} 02, R 03) register 20 consisting of D flip-flop (DFF) 200 to 203 for outputting , the codeword _{(R 10, R 11, R} 12, R 13) register 21 consisting DFF210~213 for outputting,
D for outputting the codeword _{(R 20, R 21, R} 22, R 23)
A register 22 consisting of FF220～223, and outputs a codeword _{(R 30, R 31, R} 32, R 33) DFF23
0 to 233.

[0017] Referring next to also to FIG. 6, the power supply voltage V _cc applied between the power supply terminals 51 and 52 and between the power-on clear circuit 50 of the power supply terminals 5 and 6 of DAC100 this embodiment 0 period in the range of V ₁ volt, since the output signal of the power-on clear circuit 50 is at the low level potential (hereinafter "0" to), the output signal T _R of the reset signal generating circuit 11 becomes "0". Therefore, control signal generating circuit 12 and counter 13 are in the reset state, and signals A ₀ , A ₁ , φ ₁ and φ ₂ remain at “0”, respectively. Similarly, set signal generation circuit 1
The output signal T _S of 4 also remains at "0".

[0018] power supply voltage V _cc at a time t ₁ reaches V ₁ volt to the output terminal 53 of the power-on clear circuit 50 (hereinafter referred to "1") high-level potential is output, this signal is a reset signal generator output signal T _R of the input to the input terminal 15 of the circuit 11 a reset signal generation circuit 11 releases the reset of the "1" and the counter 13. First
T when the control signal φ ₀ to the input terminal 16 of the
_{At 2} , the control signal generation circuit 12 and the counter 13 start operating. The counter 13 counts up at the falling edge of the output signal φ ₂ of the control signal generating circuit 12, so that the output code words (A ₀ , A ₁ ) of the counter 13 are at times t ₂ , t ₄ , t as shown in Table 1. changes at ₆ and t _8.
The output code words (A ₀ , A ₁ ) are stored in the EPROM 17
Is supplied as an address signal.

[0019]

[Table 1]

In response to the address signals (A ₁ , A ₀ ), the decoder 241 of the EPROM 17 selects one of the 0th to 3rd columns of the memory cell array 240. That column 0 at time _{t 2 (P 00, P 10} , P 20, P 30) to select the time t _4, t ₆ and t ₈ in the first column (P _01, P _11,
P _21, P _31), selects the second column _{(P 02, P 12, P} 22, P 32) and third column _{(P 03, P 13, P} 23, P 33) , respectively. Outputs 4 bits from the 0th row of the selected column to the third row as the conversion error corresponding correction data (E ₀ to E _3).

The 4-bit correction data of the EPROM 17 is stored in the registers 20 to 23 in synchronization with the fall of the output signal φ ₁ of the control signal generation circuit 12. EPROM1
7 in response to the address signals (A ₁ , A ₀ )
The timing at which the correction data is output from 17 and the time at which the correction data is transferred to the register circuit 18 are as shown in Table 2.

[0022]

[Table 2]

Next, referring to FIGS. 7 to 11, the correction data stored in the EPROM 17 is P ₀₀ =
1, P ₁₀ = 1, P ₂₀ = 0, P ₃₀ = 1, P ₀₁ = 0, P ₁₁ =
0, P ₂₁ = 1, P ₃₁ = 1, P ₀₂ = 0, P ₁₂ = 1, P ₂₂ =
1, P ₃₂ = 1, P ₀₃ = 1, P ₁₃ = 1, P ₂₃ = 1, P ₃₃ =
Assume that a 1, period register circuit leading to time t ₁ 18 The data stored in the DFF200~233 does not work remains undefined.

When the time t ₂ is reached, the control signal generation circuit 12
Starts operation, but the control signal φ ₁ , which is its output, remains at “1”.
The codeword stored in 00-233 remains undefined. To the control signal phi ₁ is falling time t _3, EPROM17 output codeword (E ₀ ~E ₃₎
Is taken in by the register circuit 18. At the time t ₃ EPRO
Since the input address (A ₁ , A ₀ ) of M17 is (0, 0), the 0th column of the memory cell array 240 is selected. Therefore, the output codeword (E
₀ , E ₁ , E ₂ , E ₃ ) are ( ₁ , ₁ , ₀ , ₁ ) and D
FFs 203, 213, 223 and 233 have binary values of 1,
1, 0 and 1 are transferred and held, respectively (FIG. 8). At time t ₄ the control signal phi ₂ is falling, EPR
The address input (A ₁ , A ₀ ) of the OM 17 changes to (0, 1). Therefore, the first column of the memory cell array 240 is selected and the output codewords (E ₀ , E ₁ , E ₂ ,
E ₃ ) becomes (0, 0, 1, 1). At time t ₅ and the control signal phi ₁ is falling, DFF203,213,223
And 233 are stored in the DFFs 202 and 21 of the next stage.
EPRO shifted to 2,222 and 232 respectively
The codeword (0, 0, 1, 1) from the first column (corresponding to address (0, 1)) of M17 is
13, 223 and 233 are stored instead. Similarly, at time t ₆ , the address (A ₁ , A ₀ ) to the EPROM 17 becomes (1, 0), the second column corresponding to the address is selected, and the code word ( ₀ , ₁ , ₁ , 1) is output. Is done. At time t ₇ , the storage bits of the DFFs 203, 213, 223, and 233 are stored in the DFFs 202, 212,
DFFs 203 and 21 are shifted to 222 and 232, respectively.
The codewords (0, 1, 1, 1) from the EPROM 17 are transferred and held in 3, 223 and 233 (FIG. 10).

In this way, the correction data is successively transferred to the register circuit 18 and held. The time t at which the input address (A ₁ , A ₀ ) to the EPROM 17 becomes (1, 1)
₈ last third column of memory cell array 240 is selected, the output code word of the column (1, 1, 1, 1) is transferred to the register circuit 18 at time t ₉ is held. As a result, all the contents stored in the EPROM 17 have been transferred to the register circuit 18 (FIG. 11). Becomes a time t ₁₀ the set signal generation circuit 14 sets the signal "1" from the output counter 13, and a control signal generating circuit 12 stops the respective operations.

[0026] All of the correction data stored in the above as EPROM17 is transferred during the period from _the power supply voltage V _cc is 0 volt to stand amounts to DA conversion operation start point corresponding V _c bolt in the register 18 is retained .

[0027] DA to power supply voltage V _cc by turning on the power switch has been completed as forward described above from EPROM17 the transient rise in V _c from V ₁ to the register circuit 18
C100 is a parallel 6-bit input digital signal (D
_{0 to} D ₅ ) are ready for DA conversion.

Decoder 1 which receives the upper two bits D ₅ and D ₄ of these parallel 6 bits (D _{0 to} D ₅ )
35 latch circuit decoding outputs (0,0,0) when the code word (D _5, D ₄₎ is (0, 0) 136-13
8 Similarly codeword (D _5, D ₄₎ is (0,1), (1,0) and (1,1) decoding output to the latch circuit 136 to 138 when the (0,0,1),
(0,1,1) and (1,1,1) are output, respectively. By converting the upper two bits of the input digital signal into three bits as described above, the accuracy of correcting the linearity error can be improved.

Referring back to FIG. 3, the main DAC unit 1
53 and the switch elements 112 to of the auxiliary DAC section 154.
122 is a first and second latch circuit group 171 and 1
72 from the parallel 7-bit codeword (S _{4 to} S
₁₀ ) and the code words (S _{0 to} S ₃ ) of the parallel 4-bit correction data from the matrix switch circuit 19
Receive the supply of each. These codewords (S ₀ to
When all bits of S ₁₀ ) are “1”, the constant current source 1
Numerals 01 to 111 are connected to a power supply terminal 132 maintained at a voltage _Vcc (in FIG. 3, the movable contacts in the switch elements 112 to 122 are tilted to the right). Work to guide each.
On the other hand, when all the bits of the code word (S _{0 to} S ₁₀ ) are 0, the constant current sources 101 to 111 are connected to the resistance element group 1
3 (in a state where the movable contact is tilted to the left in FIG. 3), and the power supply terminal 13 is connected via the resistance element group 174.
2 to conduct current to ground potential. In response to the digital amount represented by the input digital signal of the parallel 6 bits (D _{0 to} D ₅ ), the code word (S ₀ to
Every time each bit of S ₁₀ ) takes a value of “0” or “1”, the amount of current guided from the constant current sources 101 to 111 to the ground potential changes, and the change in the amount of current is caused by the voltage drop by the resistance element group 174. And the analog value V _OUT corresponding to the code word (S _{0 to} S ₁₀ ) is changed to the power supply terminal 132 and the DA conversion output terminal 1
Generated during 33.

The relationship between the codewords (S _{0 to} S ₁₀ ) and the DA conversion output V _OUT will be described in more detail. First, among the switch elements 112 to 118 of the main DAC unit 153 in response to the code word. When only a specific one is connected to the resistance element group 174 and only the constant current source corresponding to the specific one draws the current I to the ground potential, the resistance element group 174
Of the current flowing through the resistance element 123 is determined. Assuming that the specific switch element is the switch element 112, only the constant current source 101 draws the current I to the ground potential via the resistor element group 174. Resistance element 1 of resistance element group 174
Since the combined resistance value of 24 to 131 is 2R, the resistance element 1
The current shunts at the resistance ratio of the above-described combined resistance value 2R of the resistance value of 23, and the current I ₀ flowing through the resistance element 123 is calculated as 2I / 3. Similarly, only switch element 113 is ON
Becomes, the current I ₀ flowing through the resistance element 123 becomes 2I /
3 is calculated. Hereinafter, the switching elements 114, 115, 1
Currents I ₀ flowing through resistance elements 123 corresponding to ON states of only 17 and 118 are 2I /
3, (1/2) · (2I / 3), (1/2) ² · (2I
/ 3), (1/2) ³ · (2I / 3), (1/2) ⁴ ·
(2I / 3) can be calculated. The current I ₀ flowing through the resistance element 123 is equal to the switch elements 112 to 118 calculated above.
Can be calculated based on the principle of superposition.

The maximum value of the current I ₀ flowing through the resistive element 123, a current value of the state where all falls down to the right in FIG. 3 of the movable contact of the switch elements 112-118, the value

[0032]

## EQU1 ##

Further minimum value a current value of the state where all of the movable contacts of the switch elements 112-118 has fallen to the left in Figure 3 of the current I ₀ flowing through the resistive element 123 is 0
It is. Furthermore, the minimum step width of the current I ₀ is determined by ON / OFF of the switch element 118, and its value is (1/1).
2) It becomes ⁴ · (2I / 3). The product of the current value calculated above and the resistance value R of the resistance element 123 gives the DA conversion output voltage V _OUT .

The parallel 6-bit digital input code words (D ₅ , D ₄ , D ₃ , D ₂ , D ₁ , D ₀ ) are (0,
1, 0, 1, 0, 1) as an example.
The operation of No. 3 will be described in more detail. With this codeword input, the upper two bits (D ₅ , D ₄ ) = (0, 1) are input to the decoder 135. The decoder 135 latches each bit of the 3-bit parallel code (0, 0, 1) corresponding to the upper 2 bits (0, 1) with the latch circuits 136, 13
7 and 138, respectively. The parallel code (0, 0) held in these latch circuits 136 to 138
0, 1) are supplied as control inputs to the switch elements 112 to 114, respectively. The lower bits of the digital input code word _{(D 5, D 4, D} 3, D 2, D 1, D 0) (0,1,0,1) is latched added respectively directly to the latch circuit 139 to 142 And the switch element 11
Parallel 4-bit control inputs (S ₇ ,
S ₆ , S ₅ , S ₄ ). In response to the control input (0, 0, 1, 0, 1, 0, 1), the switching elements 112, 113, 115 and 117 are turned to the left in FIG.
And 118 fall to the right. In response to the above states of the switch elements 112 to 118, the constant current sources 101,
Reference numerals 102, 104, and 106 respectively subtract the current value I from the power supply terminal 132 to the ground potential via the resistance element group 174. Switch elements 112, 113, 115 and 117
Are 2I / 3, 2I / 3, (1/2). (2I / 3) and (1/2) ^3. (2I / 3), respectively. According to the principle, the total sum I ₀ of the current flowing through the resistance element 123 is (42/16) · (2I / 3). Therefore, the parallel 6-bit code word (0, 1, 0, 1, 1)
DA converted output V _OUT of 0, 1) (42/16) (2
I / 3) · R.

Next, the correction of the conversion error in the main DAC section 153 by the auxiliary DAC section 154 will be described. Of the switch elements 119 to 122 of the auxiliary DAC section 154, only the switch element 119 is located on the left side in the circuit diagram of FIG. Connected to the resistance element group 174 and connected to the constant current source 108.
Is the current I flowing through the resistance element 123 when the constant current I is subtracted.
₀ is the same (1/2) ³ · (2I / 3) as when only the switch element 117 is tilted to the left. Similarly, the current value I ₀ when only the switch element 120 is tilted to the left is (1
/ 2) ⁴ · (2I / 3). The current value I _{0 in the} state where only the switch element 121 and only the switch element 122 are tilted to the left is (１ ／) ⁵ · (2I /
3) and (1/2) ⁶ · (2I / 3). Maximum value of the conversion error compensation amount, the current value I ₀ is the switch element 1
It is obtained when all of 19 to 122 correspond to the case of falling to the left, and the maximum value is (15/64) · (2I /
3), the minimum value is 0. Further, the minimum step width of the conversion error correction amount is obtained according to ON / OFF of the switch element 122, and its value is (1/64) · (2I / 3).

Next, the relationship between the conversion error correction amount and the parallel 6-bit input digital code words (D _{0 to} D ₅ ) will be described. As described above, the DA conversion output V
_The upper two bits (D ₅ ,
D ₄ ) and lower 4 bits (D ₃ , D ₂ , D ₁ , D ₀ )
The degree of influence, the current value I ₀ when the switching element 115 by subtracting the constant current I via the resistor element group 174 is (1 /
2) · (2I / 3), while the other switch element 112,
Since the current value I ₀ when the stop current I is drawn by the resistors 113 and 114 via the resistor element group 174 is (2I / 3), the degree of influence by the switch element 115 is the same as that by the switch elements 112 to 114. It may be considered 50% of the degree of influence. Similarly, the degrees of influence by the switch elements 116, 117 and 118 are 25%, 12.5% and 6.75%, respectively. Therefore, the target of error correction is the switch elements 11 related to the upper two bits (D ₅ , D ₄ ).
Even if only the switches 2, 113 and 114 are included and the switch element 115 is excluded from the correction target, there is no practical problem.

Next, the upper two bits (D ₅ , D ₄ ) are (0,
The correction data of 0) is calculated. Input digital code word _{(D 5, D 4, D} 3, D 2, D 1, D 0) is (0,
0, 1, 1, 1, 1), since the lower 4 bits are all 1s, the switch elements 115 to 118 are all tilted to the right in FIG. Does not affect the conversion error of the DA conversion output V _OUT . On the other hand, the upper 2 bits (D _5, D ₄₎ code word (0 appearing at the output of the latch circuit 136 to 138 because it is (0, 0),
0, 0), and the switch elements 112 to 114 tilt to the left, and all the currents from the switch elements pass through the resistance element 123. In this state, the DA conversion output V _OUT
Is the theoretical value of (6/2) · (2I / 3) · R
However, the DA conversion error caused by the constant current sources 101, 102, and 103 is inevitable. The main D of this DAC measured prior to storing the correction data in the EPROM 17
The conversion error inherent to the AC unit 153 is (1/16) · (2I
/ 3) · R This conversion error causes the switch element 120 to move to the left and switch elements 119, 121 and 1
Since the output voltage is equal to (1/16) · (2I / 3) · R of the auxiliary DAC unit 154 in a state in which the signal 22 is tilted to the right, the conversion error can be accurately corrected. That is, the control inputs (S ₃ , S ₂ , S ₁ , S ₀ ) to the switch elements 119 to 122 of the auxiliary DAC unit 154 are ( ₁ , ₀ , ₁ ,
The correction of the conversion error can be achieved by 1). These upper two bits (D ₅ , D ₄ ) are stored in EPROM1
7 and the above control input (1, 0, 1, 1)
1) is stored in the EPROM 17. That is, EPR
The 0th column of the memory cell array 240 of the OM 17 (P ₀₀ ,
_{P 10, P 20, P 30} ) to the code word (1,1,0,1)
Is stored.

When the upper two bits (D ₅ , D ₄ ) of the input digital signal are (0, 1), the above (0,
Correction data is created in the same manner as in the case of 0). That is, the digital input code word (D _{0 to} D ₅ ) is assumed to be a code word ( ₀ , 1, 1, 1, 1, 1) in which all the lower 4 bits (D _{3 to} D ₀ ) are set to 1. At this time, the upper two bits (0, 1) are converted into a code word (0, 0, 1) by the decoder 135 and the latch circuits 136 to 13
8 is latched. Therefore, the switching elements 112 and 113 are tilted to the left and the switching element 114 is tilted to the right, and the theoretical value of the DA conversion output V _OUT by the current I ₀ is (4/2) · (2I / 3) · R. Assuming that the previously measured conversion error due to the constant current sources 101 and 102 is (3/64) · (2I / 3) · R, the switch elements 121 and 122 of the auxiliary DAC unit 154 are switched to the left. {(1/2) ⁵ + (1/2) ⁶ } · (2I / 3) with 119 and 120 tilted to the right
R, that is, a correction output of (3/64). (2I / 3) .R is generated, so that the above conversion error can be eliminated. This conversion error is caused by switching elements 119 to 1 of auxiliary DAC section 154.
This can be achieved by making the control inputs (S ₃ , S ₂ , S ₁ , S ₀ ) to 22 into codewords ( ₁ , ₁ , ₀ , ₀ ). Therefore, the memory cell array 2 of the EPROM 17
The storage contents (P ₀₁ , P ₁₁ , P ₂₁ , P ₃₁ ) (FIG. 5) of the first column corresponding to the 40 upper bits (0, 1) are codewords (0, 0, 1, 1). The correction data when the upper two bits (D ₅ , D ₄ ) of the input digital signal are (1, 0) and (1, 1) are also the same as those for the above (0, 0) and (0, 1). Determined by the same procedure, EPR
The stored contents (P ₀₂ , P ₁₂ , P ₂₂ , P ₂₃ ) and (P ₀₃ , P ₁₃ , P ₂₃ , P ₃₃ ) of the second and third columns of the memory cell array 240 of the OM 17 are respectively (0 , 1,1,
1) and (1,1,1,1).

Next, the input digital codeword (D ₅ ,
D ₄ , D ₃ , D ₂ , D ₁ , D ₀ ) are ( ₀ , ₁ , ₀ , ₁ , ₁ ).
The operation of the auxiliary DAC unit 154 will be described more specifically, taking the case of (0, 1) as an example.

As described above, the main DAC 15 corresponding to the input code word (0, 1, 0, 1, 0, 1)
The theoretical value of the DA conversion output V _OUT of No. 3 is (42/16)
(2I / 3) · R. However, the actual main DAC unit 15
In No. 3, a conversion error occurs due to the constant current sources 101 to 107 and the resistor element circuit group 174. D including the error
The actual measured value of the A conversion output V _OUT is (42/16)
It is assumed that (2I / 3) · R− (4/64) · (2I / 3) · R. The register circuit 18 holds the above-described correction data transferred from the EPROM 17 through the above-described process. The input codeword (0, 1, 0,
The upper two bits (D ₅ , D ₄ ) of (1, 0, 1) are (0,
1), the matrix switch circuit 19 includes the DFFs 201, 211, 2 by the semiconductor switches 24-27.
21 and 231 output signals R ₀₁ , R ₁₁ , R ₂₁ and R
Select ₃₁ . That is, the matrix switch circuit 19
Control outputs (S ₃ , S ₂ , S ₁ , S ₀ ) are (1,
1, 0, 0) (see FIG. 11). The control output (S
₃ , S ₂ , S ₁ , S ₀ ), the switch elements 121 and 122 of the auxiliary DAC unit 154 are tilted to the left, and a current flows through the resistor element group 174, so that the error correction amount of the DA conversion output V _OUT of the main DAC unit 153 Is ｛(1/2) ⁵ +
(1/2) ⁶ ｝ · (2I / 3) · R = (3/64) ·
(2I / 3) · R. Therefore, the DA conversion output V
_OUT is

[0042]

Is as follows.

The D / A conversion accuracy of the first embodiment described above is based on the input digital code words (D ₅ , D ₄ , D ₃ , D ₂ , D
The unit change of the value of the DA conversion output V _OUT corresponding to the unit change of the least significant bit D ₀ (LSB) of ( ₁ , D ₀ ) is (1
/ 2) ⁴ · (2I / 3) · R.

Referring now to FIG. 12, the DAC of the second embodiment of the present invention shown in FIG. 12 uses the control signal φ ₀ instead of being supplied from the outside as in the first embodiment described above. The signal is generated by an oscillation circuit 28 incorporated in the control signal generation circuit 12. Except for this point, the second embodiment is the same as the first embodiment. Therefore, each component is indicated by the same reference numeral as in FIG. 2 and the description is omitted.

Referring to FIG. 13, the DAC according to the third embodiment of the present invention shown in FIG. 13 differs from the first embodiment in that a state control circuit 30 is added to the first embodiment, and a set signal generation circuit. 14 generates an output Tφ1 for controlling the control signal generation circuit 12 as well as the stop control signal T _S.

The state control circuit 30 has a third input terminal 31 for receiving a parallel 1-bit (1 is a natural number) input digital signal.
, And the output signal MCR is taken out. The output signal MCR gives the data transfer start address of the EPROM 17 to the set signal generation circuit 14 as a control input. The data transfer control circuit 10 has the same configuration as that of the first embodiment except that the output Tφ1 of the set signal generation circuit 14 is supplied to the control signal generation circuit 12.

Referring again to FIG. 13, in the DAC of the third embodiment, the state control circuit 30 has an EPROM
The address of the EPROM 17 from which the data stored in the EPROM 17 to start the data transfer to the register circuit 18 is input terminal row 3
1 as a control input. This data transfer start address is represented by an address input (A ₁ , A ₀ ), and the case where (A ₁ , A ₀ ) is ( ₁ , ₀ ) will be described as an example (the correction data stored in the EPROM 17 is the first data). The same as in the embodiment-see FIG. 7). Referring also to FIG. 14, the period during which power supply voltage V _cc reaches V ₁ volts 0 volts, as in the first embodiment, the control signal generating circuit 1
2 and the counter 13 are in a reset state. The output signal T _R of the reset signal generating circuit 11 is "0".
Further, output signals T _S and T of set signal generation circuit 14 are output.
φ1 is also “0”.

The output signal T _R signal is supplied to an input terminal 15 of the power supply voltage V _cc at a time t ₁ reaches V ₁ volt reset signal generation circuit 11 becomes a reset release signal. When the control signal φ ₀ input to the first input terminal 16 reaches the time point t ₂ when it becomes “1”, as in the first embodiment,
The control signal generation circuit 12 and the counter 13 start operating.

At time t ₃ , since the address (1, 0) of the data transfer start point of the EPROM 17 is input to the input terminal 31 of the state control circuit 30, the output signal Tφ 1 of the set signal generation circuit 14 becomes “ 0 ". Therefore, output signal φ ₁ of control signal generation circuit 12 is “0”
In this state, the output signal φ ₂ and the counter 13 continue to operate.

At time t ₄ , the counter 13 counts up in response to the output signal φ ₂ of the control signal generating circuit 12 and the output (A ₁ , A ₀ ) of the counter 13 becomes (0, 1). As a result, the memory cell array 2 of the EPROM 17
The first column of 40 is selected and the output signals (E _{0 to} E ₃ ) are E ₀
= 0, E ₁ = 0, E ₂ = 1, E ₃ = 1.

At time t ₅ , the address of the data transfer start point of the EPROM 17 is (1, 0) as in the state at time t ₃ , so that the output signal Tφ 1 of the set signal generation circuit 14 is “0”. Control signal generation circuit 12
Also of the output signal φ ₁ remains "0" remain. As a result, the output signals (E _{0 to} E ₃ ) of the EPROM 17 are not transferred to the register circuit 18, and the data of the registers 20 to 23 remain undefined.

Next, at time t ₆ , the counter 13 further counts up and outputs (A ₁ , A ₀ ) become (1, 1).
0). As a result, the second column of the memory cell array 240 of the EPROM 17 is selected, and the output signals (E _{0 to} E ₃ ) are E ₀ = 0, E ₁ = 1, E ₂ = 1, E ₃ = 1. Since the data transfer start address (1, 0) of the EPROM 17 and the output (1, 0) of the counter 13 are equal, the output signal Tφ1 of the set signal generation circuit 14 becomes “1”. Therefore, control signal φ ₁ appears from time t ₆ .

At time t ₇ , the control signal φ ₁ has a falling waveform, and the EP selected at time t ₇
The output signals E ₀ = 0, E ₁ = 1, E ₂ = 1, and E ₃ = 1 of the second column of the memory cell array 240 of the ROM 17 are transferred to the DFFs 203, 213, 223 and 2 of the registers 20 to 23.
Transfer to 33.

EPROM where transfer of the data should be stopped
Address 17 is an output signal M from the state control circuit 30.
The data is controlled by the CR to the address immediately before the data start address. Nachi Suwa stop address (A _1, A ₀₎ is (0,1) and is is from time t ₈ because to time t ₁₃ after another correction data EPROM17 register circuit 1
8 is transferred.

[0056] At time t _14, the output of the counter 13 (A _1, A ₀₎ is (0,1) and the stop control signals T _S and the set signal Tφ1 are "1" and "0" data transfer and counter Operation 13 stops.
At this time, the DFFs 200, 210,
220 and 230 hold the data of the second example of the EPROM 17, DFFs 201, 211, 221 and 231 hold the data of the third column,
2, 212, 222, and 232 hold data in the 0th column, and DFFs 203, 213, 223, and 233 hold data in the first column, respectively (FIG. 18).

By the above operation, the data stored in the EPROM 7 undergoes an address change and the register circuit 18
Transferred to and retained. That is, the correction data can be changed without rewriting the data stored in the EPROM 17. With the application of the voltage V _cc, the data transfer is complete until the voltage rises to V _c, the DA operation at the application time point of the input digital code word (D ₀ ~D ₅₎ is ready to start Are the same as those in the first embodiment, and a description thereof will be omitted.

Still referring to FIG. 15, the fourth embodiment of the present invention will be described.
The DAC of the third embodiment has four out of the input terminals 31 corresponding to the parallel 1 bit of the state control circuit 30 of the third embodiment.
Three data input terminals 33 to 36, and
0 generates the output signals MCS and MCX to the set signal generation circuit 14 in addition to the 4-bit data outputs MC0 to MC3. Output signal MCS is EPR
The data transfer end address of the OM 17 and the output signal MCX give the number of data to be transferred from the outside to the set signal generation circuit 14 as a control signal.

In the DAC of this embodiment, the data output signals MC0, MC1, MC2, and MC3 from the state control circuit 30 and the output signals E ₀ ,
It has selector circuits 40, 41, 42 and 43 for receiving E ₁ , E ₂ and E ₃ as inputs, and generates a set signal as a control signal for switching an input signal of a selector circuit group 39 composed of these selector circuits 40 to 43. Circuit 1
Provides a signal T _S from 4, and inputs an output signal of the selector circuit 40 to 42 and (F ₀ ~F ₃₎ to the register 20-23. Except for the above points, the configuration is the same as that of the third embodiment.

The operation of the DAC according to the fourth embodiment will be described with reference to FIG. Here, the start address of the data transfer of the EPROM 17 is (0, 0), and the end address of the data transfer is (0, 1). Also, EPROM
The data (P ₀₂ , P ₁₂ , P ₂₂ , P ₃₂ ) and (P ₀₃ , P ₁₃ , P ₂₃ ) of the addresses (1, 0) and (1, 1) at 17
The external data corresponding to (P ₃₃ ) is (X ₀₂ , X ₁₂ , X ₂₂ , X
₃₂ ), (X ₀₃ , X ₁₃ , X ₂₃ , X ₃₃ ), which are (1, 0, 0, 1) and (0, 1, 1, 0), respectively.

[0061] power supply voltage V _cc is V ₁ volt period from 0 volts, as in the first embodiment and the third embodiment, the control signal generating circuit 12 and the counter 13 is reset. Also the output T _R is "0" the reset signal generation circuit 11, the output T _S and Tφ1 of the set signal generation circuit 14 is also "0".

[0062] When the power supply voltage V _cc at a time t ₁ is V ₁ volt, the output T _R contains the signal to the input terminal 15 to the reset signal generation circuit 11 becomes a reset release signal. When the control signal φ ₀ to the input terminal 16 reaches the time point t _{2 at} which it becomes “1”, the control signal generation circuit 12 and the counter 13 start operating as in the first and third embodiments.

During the period from time t ₃ to time t ₅ , the data transfer start address (0, 0) of EPROM 17
Since the data transfer end address (0, 1) has been input to the state control circuit 30, the data in the EPROM 17 is transferred to the register circuit 18.

At time t ₆ , the outputs (A ₁ , A ₀ ) of the counter 13 become (0, 1) and the stop control signal T _S
Becomes "1" and the counter 13 and the control signal generation circuit 1
2 stops. On the other hand, since the output MCX of the state control circuit 30 indicates that there are two external data, the output signal Tφ 1 of the set signal generation circuit 14 remains “1” and the output φ of the control signal generation circuit 12 ₁ continues as it is. When the stop control signal T _S is “1”, the outputs MC 0, MC 1, MC 2 and M
The selector circuit group 39 is controlled so as to input C3.

[0065] Thus, the external data in the period ranging from the time point t ₇ to the time t ₉ (X ₂₀ ~X ₂₃₎ and (X ₃₀ ~X _{3 3)}
Is transferred to the register circuit 18.

[0066] At the time t _10, set the signal generating circuit 1
4 output signal Tφ1 becomes “0” and the control signal generation circuit 1
2 outputs phi ₁ is stopped.

Through the above-described process, a part of the data stored in the EPROM 17 and the external data are transferred to the register circuit 18 and held. That is, the correction data can be changed without rewriting the data stored in the EPROM 17.

[0068] DA conversion between the input digital signal after _the power supply voltage V _cc of the closing of the power switch in DAC100 this embodiment rises to V _c (D ₀ ~D ₅₎ is started. This point is the same operation as the first and third embodiments, and therefore the description is omitted.

Referring now to FIG. 17, a variation of the embodiment which can be applied in common to the above-described first to fourth embodiments is to directly supply bit-parallel input digital signals (D _{0 to} D ₅ ). A third latch circuit group 60 including latch circuits 61 to 66 for receiving and latching, and an input digital signal (D
_{0 to} D ₅ ) and the lower 4 bits (D _{0 to} D ₃ ) and the 4-bit output (S _{0 to} S ₃ ) of the matrix switch circuit 19.
And an output of the adder 80 (G
_{0 to} G ₃ ), and a fourth latch circuit group 70 including latch circuits 71 to 73 for latching the upper 3 bits. The output of the fourth latch circuit group (S ₄ To S ₁₀ ) are supplied to the switch elements 112 to 118 of the main DAC unit 153.

According to this modification of the embodiment of the present invention, the correction data and the lower 4 bits of the input digital signal (D _{0 to} D ₅ ) are set.
By adding the bits (D _{0 to} D ₃ ), the control signals of the switch elements 115 to 118 of the main DAC unit 153 can be changed.
That is, in addition to the conversion error correction in the auxiliary DAC unit 154, the conversion error correction based on the lower-order digit of the main DAC unit 153 can be performed, so that the correction can be performed beyond the maximum value of the correction amount possible in the auxiliary DAC unit 154. Due to the characteristics of the main DAC unit 153, a digital-to-analog converter with higher accuracy can be realized.

[0071]

As described above, in the DAC of the present invention, the error data corresponding to the previously detected conversion error is transferred from the storage circuit storing the error data to the register circuit during the rising period of the power supply voltage and held. After the power supply voltage reaches the operating voltage, the matrix switch circuit is operated in response to the higher-order bit to be subjected to the conversion error correction in the bit-parallel input digital codeword, and the correction data held in the register circuit is selected. Since the conversion error is corrected, there is no need to read out error data from the storage circuit every time an input digital code word requiring correction is applied, and the response speed can be remarkably increased as compared with the conventional DAC. . For example, the read time of the above memory circuit is about 500 nS and the response speed of the conventional DAC is about 1.2 μS, but the response speed of the DAC according to the present invention is several tens to several tens of times because the response speed is ten and several ns Can be realized.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a DAC according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a DAC according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing another part of the DAC according to the first embodiment of the present invention.

FIG. 4 is a more detailed circuit diagram of a part of the circuit shown in FIG. 3 of the DAC according to the first embodiment of the present invention;

FIG. 5 is a configuration diagram of a storage circuit and a register circuit shown in FIG. 1 of the DAC according to the first embodiment of the present invention.

FIG. 6 is a signal waveform diagram for explaining the operation of the DAC according to the first embodiment of the present invention.

FIG. 7 is a diagram showing data contents at a specific time point (time point t ₁ in FIG. 6) of the register circuit of the DAC.

FIG. 8 is a diagram showing data contents at a specific time point (time point t ₃ in FIG. 6) of the register circuit of the DAC.

FIG. 9 is a diagram showing data contents at a specific time point (time point t ₅ in FIG. 6) of the register circuit of the DAC.

FIG. 10 shows a specific time point of the register circuit of the DAC (FIG. 6)
FIG. 9 is a diagram showing data contents at time point t ₇ ).

FIG. 11 shows a specific time point of the register circuit of the DAC (FIG. 6)
FIG. 8 is a diagram showing data contents at time point t ₉ ).

FIG. 12 is a circuit diagram similar to FIG. 2 of a part of a DAC according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram similar to FIG. 2 of a part of a DAC according to a third embodiment of the present invention.

FIG. 14 is a signal waveform diagram for explaining the operation of the DAC according to the third embodiment of the present invention.

FIG. 15 is a circuit diagram similar to FIG. 2 of a part of a DAC according to a fourth embodiment of the present invention.

FIG. 16 is a signal waveform diagram for explaining the operation of the DAC according to the fourth embodiment of the present invention.

FIG. 17 is a modified circuit diagram of the above embodiment of the present invention.

FIG. 18 is a diagram showing data contents at a specific time point (time point t ₁₃ in FIG. 14) of the DAC circuit of the third embodiment.

[Explanation of symbols]

Reference Signs List 10 data transfer control circuit 11 reset signal generation circuit 12 control signal generation circuit 13 counter 14 set signal generation circuit 17 EPROM 18 register circuit 19 matrix switch circuit 20, 21, 22, 23 register 24, 25, 26, 27 semiconductor switch 28 oscillation Circuit 30 State control circuit 15, 16, 31, 33, 34, 35, 36, 147,
148, 149, 150, 151, 152 Input terminal 5, 6, 51, 52, 132 Power supply terminal 39 Selector circuit group 40, 41, 42, 43 Selector circuit 50 Power-on-clear circuit 53 Output terminal 61, 62, 63, 64 , 65,66,71,72,7
3,74,75,76,77,136,137,13
8, 139, 140, 141, 142 Latch circuit 60, 70, 171, 172 Latch circuit group 80 Adder 100 DAC 101, 102, 103, 104, 105, 106, 1
07, 108, 109, 110, 111 Constant current source 112, 113, 114, 115, 116, 117, 1
18, 119, 120, 121, 122 Switch elements 123, 124, 125, 126, 127, 128, 1
29, 130, 131 resistor element 133 DA conversion output terminal 135, 241 decoder 153 main DAC section 154 auxiliary DAC section 155 DAC section 174 resistor element group 200, 201, 202, 203, 210, 211, 21
12,213,220,221,222,223,23
₀ , 231, 232, 233 D flip-flop 240 Memory cell array A ₀ , A ₁ Counter output D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ Input digital code word E ₀ , E ₁ , E ₂ , E ₃ EPROM outputs F ₀ , F ₁ , F ₂ , F ₃ selector circuit outputs G ₀ , G ₁ , G ₂ , G ₃ Adder outputs I ₀ Currents flowing through the resistance element 123 S ₀ , S ₁ , S ₂ , S ₃ matrix switch circuit output codeword _{S 4, S 5, S 6} , S 7, S 8, S 9, S 10 latch circuit output codeword _{P 00, P 01, P 02} , P 03, P 10, P 11 , P ₁₂ , P ₁₃ , P
_{20, P 21, P 22,} P 23, P 30, P 31, P 32, P 33 the memory address _{R 00, R 01, R 02} , R 03, R 10, R 11, R 12, R 13, R
_{20, R 21, R 22,} R 23, R 30, R 31, R 32, R 33 register circuit output codeword _{X 02, X 12, X 22} , X 32, X 03, X 13, X 23, X 33
External data T _S stop signal T _R the reset signal generating circuit outputs _{φ 0, φ 1, φ 2} , Tφ1 control signals MC0, MC1, MC2, MC3, MCR, MCS, M
CX state control circuit outputs T1, T2 bipolar transistor V _cc power supply voltage V _c DA operating voltage V _OUT DA conversion output V _REF reference potential

Continuation of front page (56) References JP-A-55-100744 (JP, A) JP-A-59-36421 (JP, A) JP-A-1-142934 (JP, A) JP-A-1-300500 (JP) JP-A-63-268030 (JP, A) JP-A-1-129334 (JP, A) JP-A-54-125933 (JP, A) JP-A-2-185465 (JP, A) 2-46227 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) H03M 1/10 H03M 1/68

Claims (1)

(57) [Claims] 1. Digital-to-analog conversion of a digital signal
Main digital-to-analog conversion
Conversion section, and the analog signal and a desired analog signal.
Corresponding to the digital-to-analog conversion error that appears between
In response to error correction information for each digital signal, the digital
Analog-to-analog conversion error for each digital signal
An auxiliary digital-to-analog conversion unit, and the error correction information.
And stores the auxiliary digital
Digital circuit having a storage circuit for supplying the analog conversion section
An analog converter, which is above the power supply potential when the power is turned on.
And detects the rise and reads the error correction information from the storage circuit.
Corresponding to the data transfer control circuit and the error correction information.
And providing the read error correction information to the digital
Multiple registers that are held before the
The digital signal is input after the power is turned on.
Is supplied to the main digital-to-analog converter.
And the error correction information in response to the digital signal.
Are read from the corresponding registers and
It is supplied to an auxiliary digital-to-analog converter.
Digital-to-analog converter.