JPS60136460A - Dtmf signal generator - Google Patents

Abstract

PURPOSE:To attain IC-implementation and to allow low-voltage operation by constituting a circuit which generates a reference frequency signal while including an MOS type semiconductor element and a natural oscillation element, and generating an output of specific frequency. CONSTITUTION:A reference frequency signal from a reference oscillation circuit 11 is frequency-divided by a high group frequency dividing circuit 13 and a low group frequency dividing circuit 14 into two kinds of rated frequency, and a high group cosine wave generating circuit 16 and a low group cosine wave generating circuit 17 generate cosine wave signals. Those cosine wave signals are mixed by an output synthesizing circuit 18 to generate a DTMF (dual tone multiple frequency) signal, which is sent out to a telephone circuit. The reference oscillation circuit 11 consists of an inverter 11a, resistance 11b, a ceramic resonator 11c which has a natural oscillation frequency of 480kHz, capacitors 11d and 11e, N channel MOS transistor 11f, and NOR circuit 11g.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a DTMF (Dual Tone Multisol Frequency) signal generation device in a telephone communication network, and particularly to a DTMF (Dual Tone Multisol Frequency) signal generation device in response to key operations of a Zosh type telephone.
Pertains to generating and transmitting signals onto standard telephone lines.

[Technical background of the invention and its problems]

As is well known, the DTMF signal generator as described above divides the reference clock signal output from the reference oscillation circuit to a frequency that is standardized for each row and column where the operated key is located. , by converting these frequency-divided signals into cosine waveforms with different periods and combining them, 1
7' (DTMF signals are obtained in response to the 7 keys).

By the way, in the conventional DTMF signal generation device, the frequency of the reference clock signal output from the reference oscillation circuit is 3.
Since the frequency is as high as 58 MHz, the current consumption is large and the oscillation operation cannot be performed unless the line voltage is approximately 3.0 to 3.5 [V] or higher. However, in actual telephone lines, the line voltage sometimes drops to about 1.5 to 2.0 (V), and in such cases, the DTMF
'A problem arises in that the signal generator becomes inoperable.

Furthermore, the conventional DT signal generator consumes a large amount of current, has a complicated structure of the frequency dividing circuit, and the crystal resonator for 3.58 (MHz) used in the reference oscillation circuit is expensive and uneconomical. Various questions such as being at a disadvantage
This is what we have.

Therefore, conventionally, it has been considered to lower the frequency of the reference clock signal to reduce current consumption and enable operation at low voltages, but simply lowering the frequency of the reference clock signal does not work. , it is difficult to set the frequency division ratio to fully divide the clock signal to the standardized frequency for each row and column of the key layout, and the configuration of the frequency divider circuit itself becomes more complicated, resulting in lower accuracy. In this case, it becomes impossible to obtain a high-quality DTMF signal.

For this reason, conventional DTMs can operate stably even at low voltages and are economically advantageous due to their simple configuration.
There has been a demand for the development of an F signal generator, and this demand, combined with the recent demand for a DTMF signal generator 'i CMO8 integrated circuit, is strongly desired to be realized as much as possible. There is.

[Purpose of the invention]

This invention has been made based on the above circumstances, and is operable with a low power supply voltage, has a simple structure and is economically advantageous, and has an extremely good TMF that can effectively promote integrated circuits. Providing a signal generator? purpose.

[Summary of the invention]

That is, the present invention provides a frequency division method that divides a reference frequency signal into two standard frequencies in accordance with the type of key operated, and generates a sine wave signal sound having a period approximately equal to the frequency division period. and a DTMF signal generating device comprising a sine wave generating means, and a combining means for combining both signals outputted from the sine wave generating means and transmitting the obtained DT'' signal to a telephone line, wherein the reference frequency signal is The circuit for generating the oscillation frequency 'k is 480 (kH).
By setting the reference frequency signal near 480 (kHz) to the standard frequency and giving the frequency dividing means a frequency division ratio that can divide the reference frequency signal near 480 (kHz) to the standard frequency, it is possible to However, it is designed to operate stably.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, 11 is a reference oscillation circuit;
Inverter 11 &, resistance J 7 b, 480 [k
A CERAOC resonator 11c and a capacitor 11d have a natural frequency of Hz, ].

11*, N-channel MOS transistor llf and NO
It is composed of an R circuit 11g.

In this reference oscillation circuit 1, when a power down signal PD from a key input interface circuit 12, which will be described later, is active, that is, at an H (high) level, the transistor llf is turned on and the oscillation operation is stopped, and the NOR circuit 11g is also f-. 1 is in a closed state and its output is fixed at L (low) level, making it in a non-operating state. Further, in the reference oscillation circuit 1, when the t4 word-down signal PD is inactive or at the j5L level, the transistor llf is turned off and the oscillation operation is automatically started, and the NOR circuit 11g is also in the f-1 open state. In this case, a reference clock signal CK of 480 (kHz) is output.

Then, the above-mentioned reference a check signal CK is transmitted to the high group frequency divider circuit 1.
3 and a clock input terminal CKIN of the low group frequency divider circuit 14, respectively. Further, the high group and low group frequency dividing circuits 13 and 14 are configured such that the power down signal pD is supplied to their reset input terminals R, respectively.
When the arm power down signal PD is active, it is in a non-operating state, and when it is non-active, it is in an operating state in which the frequency of the reference clock signal CKi6 is divided based on the division ratio data output from the key input interface circuit 12. It is.

Here, the key human interface circuit 12 determines the position of the operated key among 12 keys arranged in three columns in the vertical direction and four rows in the horizontal direction on the key operation unit 15 shown by the dotted line in the figure. All corresponding frequency division ratio data are generated for each column and row. That is, the key operation unit 15
It has three column signal lines C1 to C3 and four row signal lines R1 to R4, and when any one key is operated, each signal line C1- of the column and row where the key is located is C, and R1 to R4k are activated.

For example, if the "5" key is operated, both the column signal line C2 and the row signal line Rs are activated.

In this way, when any one of the column signal lines 01 to C3 becomes active and any one of the row signal lines R1 to R4 becomes active, the key input interface circuit 12 activates the three signal lines corresponding to the column. Bits, bits, and bits of high group frequency division ratio data KC, ~KCs'ji are generated and output to the high group frequency division circuit 13, and 4-bit low group frequency division ratio data KR1 to KR41f corresponding to the rows are generated! : Generated and output to the low group frequency divider circuit 14. For example, when the "5" key is operated as described above, r O, 'I, OJ corresponding to activation of column signal line C, as high group frequency division ratio data KC, ~KC3. The row signal line R generates data as low group frequency division ratio data KR1 to KR4.

ro,I corresponding to becoming active.

0.0" is generated.

Further, the key input interface circuit 12 sets the above-mentioned word down signal PDi to the active or low level when no key is operated,
When any one key is operated, the column and row signal lines C
When I"Cm and R1-R4 become active, the 9 word-down signal PD becomes inactive (or becomes inactive)
This is the L level.

Then, based on the high group and low group frequency dividing ratio data KC1 to KC8 and KR1 to KR4 generated as described above, the high group and low group frequency dividing circuits 13 and 14 respectively generate the a-clock signal CK according to the reference. Divide the frequency.

In this case, the high group frequency division circuit J3 outputs high group frequency division ratio data KC corresponding to the activation of the column signal line CI.
When 1~KC, is input, the above 480 (kHz)
The reference clock signal CK122 is frequency-divided. Further, the high group frequency divider circuit 13 is connected to the column signal line C*+C
When high group frequency division ratio data KC, -KC, corresponding to B becoming active, is input, the reference clock signal C
Ki is operated to be frequency-divided by 20 and 18, respectively.

Further, the low group frequency dividing circuit 14 outputs low group frequency dividing ratio data K corresponding to the activation of the row signal line R1.
When R1 to KR are input, the reference clock signal C
It is operated to divide the frequency by Kf43. Furthermore, when the low group frequency dividing circuit 14 receives the low group frequency dividing ratio data KR1 to KR corresponding to the activation of the row signal line RN*R1+R4, the low group frequency dividing circuit 14 receives the reference clock signal CKi. 3 each
It is operated to divide the frequency by 9, 35, and 32.

Here, the above frequency division number r22, 20, 18°43.3
9, 35, 32J are the key operation unit 1, details of which will be described later.
These numbers are selected in order to finally obtain standardized frequencies for each column and each row of 5.

As described above, the high group frequency divider circuit 13 and the low group frequency divider circuit 1
A high group frequency division signal φ□ and a low group frequency division signal φ divided by 4,
are supplied to the input terminals IN of the high group cosine wave generation circuit 16 and the low group cosine wave generation circuit 17, respectively. These high group and low group cosine wave generating circuits 16.11 are configured such that the above mother power down signal FD is supplied to their reset input terminals R, respectively, and the power down signal P
When D is active, it is in an inactive state, and when it is non-active, it is in an operating state.

10- First, the high group cosine wave generation circuit 16 generates a time ' for 18 cycles of the high group frequency divided signal φ□, although the details will be described later.
This generates a stepped high group cosine wave signal whose voltage level changes every half period of the high group frequency divided signal φ□. Further, the low group cosine wave generation circuit 17 is
The I period is equal to 16 cycles of the low group frequency division signal φ, and a step-like low group cosine wave signal whose voltage level changes every half period of the low group frequency division signal φ1 is generated. . That is, in terms of frequency, these high group and low group cosine wave signals are equal to the high group and low group frequency divided signals φ8. They are obtained by dividing φL by 18 and 16, respectively. In this case, the frequency division number r18. I6J is also a number selected to obtain a standardized frequency for each column and each row of the key operation section 15, as previously explained in the high group and low group frequency dividing circuits 13 and 14.

In this way, the high group and low group cosine wave generation circuits 16.
The high group and low group cosine wave signals outputted from 17 are combined by an output combining circuit 18, respectively, to generate a DTMF signal corresponding to one key. This DTMF' signal can be sent to a telephone line, exchange, etc. (not shown) through all the output terminals 19. The power down signal PD is also supplied to the reset input terminal R of the output combining circuit 18, and the output combining circuit 18 is in an inactive state when the power down signal PD is active. The reference clock signal CK output from the reference oscillation circuit 1 is outputted from the high group and low group frequency dividing circuits 13, . After the frequency is divided by the frequency dividing ratio corresponding to each row and column where the key operated by 14 is located, high group and low group cosine wave generating circuits 16 and 17 respectively generate 18
The key operation section 15
High group and low group frequency divider circuit 13 by making column and row signal lines C1 to C3 and R, -R4 active.
．． The output frequencies of 14 and the output frequencies of high group and low group cosine wave generating circuits 16 and 17 are as shown in the following table.

13- That is, for example, when the row signal R1 is activated, the low group frequency divider circuit 14 divides the frequency of the reference clock signal CK143 of 480 (kHz) to 11.J6[
kHz) outputs a low group frequency divided signal φL. Then, the low group cosine wave generation circuit 17 has a frequency of 11, 16 [kHz]
] Low group frequency divided signal φ is divided by J-16 to obtain 697.7[
Hz] outputs a low group cosine wave signal. Here, the frequency of 697.7 [Hz] of the low group cosine wave signal is
It is extremely accurate, having only a deviation of 0.1 C% from the predetermined standard frequency of 697 [Hz] for the row signal line R1, and here the row signal line R
It is possible to obtain the standard frequency corresponding to 1. Further, the other signal lines R, -R4, and C1 to C3 can be explained in substantially the same manner as described above, and the corresponding standard frequencies can be obtained.

The overall operation has been explained above, and next, the detailed configuration and operation of each part will be explained. First, FIG. 2 shows the reference oscillation circuit 11, and the inverter lla is composed of a P channel MO transistor Q1 and an N channel MOS transistor Q1 as shown. In addition, a human resistor 11b and an output resistor 11 are provided at the input end and the output end of the inverter 11a, respectively.
1 is connected. In this case, the connection terminals 11j, II
The part above k in the figure is the part to be integrated into a CMO8 circuit, and the output resistor 111° ceramic resonator lie and capacitors 11d and lle are externally attached.

Further, in FIG. 2, 111 is an input terminal to which the power down signal PD is supplied, and 11m is an output terminal connected to the clock input terminal CKIN of the high group and low group frequency dividing circuits 13 and 14, 11n is a power supply terminal to which a DC voltage of 10 V is applied.

Here, the above-mentioned ceramic cresonator LLC has a reference frequency of 480 CkHz and a frequency tolerance of ±0.5.
[H], resonant resistance 20 [Ω] or less, anti-resonance resistance 70 [k]
Ω] or more, temperature stability ±0.3 [chi] (-20 [℃] ~
+80 [°C]) with a characteristic of 'kV' has been realized. Further, the resistor 11b has a feedback function,
Normally, something about 1 [title] is used. Furthermore, in practice, the input resistor 11b and the output resistor 111 are each about 1 [kΩ], and the capacitor l
Each of ld and 11e is of the order of ]0O[...] for operation.

Accordingly, according to the reference oscillation circuit 11 as described above,
1.5 since it is configured using MOS transistors.
CV) ~2.0 [V] (7) Sufficiently stable oscillation operation can be performed even at low voltage, and
Option 9 is also direct and suitable for CMO8 integrated circuits. Also, the frequency of the reference clock signal CK is changed from the conventional 3.
Since the frequency is significantly lower than 58 (MHz) to 480 [kHz], the operating current consumption, which is determined by frequency x voltage x charge/discharge capacity, can also be significantly lowered. Furthermore, since the ceramic resonator 1lcf is used, it is economically advantageous compared to the conventional one using a crystal resonator 17--.

Here, the frequency of the reference clock signal CK is set such that the current consumption is reduced to the extent that sufficient stable oscillation operation can be performed even at a low voltage of, for example, 1.5 [V] to 2.0 [:V]. One condition is that the frequency is as low as possible, the other is that the frequency is high enough to allow the various frequency dividing means connected to the subsequent stage to perform stable frequency dividing operations, and the frequency is as low as possible, as shown in the diagram. 480 (kHz) was selected based on the condition that all the ratios are realized by simple integers and that it is a frequency that can obtain a frequency that is extremely close to the standard frequency.

Therefore, the frequency of the reference clock signal CK is exactly 4
80 CkHz)
, 480 (kHz), it is acceptable even if there is a slight variation around 480 (kHz), and in short, it is sufficient as long as it is around 480 [kHz].

Next, FIG. 3 shows the high group frequency dividing circuit 13'Jf. In other words, this high group frequency divider circuit 1318- is functionally equivalent to a programmable frequency divider, and
It consists of a bit shift counter circuit 20, a programmable state detection circuit 21, and a binary counter circuit 22. Of these, 4-bit shift counter circuit 2O
consists of four D-type flip-flop circuits (hereinafter referred to as DFF).
201 to 20df are connected in series, and the output terminals Q of the final stage DFF circuits 20c and 20d are connected to an exclusive OR circuit (hereinafter referred to as an EX-NOR circuit) 20e.
It is connected to the input end of the first-stage DFF circuit 20a via the DFF circuit 20a.

The clock input terminal CK of each DFF circuit 201L to 20d is connected to the input terminal 20fK to which the reference clock signal CK is supplied.

In addition, 20g in the figure is an input terminal to which the worddown signal PD is supplied, and it is connected to each DFF via an OR circuit 20b.
It is connected to the reset input terminal R of circuits 2Oa to 20 (1). Then, when any key of the key operation section J5 is operated, the power down signal PD becomes inactive as shown in FIG. 4(-). When it is done to the fiL level,
The reference oscillation circuit 11 is driven and a reference clock signal CK is generated as shown in FIG. 4(b). Then, the 4-bit shift counter circuit 2O starts operating and each DF
The outputs of the F circuits 20h to 20d are supplied to the programmable state detection circuit 21.

Here, the programmable state detection circuit 21 appropriately calculates the outputs of the DFF circuits 20 a to 20 d based on the high group frequency division ratio data KC1% KC, and calculates the reference clock signal CKt high group frequency division. Ratio data KC1~KC
It outputs a frequency division signal as shown in FIG. 4(C), which is divided by the frequency division ratio specified by 1. This frequency-divided pulse signal is applied to each DF via the OR circuit 20hf.
The signal is supplied to the reset input terminal R of F circuits 20IL to 20 (1), and the 4-bit shift counter circuit 2O is reset each time it becomes H level. The signal is supplied to the binary counter circuit 22, and its level is inverted every time it rises to generate a high group frequency division signal φyo as shown in FIG. 4(d). In this case, the programmable state detection circuit 21 controls and outputs the frequency division/f pulse signal so that the ratio of the H level period and the L level period of the high group frequency division signal φ□ is approximately 50C%E. The high group frequency divided signal φyo output from the binary counter circuit 22 is outputted to the high group cosine wave generating circuit 16 via the output terminal 23.

Next, FIG. 5 shows the low group frequency divider circuit 14. This low group frequency divider circuit 14 is also functionally equivalent to a programmable frequency divider, and is a 6-bit shift counter circuit 24.
, programmable state detection circuit 25, and NOR circuit 2e.
Set-reset type free consisting of a + x 6 b.

This is similar to the Zoflop circuit (hereinafter referred to as R-SFF circuit) 26. Among these, the 6-bit shift counter circuit 24 has six DFF circuits 24a to 24ff connected in series, and output terminals QgEX-NORO of the DFF circuits 2l-24e and 24f.
R circuit 24 f, input terminal D of first stage DFF circuit 24m
K connections are made.

The clock input terminal CK of each DFF circuit 24a to 24f is connected to the input terminal 24b to which the reference clock signal CK is supplied.

Reference numeral 241 in the figure is an input terminal to which the power down signal PD is supplied, and is connected to the reset input terminal R of each DFF circuit 24&~1141 via an OR circuit 24. Then, when any key of the key operation section 15 is operated and the 4-way down signal PD is made to the non-active or JL level (as shown in FIG. 6), the reference oscillation circuit 1 is driven, and a reference clock signal CK is generated as shown in FIG. 6(b). Then, the 6-bit shift counter circuit 24 starts operating, and the outputs of the OFF circuits 24h to 24f are supplied to the programmable state detection circuit 25.

Here, the programmable state detection circuits 22-25 suitably calculate the outputs of the respective DFF circuits 24a to 24f based on the low group frequency division ratio data KR1%KR, and detect the outputs of the above-mentioned reference a check signals CK. −i Separate for each frequency division ratio specified by low group frequency division ratio data KR, ~KR,
It outputs frequency-divided pulse signals as shown in FIGS. 6(e) and 6(d), respectively. One of these frequency-divided pulse signals (see FIG. 6(C)) is supplied to the OR circuit 24J.
'fr is supplied to the reset input terminals R of the DFF circuits 24a to 24f, and the 6-bit shift counter circuit 24 is reset each time it becomes H level. And these frequency-divided pulse signals are
It is supplied to the R-SFF circuit 26, set at the rising edge of the frequency division pulse signal shown in FIG. 6(d), and reset at the rising edge of the frequency division pulse signal shown in FIG. 6(,). , here a low group frequency division signal φ1 as shown in FIG. 6(,) is generated. In this case, the programmable state detection circuit 25 controls and outputs the branch pulse signal so that the ratio of the H level period and the L level period of the low group frequency division signal φ1 is approximately 50%E. It is something. Then, the low group frequency division signal φ output from the R-SFF circuit 26,
is outputted to the low group cosine wave generation circuit 17 via the output terminal 27.

Next, FIG. 7 shows the high group cosine wave generating circuit 16f. That is, first, 18 DFF circuits t
-I)is are connected in series to form a 9-bit shift power counter circuit 28.

How many of these DFF circuits DI"Dlll have odd codes?
*D9 +D11 r D13 v I)ts l
Dty has its clock input terminal φ connected to the input terminal 28hVC to which the high group frequency division signal φ□ is supplied.

In other words, DFF circuits with odd numbers (1-yl),
latches the signal supplied to the input end at the rising edge of the high group frequency division signal φ□ and outputs it from the output end Q. Furthermore, among the above DFF circuits D1 to I)ts, the DFF circuit D2 with an even number code #D4*D6eI)
s 1D+or Dxz +014 + Dts +
Dts is 1, and the output terminal φ is connected to the input terminal 28.
connected to a. Tsumashi, DF with even number sign
The FFF circuits -2 to Is latch the signal supplied to the input terminal at the falling edge of the high group frequency division signal φ, and output it from the output terminal Q.

Further, the reset input terminals R of each of the DFF circuits D1 to D11B are connected to the input terminal 28b to which the power down signal PD is supplied.

Furthermore, the final stage D of the 9-bit shift power counter circuit 28
The output terminal Q of the FF' circuit DIi1 is connected to the inverter 28cf.
It is connected to the input end of the first-stage DFF circuit Dl through it, and is also connected to one input end of the NOR circuit 29.

Here, the switch circuits 81 to 5ill generate a reference voltage v11y which is outputted from the reference voltage generation circuit 32 in accordance with the DFFFF circuits-1 to Dllll, respectively.
Is one of the switch circuits S1-StS that operates to selectively supply VB2k to the capacitors C1-0111? For example, it is configured as shown in FIG. Tsumashi, above DFF circuit D
The input terminal 33 to which the 25- outputs of 1 to D1g are supplied is connected to the control electrode of the P channel MOS transistor 34, and is also connected to the other P channel MOS transistor 3 via the inverter 35.
60 control electrodes. One of the controlled electrodes of these transistors 34 and 36 is connected to the power supply line 32a to which the reference voltages v and 2 are applied, respectively.

RL R2 32b, and the other controlled electrodes are both connected to an output terminal 37 connected to the capacitor CI"C1l. Therefore, the DFF circuit DI"Dllll
When the output terminal Q of the transistor 34 is set to H level, the transistor 34
is turned on and the reference voltage ■8□ is generated at the output terminal 37. Also, when the output terminal Q of the DFF circuit DI""'DI11 is set to L level, the transistor 36 is turned on and the reference voltage ■8□ is generated at the output terminal 37.
is generated at the output terminal 37.

In this case, the reference voltage vR□1vR2 is: ■8□〉v
The relationship is R□, and in particular, the power supply voltage may be used directly for one of the reference voltages vR1.

Further, as shown in FIG. 7 again, the power supply line 32h to which the reference voltage vR□ is applied is connected to the other end of the switch 31. Further, the output terminal Q of the DFF circuit Dl is connected to the other input terminal of the NOR circuit 29. The switch 31 is connected to the NOR circuit 2
It operates so that it is turned on when the output of No. 9 is at H level and turned off when it is at L level.

High group cosine wave generation circuit 1 configured as above
6, the entire operation will be explained below. First, it is assumed that a high group frequency division signal φ□ as shown in FIG. 9(,) is supplied to the input terminal 28a. Then, each DF'F circuit D1 to I)
As shown in FIGS. 9(b) to (s), the output of ta is the high group frequency divided signal φ□ divided by 18, and the phase is 1/2 period of the high group frequency divided signal φ. It will be shifted one by one. The output of the NOR circuit 29 is shown in FIG. 9 (1).
As shown in FIG.
The signal is kept at H level only during the period. Note that the output of the NOR circuit 29 has become H level i R
It is assumed that a CH signal has been generated.

Now, suppose that the RCH signal is generated at time tl in FIG. 9 as shown in FIG. 9 (1). Then, the switch 31 is turned on, and the reference voltage vR□ output from the reference voltage generation circuit 32 is applied to the output terminal 3 via the switch 31f.
Generated at 0. Here, FIG. 10 shows changes in the voltage level generated at the output terminal 30. For ease of understanding, the same symbols are attached to the same times as in FIG. The frequency-divided signal φ□ and the RCH signal are also shown.

That is, when the RCH signal is generated at time t1, the reference voltage vR□ is generated at the output terminal 30.

At this time, as is clear from FIG. 9, all DFF circuits D! Since the output of ~Dts is at L level, the switch circuit S~S1= is the reference voltage V, 1e capacitor 0
1 to C, 8: Outputting. Tsumushi, each capacitor C
The reference voltage ■8□ is applied to the upper side of FIG. 7 from 1 to CtS, and the reference voltage vR1 is also applied to the lower side.

Then, time 1. At the rising edge of the next high group frequency division signal φY (time tz), the DFF circuit D is activated as shown in FIG. 9(b).
! When the output terminal Q of
Wodensa C! will be output to . At this time, the voltage fluctuation occurring at the output terminal 30 is
Let CH be the parallel combined capacity of .

becomes. Therefore, the voltage generated at the output terminal 30 is as follows. Here, as mentioned above, 29 of VR□〉vR□
- Since there is a relationship, the voltage expressed by equation (1), the first
As shown in Figure 0, it is lower than the reference voltage ■3□.

Next, time 1. At the next falling edge of the high group frequency division signal φY (time ts), the DFF circuit is activated as shown in FIG. 9(C).
When the output terminal Q of is inverted to H level, the switch circuit S
! is now output to the reference voltage VB2e capacitor C. Therefore, the voltage generated at the output terminal 30 is as follows, and as shown in FIG. 10, the directivity expressed by equation (1) also becomes lower.

As above, DFFFF circuit-3~DI? As the output terminal Q is sequentially inverted to H level, the voltage generated at the output terminal 30 becomes lower every 1/2 period of the high group frequency division signal φ□, as shown in FIG. It's something that will happen.

Now, at time t4, when the output terminal Q of the final stage DFF circuit ta is inverted to H level -30- as shown in FIG.
is output to the capacitor C1l.

Therefore, the voltage generated at the output terminal 30 is.

=vR2, where 1A cycle of the stepped high group cosine wave signal is obtained.

Here, the capacitance of each of the capacitors 01 to C11l is a factor that determines the width of the voltage fluctuation.
The capacitors CteCtse located at both ends in the figure are the smallest, and the capacitors 9 and CG+CI become larger toward the center. It is set symmetrically so that the maximum is achieved. By doing this, as shown in FIG. 10, the stepwise voltage fluctuation width of the high group cosine wave signal is controlled, and the waveform is brought closer to a high cosine waveform.

At this time t4, each capacitor C1 to C
The voltages on the upper and lower sides of tS in FIG. 7 are both the reference voltage vR□.

Next, at the rising edge of the next high group frequency division signal φ3 after time t4 (time Ts), the DFF circuit Dl
When the output terminal Q of is inverted to L level, the switch circuit S
1 is outputted to the capacitor C1 as the reference voltage VR1. Therefore, the voltage generated at the output terminal 30 is as follows. Here, because of the relationship vRl>VR□ as described above, the voltage value expressed by equation (2) is also higher than the reference voltage vR□, as shown in FIG.

Then, at the falling edge of the next high group frequency division signal φ□ at time t5 (time 1.), as shown in FIG. 9(c), the DFF circuit D!
When the output terminal Q of is inverted to L level, the switch circuit S
, so that the reference voltage VRX is output to all capacitors C2, the voltage generated at the output terminal 30 becomes even higher than the value expressed by equation (2), as shown in FIG. .

As the DFFFF circuit-3 to Dty output terminal Q are sequentially inverted to the L level as described above, the voltage generated at the output terminal 3O is as shown in FIG. The value gradually increases every 1/2 cycle of □.

Then, at time t, when the output terminal Q of the DFF circuit Dla is inverted to L level as shown in FIG. 9(,), the RCH signal is generated as shown in FIG. 9(1), and the When the switch 31 is turned on, the voltage generated at the output terminal 30 is refreshed to the original reference voltage VB□, and the cycle of the high group cosine wave signal is completed.

33- Next, FIG. 11 shows the low group cosine wave generating circuit 17. However, this low group cosine wave generation circuit 1
7 has substantially the same configuration as the above-mentioned high group cosine wave generation circuit 16, the same parts as in FIG. 7 are shown with the same symbols, and only the different parts will be explained here.

That is, since the low group cosine wave generation circuit 17 generates a cosine wave signal in which the 16 period period of the low group frequency divided signal φ is one period in total, 16 DFF circuits Dl-D1611r are connected in series. The difference from the high group cosine wave generation circuit 16 is that an 8-bit shift counter circuit 38 is used. Furthermore, in this case, the low group frequency division signal φ1 is supplied to the input terminal 28m.
RCL indicates that the output of the NOR circuit 29 has become H level.
Let us assume that a signal has been generated.

Roughly speaking, the capacitance of each capacitor CI'''C16 is the 11th
Capacitors C,,C, located at both ends in the figure.

The capacitors are set symmetrically so that the capacitor ca+c9 is the minimum, gradually increases toward the center, and the capacitor ca+c9 is the maximum.

With this configuration, the specific operation can be explained in the same way as the high group cosine wave generation circuit 16, and the low group frequency divided signal φ, as shown in FIG. A low group cosine wave signal having one period of 16 periods can be obtained.

Therefore, according to the high group and low group cosine wave generating circuits 16 and 17 as described above, each capacitor CI''C18
Since the voltages applied to both ends of the ax-cts and ax-cts are sequentially varied to obtain high-group and low-group cosine wave signals at the output terminal 30, no steady current flows, reducing overall current consumption. This makes it possible to operate with a low power supply voltage.

Regarding this point, the conventional cosine wave generation circuit has a reference voltage +v across the resistor 39, as shown in FIG.
, -v'2 respectively, all the switches SW are connected to predetermined positions of the resistor 39, and all the switches SW are sequentially turned on and off by the control signal),
An attempt is made to obtain a cosine wave as shown in FIG. 13(b).

For this reason, in the conventional circuit, a steady current always flows through the resistor 39, which consumes a large amount of current, making it difficult to lower the power supply voltage.

However, according to the high group and low group cosine wave generation circuits 16 and 17 as shown in FIGS. This can effectively promote CMO8 integrated circuit integration of the signal generator.

Here, the ratio of the capacitance values of the capacitors C1 to CI+1 of the high group cosine wave generating circuit 16 is
When the total parallel composite capacitance CHerlJ is tS, a good high group cosine wave signal can be obtained by setting as shown in Table (1), for example.

37- In this case, the ratio of each capacitance value of the capacitors C1 to C1g is determined as follows. In other words, among the 18 capacitors ct""cts, the capacitor ct""ct
When the total parallel combined capacitance CH of s is normalized as "1", the parallel combined capacitance, stone, Ct from the capacitor C1 to the Nth capacitor is expressed as follows. Therefore, N=1, that is, capacitor C,
The capacitance of is 9, N=2 capacitor c1. The parallel combined capacitance of c2 is p, and the parallel combined capacitance of N=3 capacitors 01 to c3 is 38-. The parallel combined capacitance obtained in this way is summarized in Table (2).

For example, since the capacitance when N=2 is (C1+C2), by subtracting the capacitance when N=1, 0.
0302-0.0076=0.0226 and the above clothing (1)
The ratio of the capacitance of capacitor C2 shown in FIG.

Further, the capacitance ratio of each capacitor ct-cts of the low group cosine wave generating circuit 17 can also be determined in the same manner as described above, and is shown in Table (3).

Table (3) Here, the high group and low group cosine wave generation circuit 16.1
Taking the low group cosine wave generating circuit 17 as an example, 7 can also be configured as shown in FIG. That is, this uses eight DFFFF circuits -1 to DI+ switch circuits 81 to S8 and capacitors 01 to C8, and the low group frequency division signal φL'fr'A component supplied to the input terminal 28* is used. Each DFF circuit D1 via the circuit 40
~D8 clock input terminal φ or 1.

With this configuration, when the low group frequency division signal φL as shown in FIG. 15(LL) is supplied to the input terminal 281L, the output of the frequency division circuit 4O is as shown in FIG. 15(b). It becomes as shown in . Then, the DFF circuit DI "' D8,
By operating the switch circuits S1 to Ss and the capacitors C1 to C8 as described above, a low group cosine wave signal as shown in FIG. 15(c) can be obtained at the output terminal 30. This low group cosine signal is similar to that shown in FIG.
1. The 16 cycle period of L is one cycle. $1241
− The resolution is different from that shown in the figure.

Therefore, in cases where high precision is not required for the cosino waveform, the configuration can be further simplified by adopting the configuration shown in FIG. 14. Note that FIG. 15(d) shows the generation state of the RCL signal.

It goes without saying that the configuration of the high group cosine wave generation circuit 16 can also be simplified in the same manner as described above. In this case, the number of DFF circuits, switch circuits, and capacitors is set to nine, and the high group frequency division signal φn
The clock input terminal φ or f of the DFF circuit is divided by tH.
It is only necessary to have it supplied to

Furthermore, as shown in FIG. 16, the high group cosine wave generation circuit 16 connects the set input terminal S of the DFF circuit 010""Dlg to the input terminal 28b, and the power down signal P
When D is inverted from H level to L level, the DFF circuit output terminal Q of %D is reset to L level, and O
FF circuit DIG~42-1) If the output terminal Q of ts is set to H level, a sine waveform can be obtained, which can be selected as appropriate.

Also, in the low group cosine wave generation circuit 17, D
Set input terminal S of FFFF circuit-9 to Is to input terminal 2
Of course, by connecting to 8b, a sine waveform can be obtained.

Next, FIG. 17 shows the output synthesis circuit 18. That is, in the figure, '41' is an input terminal to which the high group cosine wave signal outputted from the high group cosine wave generating circuit 16 is supplied. This input terminal 41 is grounded via a capacitor CFI 1 + cH2 in series. And the connection point of the above capacitor C old + CH2 is
It is connected via a switch circuit 42 to a power supply terminal 43 to which a reference voltage VBBO is applied, and is also connected to an operational amplifier OP.

is connected to the non-inverting input terminal (+) of Here, the switch circuit 42 is connected to the high group cosine wave generating circuit 16.
the presence or absence of the RCHM signal generated from the NOR circuit 29;
#) It is turned on and off depending on the H level and L level. A circuit including the capacitor C1CH2 and the switch circuit 42 constitutes a high group level conversion circuit 44.

On the other hand, numeral 45 in FIG. 17 is an input terminal to which the low group cosine wave signal output from the low group cosine wave generating circuit 17 is supplied. This input terminal 45 is a capacitor C
It is grounded via L11CL2 in series. The connection point of the capacitor CLI1CL2 is connected to the power supply terminal 47 to which the reference voltage VR3 is applied via the switch circuit 46.
It is also connected to the non-inverting input terminal (+) of the operational amplifier OP2.

Here, the switch circuit 46 is turned on or off depending on the presence or absence of the RCL signal generated from the NOR circuit 29 of the low group cosine wave generation circuit 17, that is, the H level or L level. And the above capacitor CLI +
Circuits such as Cu2 and the switch circuit 46 constitute the low group level conversion circuit 48.

Here, the operational amplifiers 0P110P2 each have a female logic follower configuration in which their output terminals are connected to the inverting input terminal (-), and constitute buffer amplifiers 49 and 50 for impedance conversion. It is. The output terminals of this buffer amplifier 49°50 are connected to resistors R1+R, respectively.
1, and the connection point is NPN
Transistor Tr! Connected to the pace of. In addition, the collector of this transistor Tr1 is connected to a DC voltage (+
It is connected to a power supply terminal 51 to which Va) is applied, and its emitter is connected to an output terminal 52. The buffer amplifiers 49, 50, resistors R1+R2 and transistors Tr
The mixing circuit 53 is a circuit of the first order of magnitude.

In the output synthesis circuit 18 configured as described above, first, the high group cosine wave signal supplied to the input terminal 41 is level-converted according to the capacitance ratio of the capacitors CHI r CHI, and the switch circuit 42 is switched every cycle. By being turned on, the level is shifted as reference voltage Vnst-reference. In addition, the low group cosine wave signal 45- supplied to the input terminal 45 is also level-converted according to the capacitance ratio of the capacitors CLI + Cu2, and the switch circuit 46 is turned on every cycle to convert the level to the reference voltage. The level is shifted based on the via. Such a level conversion operation is intended to facilitate voltage synthesis in the mixing circuit 53 at the subsequent stage.

The high group and low group cosine wave signals level-converted as described above are voltage-synthesized via buffer amplifiers 49 and 50 and resistors R11R2, respectively, and the transistors Tr
1, the current is converted and output as a DTMF signal to the output terminal 52.
It is sent to the telephone line via the telephone line. in short,
The output synthesis circuit 18 functions to provide voltage amplitude, output impedance, etc. suitable for transmitting a DTMF signal of a telephone line.

Therefore, according to the output synthesis circuit 18 as described above,
Buffer amplifier 49 which is a signal input section of mixing circuit 530
．． 50 has a high input impedance, so the level conversion circuit 4 which is a signal supply section to the mixing circuit 53
4, 4846- as capacitor C old + CH2 and ct, i l C
A high impedance device using L2 can be used, a good TMF signal can be generated, and the configuration can be simplified.

Regarding this point, the conventional output synthesis circuit is shown in FIG.
As shown in , the high group and low group cosine wave signals supplied to the input terminals 54 and 55 are current-added via the resistors Ra+R+e, and the Darlington-connected transistor Tr2
, TrB to obtain the DTMF signal from the output terminal 56, or as shown in FIG. Combined via R6, operational amplifier OP,
and an output terminal 60 via an amplifier 59 consisting of a resistor R7.
The DTMF signal is obtained from For this reason, the input impedance is low, and there is a problem in that it cannot be used as an input signal source unless it has low impedance, and it is particularly difficult to operate at a low voltage.

However, according to the output synthesis circuit 18 shown in FIG. 17, as mentioned above, a capacitive type can be freely used as the input signal source, and low voltage can be easily achieved by using a MOS transistor. It is possible to aim for

Next, FIGS. 19 to 23 show other examples of the output synthesis circuit 18, respectively.

First, what is shown in FIG. 19 is the buffer amplifier 49.5.
0 to N channel MOS) Lanzostar Qs+Q4 and Q
It is configured using s+Qs, and in this case, it has a source follower configuration. In this way, it is possible to make the input impedance high and the output impedance all the groups with a simple configuration, and in particular, low voltage operation can be easily made possible.

In addition, the one shown in FIG. 20 configures a differential circuit with N-channel MOS transistors Q7 to Q9, and the transistor Q
? , Qll's source composite voltage 'i is taken out as a DTMF signal.

Furthermore, what is shown in FIG.
Integrating circuit 61.62 and resistor R81R are better than 410P5
DTMF signal is obtained through an amplifier 63 consisting of a resistor RtO and an operational amplifier 0Ps.

In addition, in the device shown in FIG. 22, the high group and low group cosine wave signals supplied to the input terminals 64 and 65 are connected to source follower circuits 66 and 67 and resistors al as shown in FIG.
synthesized through l + Rls k, resistor ats l 1
R14* R15% Amplifier 6 similar to operational amplifier OP7
8 and transistor Tr4ffi to obtain a DTMF signal. In this case, operational amplifier 0P
The voltage applied to the inverting input terminal (-) of 70 is the reference voltage VR
4'c source follower circuit 69. Here, the resistor R13 is the input resistance of the operational amplifier 0Py, and the resistor R14r Rts is the 49-pin resistor for setting the r-in of the amplifier 68.

Furthermore, in the configuration shown in FIG.
111r R1? The signal is led to the transistor Tr4 via an amplifier 70 of υ. In this case, resistor R16 is for the r-in setting of amplifier 70, and resistor at
y is the input resistance of the operational amplifier ops.

Here, in the various output combining circuits 18 described above, if there is no need to convert the level of the high group and low group cosine wave signals, the high group and low group cosine wave signals output from the high group and low group cosine wave generating circuits 16 and 17 Of course, the and low group cosine wave signals may be combined as described above without going through the high group and low group level conversion circuits 44 and 411.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, it is possible to operate with a low power supply voltage, has a simple structure, is economically advantageous, and is extremely effective in promoting integrated circuits. A good TMF signal generator can be provided.

[Brief explanation of drawings]

FIG. 1 is a block circuit configuration diagram showing an embodiment of the DTMF signal generator according to the present invention, FIG. 2 is a circuit diagram showing details of the reference oscillation circuit of the same embodiment, and FIGS. 3 and 4 are FIGS. 5 and 6 are block configuration diagrams showing a high group frequency divider circuit of the same embodiment and timing diagrams for explaining its operation, respectively, and FIGS. 7 is a block diagram showing the high group cosine wave generation circuit of the same embodiment, and FIG. 8 is a circuit showing details of the switch circuit of the high group cosine wave generating circuit. Configuration diagram, Figures 9 and 10
The figures are timing diagrams for explaining the operation of the high-group cosine wave generation circuit, respectively, and FIGS. 11 and 12 are block diagrams showing the low-group cosine wave generation circuit of the same embodiment and their operations, respectively. Timing diagram for, 1st
3 is an explanatory diagram of a conventional cosine wave generation circuit, FIGS. 14 and 15 are a block diagram showing a modified example of the low group cosine wave generation circuit, and a timing diagram for explaining its operation, and FIG. 16 17 is a block diagram showing a modified example of the high group cosine wave generation circuit, FIG. 17 is a block circuit diagram showing the output synthesis circuit of the same embodiment, and FIG. 18 is a block circuit diagram showing a conventional output synthesis circuit. FIGS. 19 to 23 are block circuit configuration diagrams showing other examples of the output synthesis circuit of the same embodiment. DESCRIPTION OF SYMBOLS 11... Reference oscillation circuit, 12... Key input interface circuit, 13... High group frequency dividing circuit, 14... Low group frequency dividing circuit, 15... Key operation section, 16... High Group cosine wave generation circuit, 17... Low group cosine wave generation circuit, 18... Output synthesis circuit, 19... Output terminal, 20
... 4-bit shift counter circuit, 2... Programmable state detection circuit, 22... Binary counter circuit, 23... Output terminal, 24... 6-bit shift counter circuit, 25... Programmer sol state detection circuit,
26... R-8FF circuit, 27... Output terminal, 28
...9-bit shift counter/recircuit, 29...NOR
Circuit, 30... Output terminal, 31... Switch, 32
...Reference voltage generation circuit, 33...Input terminal, 34.
...P channel MO8) transistor, 35...inverter, 36...P channel MO8) transistor, 37
... Output terminal, 38... 8-bit shift counter circuit, 39... Resistor, 40... Frequency divider circuit, 41...
- Input terminal, 42... Switch circuit, 43... Power supply terminal, 44... High group level conversion circuit, 45... Input terminal, 46... Switch circuit, 47... Power supply terminal,
48... Low group level conversion circuit, 49.50... Buffer amplifier, 51... Power supply terminal, 52 Output terminal, 53...
・Mixing circuit, 54.55... Input terminal, 56.
...Output terminal, 57.58...Input terminal, 59...
Amplifier, 60... Output terminal, 61 t 62... Integrating circuit, 63... Amplifier, 64.65... Input terminal, 66.67... Source follower ° circuit ζ6"8...
・Amplifier, 69... Source follower circuit, 70...
amplifier. 53- Figure 17 Figure 18 (a) (b)

Claims (1)

[Claims] Frequency division and sine wave generation means that divides the reference frequency signal into two standard frequencies in accordance with the type of operated key, and generates a sine wave signal having a period approximately equal to the frequency division period; , and a DTMF signal generating means for combining both signals outputted from the sine wave generating means and transmitting the obtained DTMF signal to all telephone lines, the circuit for generating the reference frequency signal (i-
The structure includes an MO8 type semiconductor element and a natural vibration element, and the oscillation frequency is set near k 480 [kHz], and the 480 [kHz] is set in the vicinity of the frequency dividing means.
D characterized in that the reference frequency signal in the vicinity of D is provided by a frequency division ratio that can divide the reference frequency signal to the standard frequency.
TMF signal generator.